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EEC 483 Computer Organization
Chapter 4.7 Data Hazards, Forwarding and Stalling
Chansu Yu
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5-Stage Pipeline
Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
Instructions and datamove generally fromleft to right throughthe five stages as theycomplete execution “except two cases”.
- WB stage- PC selection at MEM stage
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Pipeline Complexities
Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
Assume $2=2222,$3=3333,…
add $5, $2, $3sub $6, $5, $2
beq $7, labeladd $1, $2, $3add $4, $5, $6label:sub $7, $8, $9
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Hazards
Hazard= when an instruction’s stage is unable to execute during the current cycle.
Forced to stall (delay) the pipeline:1Instructions Time Step (Clock Cycle)
IF1
2 ID2IF3 EX
3IDIF WB
5MEMEX4
MEM4
EXIDIF ID6WBMEMEX7 WBMEM8 WB9Stall Instruction #2 stage 3unable to continue.
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Hazard Types
� Structural hazards : Necessary functional unit is busy� suppose we had only one memory� we already remove this type of hazards
� Control hazards : Next instruction address unknown� need to worry about branch instructions
� Data hazards : Source data not yet available� an instruction depends on a previous instruction
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Structural Hazards
A needed functional unit is busy executing a previous instruction.
1Instructions Time Step (Clock Cycle)IF12 ID
2IF3 EX3ID IFWB
5MEM EXMEM4EX ID6WB MEM7 WB8 9Stall Stall
Example:– Our sample MIPS pipeline has none.– What if PC+4 computation used main ALU instead of separate adder?
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Structural Hazards: Avoiding
� Add or replicate functional units.� Usually easy in modern processors (lots of hardware real estate).� Our sample pipeline avoids all structural hazards.
� Load/store architecture� Avoids structural hazards by limiting memory access only to load and store instructions� “sub $1, 200($10)”� IF – ID – EX (Addr. Comp.) – MEM – “EX (subtraction)” – WB� One more stage (EX) between MEM/WB with additional ALU is not a big
problem� But all other instructions should be wasting a clock since they need to execute the same number of stages
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*Graphically Representing Pipelines
�Can help with answering questions like:�how many cycles does it take to execute this code?
�what is the ALU doing during cycle 4?
�use this representation to help understand datapaths
IM Reg DM Reg
IM Reg DM Reg
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
lw $10, 20($1)
Program execution order (in instructions)
sub $11, $2, $3
ALU
ALU
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Data Hazards
�Needed data still being computed by previous instruction
sub $2, $1, $3and $12, $2, $5or $13, $6, $2add $14, $2, $2sw $15, 100($2)
Assume $1=10,$2=10, $3=30
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� Problem with starting next instruction before first is finished� dependencies that “go backward in time” are data hazards
Data Hazards: Dependencies
IM Reg
IM Reg
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
sub $2, $1, $3
Program execution order (in instructions)
and $12, $2, $5
IM Reg DM Reg
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9
10 10 10 10 10/– 20 – 20 – 20 – 20 – 20
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
Value of register $2:
DM Reg
Reg
Reg
Reg
DM
“and” has a problem“or” has a problem“add” ???“sw” is OK
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� Have compiler guarantee no hazards
� Where do we insert the “nops” ?sub $2, $1, $3and $12, $2, $5or $13, $6, $2add $14, $2, $2sw $15, 100($2)
� Or, detect and “stall” the pipeline
� Problem: this really slows us down!
Data Hazards: Software Solution
Is compiler dependent on machine (CPU)?⇒A LOT !!!(because it is supposedto generate machine code)⇒CPU designer & compiler designer shouldwork together.
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Data Hazards: Forwarding
sub $2,$1,$3 IFand $12,$2,$5
IDIF EXIDWBEXStall MEMStall MEM WBWhile result not written back until WB:sub $2,$1,$3 IFand $12,$2,$5
IDIF EXID WBEX MEM MEM WBIt is calculated earlier – in EX:Add forwarding hardware to allow, e.g., EX’s output (located in EX/MEM pipeline register) to be EX’s input.
Actually available after EX stage (not WB)
Actually needed at EX stage (not ID)
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Forwarding : All 2 Cases
IM Reg
IM Reg
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6
Time (in clock cycles)
sub $2, $1, $3
Program execution order (in instructions)
and $12, $2, $5
IM Reg DM Reg
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9
10 10 10 10 10/– 20 – 20 – 20 – 20 – 20
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
Value of register $2 :
DM Reg
Reg
Reg
Reg
X X X – 20 X X X X XValue of EX/MEM :X X X X – 20 X X X XValue of MEM/WB :
DM
“and” has a problem-> fixed
“or” has a problem-> fixed
“add” ??? -> OK“sw” is OK
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Forwarding : Implementation
sub $2,$1,$3IFand $12,$2,$5
IDIF EXID WBEX MEM MEM WBRead registers rs($1) and rt($3), but just pass rd($2)
Calculate ALU output= $1+$3Write to register rd($3) with ALU output
Read registers rs($2) and rt($5)
Calculate ALU output=$2+$5
If they match, we needto feed the result directly.- How to detect ?
=> control- How to feed ?
=> datapath
Write to register rd($12) with ALU output
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Forwarding : Implementation
Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX Additional datapathfor forwarding ?
How to control theforwarding datapth ?
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Data Hazards (again)
�Needed data still being computed by previous instruction
sub $11, $3, $2and $12, $11, $4or $13, $6, $11add $14, $8, $9sw $15, 100($2)
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
(d)
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(i)
(k)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
sub $11, $3, $2
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
sub $11, $3, $2
Rs=3
(a)
(c)
(b)
(f)
(g)
(h)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
and $12, $11, $4
Rd=11
$Rs=300
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
or $13, $6, $11
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
sub $11, $3, $2and $12, $11, $4
Rs=11
Rd=12
$Rs=???
???
???
Rd=11
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
or $13, $6, $11
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
sub $11, $3, $2and $12, $11, $4
Rs=11
Rd=12
$Rs=1100
300
100
Rd=11
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
add $14, $8, $9
(d)
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(i)
(k)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
or $13, $6, $11 sub $11, $3, $2and $12, $11, $4
???
Rd=12 Rd=11
???
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
add $14, $8, $9
(d)
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(i)
(k)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
or $13, $6, $11 sub $11, $3, $2and $12, $11, $4
100
Rd=12 Rd=11
100
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Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX
sw $15, 100($2)
(d)
(a)
(c)
(b)
(e)
(f)
(g)
(h)
(i)
(k)
(l)
(j) (m)
(n)
(o)
(p)
(q)
(r)
(s)
(t)
(u)
(v)
(w)
(x) (y)
(z)
(f)
(g)
add $14, $8, $9 or $13, $6, $11 sub $11, $3, $2and $12, $11, $4
???
Rd=11
???
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Forwarding : Implementation
Instruction memory
Address
4
32
0
Add Add result
Shift left 2
Inst
ruct
ion
IF/ID EX/MEM MEM/WB
M u x
0
1
Add
PC
0
Address
Write data
M u x
1Registers
Read data 1
Read data 2
Read register 1
Read register 2
16Sign
extend
Write register
Write data
Read data
Data memory
1
ALU result
M u x
ALUZero
ID/EX Additional datapathfor forwarding ?
How to control theforwarding datapth ?
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Forwarding : Forwarding Unit
PCInstruction
memory
Registers
M u x
M u x
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
Data memory
M u x
Forwarding unit
IF/IDIn
stru
ctio
n
M u x
RdEX/MEM.RegisterRd
MEM/WB.RegisterRd
Rt
Rt
Rs
IF/ID.RegisterRd
IF/ID.RegisterRt
IF/ID.RegisterRt
IF/ID.RegisterRs
Forwarding unit:6-input, 2-output combinational circuit
HW#1, (5)
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Forwarding : Other Case� Use temporary results, don’t wait for them to be written� Register file forwarding to handle read/write to same register� ALU forwarding� In the previous example, � EX/MEM.Rd = ID/EX.Rs� How about “EX/MEM.Rd = ID/EX.Rt” ?� They are the case: EX/MEM → EX: Forwarding to the next instruction� Anything more?� In MIPS pipeline, one more forwarding case:� MEM/WB → EX: Forwarding to the instruction after the next.� sub $2, $1, $3and $12, $2, $5or $13, $6, $2� MEM/WB.Rd = ID/EX.Rs and MEM/WB.Rd = ID/EX.Rt
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Forwarding Control
�Control logic�ForwardA = � 10 if (EX/MEM.Rd = ID/EX.Rs) <- get operand from EX/MEM� 01 if (MEM/WB.Rd = ID/EX.Rs) <- get operand from MEM/WB� 00, otherwise <- get operand from ID/EX
�ForwardB =� 10 if (EX/MEM.Rd = ID/EX.Rt) <- get operand from EX/MEM� 01 if (MEM/WB.Rd = ID/EX.Rt) <- get operand from MEM/WB� 00, otherwise <- get operand from ID/EX
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Forwarding Control
� RegWrite must be active & dest. reg. is not $0� Control logic� ForwardA = � 10 if ((EX/MEM.Rd = ID/EX.Rs) && EX/MEM.RegWrite &&
(EX/MEM.Rd ≠ 0))� 01 if ((MEM/WB.Rd = ID/EX.Rs) && MEM/WB.RegWrite && (MEM/WB.Rd ≠ 0))� 00, otherwise� ForwardB =� 10 if ((EX/MEM.Rd = ID/EX.Rt) && EX/MEM.RegWrite && (EX/MEM.Rd ≠ 0))� 01 if ((MEM/WB.Rd = ID/EX.Rt) && MEM/WB.RegWrite && (MEM/WB.Rd ≠ 0))� 00, otherwise
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Forwarding Control� Control logic� ForwardA = � 10 if ((EX/MEM.Rd = ID/EX.Rs) && EX/MEM.RegWrite && (EX/MEM.Rd ≠ 0))� 01 if ((MEM/WB.Rd = ID/EX.Rs) && MEM/WB.RegWrite && (MEM/WB.Rd≠ 0))� 00, otherwise� If a list of codes is � Add $1, $2, $3 : at WB -> MEM/WB.Rd=1� Add $1, $1, $4 : at MEM -> EX/MEM.Rd=1� Add $1, $1, $5 : at EX -> ID/EX.Rs=1� When the third inst. is at EX stage, the two conditions are all met. Then, ForwardA=10 or 01???� Should be forwarded from the most recent result, which is “10”� Therefore, ForwardA=01 � if ((MEM/WB.Rd = ID/EX.Rs) && MEM/WB.RegWrite && (MEM/WB.Rd≠ 0) && (EX/MEM.Rd ≠ ID/EX.Rs))
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Forwarding Control
� RegWrite must be active & dest. reg. is not $0� Control logic� ForwardA = � 10 if ((EX/MEM.Rd = ID/EX.Rs) && EX/MEM.RegWrite &&
(EX/MEM.Rd ≠ 0))� 01 if ((MEM/WB.Rd = ID/EX.Rs) && MEM/WB.RegWrite && (MEM/WB.Rd ≠ 0) && (EX/MEM.Rd ≠ ID/EX.Rs))� 00, otherwise� ForwardB =� 10 if ((EX/MEM.Rd = ID/EX.Rt) && EX/MEM.RegWrite && (EX/MEM.Rd ≠ 0))� 01 if ((MEM/WB.Rd = ID/EX.Rt) && MEM/WB.RegWrite && (MEM/WB.Rd ≠ 0) && (EX/MEM.Rd ≠ ID/EX.Rt)))� 00, otherwise
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Forwarding : Forwarding Unit
PCInstruction
memory
Registers
M u x
M u x
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
Data memory
M u x
Forwarding unit
IF/ID
Inst
ruct
ion
M u x
RdEX/MEM.RegisterRd
MEM/WB.RegisterRd
Rt
Rt
Rs
IF/ID.RegisterRd
IF/ID.RegisterRt
IF/ID.RegisterRt
IF/ID.RegisterRs
Forwarding unit:6-input, 2-output combinational circuit
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Where does ALUSrc go?
ALU
Reg. file
Forwarding from MEM/WBForwarding from EX/MEM
Reg. file
Forwarding from MEM/WBForwarding from EX/MEM
ALU
16-bit offset from instruction(lw, sw instruction)
ALUSrc
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Data Hazards: All Considered ???
lw $s5,0($s4)
add $s7,$s5,$s6
IDIFIF ID WBEX EX MEM WBMEMStall…especially when we remember that memory access is really often much longer than a single cycle: Stall Stall…but it doesn’t eliminate all data hazards:lw $s5,0($s4)
add $s7,$s5,$s6
IDIFIF ID WBEX EX MEM WBMEMStall
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Data Hazards: Stalling
� Stall the pipeline by keeping an instruction in the same stage
lw $2, 20($1)
Programexecutionorder(in instructions)
and $4, $2, $5
or $8, $2, $6
add $9, $4, $2
slt $1, $6, $7
Reg
IM
Reg
Reg
IM DM
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6Time (in clock cycles)
IM Reg DM RegIM
IM DM Reg
IM DM Reg
CC 7 CC 8 CC 9 CC 10
DM Reg
RegReg
Reg
bubble
lw-andlw-orAt CC5, MEM stage is empty !!!
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Data Hazards: Stalling
�Stalling detection and control�Detects during the ID stage when “lw” instruction is in EX
stage� The following two instructions are in ID (“and”) and IF (“or”) stages, respectively
� If detected, � Stall the following instruction (in ID stage, “and”) so that it repeats the ID stage again => IF/ID pipeline register should not be changed� Stall the second instruction (in IF stage, “or”) so that it repeats the IF stage again => PC should not be changed
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Data Hazards: Stalling
� Hazard detection� If (ID/EX.MemRead and ((ID/EX.Rt = IF/ID.Rs) or (ID/EX.Rt = IF/ID.Rt)) stall the pipeline
� Control signals generated from hazard detection unit� IF/IDWrite to prevent IF/ID register from changing� PCWrite to prevent PC from changing� MUX control to delay forwarding control signals (pass “null” signals)
lw
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Stalling: Detection Unit
� Stall by letting an instruction that won’t write anything go forward
PCInstruction
memory
Registers
M u x
M u x
M u x
Control
ALU
EX
M
WB
M
WB
WB
ID/EX
EX/MEM
MEM/WB
Data memory
M u x
Hazard detection
unit
Forwarding unit
0
M u x
IF/ID
Inst
ruct
ion
ID/EX.MemRead
IF/ID
Writ
e
PC
Writ
e
ID/EX.RegisterRt
IF/ID.RegisterRd
IF/ID.RegisterRt
IF/ID.RegisterRt
IF/ID.RegisterRs
RtRs
Rd
Rt EX/MEM.RegisterRd
MEM/WB.RegisterRdHazard detection unit:4-input, 3-output combinational circuit
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Stalling: What happen in the pipleine?
lw $s5,0($s4)
add $s7,$s5,$s6
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM No EX stage
No MEM stage
IF ID EX MEM WBNo WB stage
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
ID stage is repeated at CC7<- IF/ID.Write
IF stage is repeated at CC7<- PCWrite
No EX at CC7, no MEM at CC8 and no WB at CC9
<- zero control signals
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Stalling: What happen in the pipleine?
�What does the pipeline do?�What does EX stage do at CC7?� simple add (ALUop1/ALUop0=00)
�What does MEM stage do at CC8?� No MemRead/MemWrite (zero control signals)
�What does WB stage do at CC9?� No RegWrite (zero control signals)
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Data Hazards: Stalling
�Data forwarding for stalled instructions�They are needed; otherwise, we need one more stall cycle� “and” – forwarding to EX stage from WB stage (MEM/WB
pipeline register)� “or” – no forwarding is required
�Then, is this forwarding already covered? � It seems not because there is no “Rd” for lw instruction� But, it is covered because “Rd” actually means destination register among Rd and Rt, selected at EX stage
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Data Hazards: Stalling� Any problems with� Example 1lw $1, 100($2)Or $1, $1, $6Sub $1, $1, $1� Example 2lw $1, 100($2)lw $1, 200($1)Sub $1, $1, $4
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Data hazards: Stalling & Forwarding
lw $1,100($2)
or $1,$1,$6
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
Hazard detection (at CC6):If (ID/EX.MemRead and ((ID/EX.Rt = IF/ID.Rs) or (ID/EX.Rt = IF/ID.Rt)) stall the pipeline
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Data hazards: Stalling & Forwarding
lw $1,100($2)
or $1,$1,$6
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
Forwarding (at CC8):ForwardA = 01 if ((MEM/WB.Rd = ID/EX.Rs) && … (EX/MEM.Rd ≠ ID/EX.Rs))
Rt or Rd???
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Data hazards: Stalling & Forwarding
lw $1,100($2)
or $1,$1,$6
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
What happens to “sub” instruction?
sub $1,$1,$1 ???
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Data hazards: Stalling & Forwarding
lw $1,100($2)
lw $1,200($4)
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
Hazard detection (at CC6):If (ID/EX.MemRead and ((ID/EX.Rt = IF/ID.Rs) or (ID/EX.Rt = IF/ID.Rt)) stall the pipeline ???
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Data hazards: Stalling & Forwarding
lw $1,100($2)
lw $4,200($1)
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
Hazard detection (at CC6):If (ID/EX.MemRead and ((ID/EX.Rt = IF/ID.Rs) or (ID/EX.Rt = IF/ID.Rt)) stall the pipeline
Forwarding (at CC8):ForwardA = 01 if ((MEM/WB.Rd = ID/EX.Rs) && … (EX/MEM.Rd ≠ ID/EX.Rs))
[email protected]
Data hazards: Stalling & Forwarding
lw $1,100($2)
lw $1,200($1)
IDIFIF ID WBEX EX MEM WBMEMStall(ID)IF ID EX MEM WBStall(IF) IF ID EX MEM WBIDIF WBEX MEMIDIF WBEX MEMIDIF WBEX MEM
IF ID EX MEM WB
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12
sub $1,$1,$4 ???
Hazard detection (at CC6):If (ID/EX.MemRead and ((ID/EX.Rt = IF/ID.Rs) or (ID/EX.Rt = IF/ID.Rt)) stall the pipeline
Forwarding (at CC8):ForwardA = 01 if ((MEM/WB.Rd = ID/EX.Rs) && … (EX/MEM.Rd ≠ ID/EX.Rs))
What else?
