Embedded System Design

Embedded System Design

Modeling, Synthesis and Verification

Daniel D. Gajski • Samar AbdiAndreas Gerstlauer • Gunar Schirner

All rights reserved.

10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connectionwith any form of information storage and retrieval, electronic adaptation, computer software, or by similaror dissimilar methodology now known or hereafter developed is forbidden.The use in this publication of trade names, trademarks, service marks, and similar terms, even if they arenot identified as such, is not to be taken as an expression of opinion as to whether or not they are subjectto proprietary rights.

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This work may not be translated or copied in whole or in part without the written

permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY

Springer Dordrecht Heidelberg London New York

© Springer Science+Business Media, LLC 2009

Springer is part of Springer Science+Business Media (www.springer.com)

ISBN 978-1-4419-0503-1 e-ISBN 978-1-4419-0504-8DOI 10.1007/978-1-4419-0504-8

Library of Congress Control Number: 20099931042

2010, AIR Bldg.

Computer Engineering

1 University Station C0803

USA

Daniel D. Gajski

University of California, IrvineCenter for Embedded Computer Systems

Irvine, CA 92697-2620USA gajski@uci.edu

2010, AIR Bldg.University of California, IrvineCenter for Embedded Computer Systems

Irvine, CA 92697-2620USA

Samar Abdi

sabdi@uci.edu

Andreas Gerstlauer

University of Texas at Austin

Department of Electrical &

Austin, TX 78712

gerstl@ece.utexas.edu

2010, AIR Bldg.University of California, IrvineCenter for Embedded Computer Systems

Irvine, CA 92697-2620USA

Gunar Schirner

hschirne@uci.edu

Preface

RATIONALEIn the last twenty five years, design technology, and the EDA industry in partic-ular, have been very successful, enjoying an exceptional growth that has beenparalleled only by advances in semiconductor fabrication. Since the designproblems at the lower levels of abstraction became humanly intractable andtime consuming earlier then those at higher abstraction levels, researchers andthe industry alike were forced to devote their attention first to problems suchas circuit simulation, placement, routing and floorplanning. As these prob-lems become more manageable, CAD tools for logic simulation and synthesiswere developed successfully and introduced into the design process. As de-sign complexities have grown and time-to-market have shrunk drastically, bothindustry and academia have begun to focus on levels of design that are evenhigher then layout and logic. Since higher levels of abstraction reduce by anorder of magnitude the number of objects that a designer needs to consider, theyhave allowed industry to design and manufacture complex application-orientedintegrated circuits in shorter periods of time.

Following in the footsteps of logic synthesis, register-transfer and high-levelsynthesis have contributed to raising abstraction levels in the design method-ology to the processor level. However, they are used for the design of a sin-gle custom processor, an application-specific or communication component oran interface component. These components, along with standard processorsand memories, are used as components in systems whose design methodol-ogy requires even higher levels of abstraction: system level. A system-leveldesign focuses on the specification of the systems in terms of some modelsof computations using some abstract data types, as well as the transformationor refinement of that specification into a system platform consisting of a setof processor-level components, including generation of custom software andhardware components. To this point, however, in spite of the fact that sys-

vi EMBEDDED SYSTEM DESIGN:

tems have been manufactured for years, industry and academia have not beensufficiently focused on developing and formalizing a system-level design tech-nology and methodology, even though there was a clear need for it. This needhas been magnified by appearance of embedded systems, which can be usedanywhere and everywhere, in plains, trains, houses, humans, environment, andmanufacturing and in any possible infrastructure. They are application specificand tightly constrained by different requirements emanating from the environ-ment they operate in. Together with ever increasing complexities and marketpressures, this makes their design a tremendous challenge and the developmentof a clear and well-defined system-level design technology unavoidable.

There are two reasons for emphasizing more abstract, system-level method-ologies. The first is the fact that high-level abstractions are closer to a designer’susual way of reasoning. It would be difficult to imagine, for example, how adesigner could specify, model and communicate a system design by means ofa schematic or hundred thousand lines of VHDL or Verilog code. The morecomplex the design, the more difficult it is for the designer to comprehend itsfunctionality when it is specified on register-transfer level of abstraction. Onthe other hand, when a system is described with an application-oriented modelof computation as a set of processes that operate on abstract data types andcommunicate results through abstract channels, the designer will find it mucheasier to specify and verify proper functionality and to evaluate various imple-mentations using different technologies. The second reason is that embeddedsystem are usually defined by the experts in application domain who understandapplication very well, but have only basic knowledge of design technology andpractice. System-level design technology allows them to specify, explore andverify their embedded system products without expert knowledge of systemengineering and manufacturing.

It must be acknowledged that research on system design did start many yearsago; at the time, however, it remained rather focused to specific domains andcommunities. For example, the computer architecture community has consid-ered ways of partitioning and mapping computations to different architectures,such as hypercubes, multiprocessors, massively parallel or heterogeneous pro-cessors. The software engineering community has been developing methodsfor specifying and generating software code. The CAD community has focusedon system issues such as specification capture, languages, and modeling. How-ever, simulation languages and models are not synthesizable or verifiable forlack of proper design meaning and formalism. That resulted in proliferationof models and modeling styles that are not useful beyond the modeler’s team.By introduction of well-defined model semantics, and corresponding modeltransformations for different design decision, it is possible to generate modelsautomatically. Such models are also synthesizable and verifiable. Furthermore,model automation relieves designers from error-prone model coding and even

PREFACE vii

learning the modeling language. This approach is appealing to application ex-perts since they need to know only the application and experiment with a set ofdesign decisions. Unfortunately, a universally accepted theoretical frameworkand CAD environments that support system design methodologies based onthese concepts are not commercially available yet, although some experimentalversions demonstrated several orders of magnitude productivity gain. On theother hand, embedded-system design-technology based on these concepts hasmatured to the point that a book summarizing the basic ideas and results devel-oped so far will help students and practitioners in embedded system design.

In this book, we have tried to include ideas and results from a wide varietyof sources and research projects. However, due to the relative youth of thisfield, we may have overlooked certain interesting and useful projects; for thiswe apologize in advance, and hope to hear about those projects so they maybe incorporated into future editions. Also, there are several important system-level topics that, for various reasons, we have not been able to cover in detailhere, such as testing and design for test. Nevertheless, we believe that a bookon embedded system techniques and technology will help upgrade computerscience and engineering education toward system-level and toward applicationoriented embedded systems, stimulate design automation community to movebeyond system level simulation and develop system-level synthesis and verifi-cation tools and support the new emerging embedded application communityto become more innovative and self-sustaining.

AUDIENCEThis book is intended for four different groups within the embedded systemcommunity. First, it should be an introductory book for application-productdesigners and engineers in the field of mechanical, civil, bio-medical, electri-cal, and environmental, energy, communication, entertainment and other ap-plication fields. This book may help them understand and design embeddedsystems in their application domain without an expert knowledge of systemdesign methods bellow system-level. Second, this book should also appeal tosystem designers and system managers, who may be interested in embeddedsystem methodology, software-hardware co-design and design process man-agement. They may use this book to create a new system level methodology orto upgrade one existing in their company. Third, this book can also be used byCAD-tool developers, who may want to use some of its concepts in existing orfuture tools for specification capture, design exploration and system modeling,synthesis and verification. Finally, since the book surveys the basic conceptsand principles of system-design techniques and methodologies, including soft-ware and hardware, it could be valuable to advanced teachers and academic

viii EMBEDDED SYSTEM DESIGN:

programs that want to teach software and hardware concepts together insteadof in non-related courses. That is particularly needed in today’s embeddedsystems where software and hardware are interchangeable. From this point,the book would also be valuable for an advanced undergraduate or graduatecourse targeting students who want to specialize in embedded system, designautomation and system design and engineering. Since the book covers multi-ple aspects of system design, it would be very useful reference for any seniorproject course in which students design a real prototype or for graduate projectfor system-level tool development.

ORGANIZATIONThis book has been organized into eight chapters that can be divided into fourparts. Chapter 1 and 2 present the basic issues in embedded system designand discuss various system-design methodologies that can be used in capturingsystem behavior and refining it into system implementation. Chapter 3 and 4deal with different models of computations and system modeling at differentlevels of abstraction as well as system synthesis from those models. Chapter 5,6, and 7 deal with issues and possible solutions in synthesis and verificationof software and hardware component needed in a embedded system platform.Finally, Chapter 8 reviews the key developments and selected current academicand commercial tools in the field of system design, system software and systemhardware as well as case study of embedded system environments.

Given an understanding of the basic concepts defined in Chapter 1 and 2,each chapter should be self-contained and can be read independently. We haveused the same writing style and organization in each chapter of the book. Atypical chapter includes an introductory example, defines the basic concepts, itdescribes the main problems to be solved. It contains a description of severalpossible solutions, methods or algorithms to the problems that have been posed,and explains the advantages and disadvantages of each approach. Each chapteralso includes relationship to previously published work in the field and discussessome open problems in each topic.

This book could be used in several different courses. One course would befor application experts with only a basic knowledge of computers engineering.It would emphasize application issues, system specification in application ori-ented models of computation, system modeling and exploration as presentedin Chapter 1 - 4. The second course for embedded system designers wouldemphasize system languages, specification capture, system synthesis and veri-fication with emphasis on Chapter 3, Chapter 4, and Chapter 7. The third coursemay emphasize system development with component synthesis and tools as de-scribed in Chapter 5 - Chapter 8. In which ever it is used, though, we feel that

PREFACE ix

this book will help to fill the vacuum in computer science and engineering cur-riculum where there is need and demand for emphasis on teaching embeddedsystem design techniques in addition to supporting lower levels of abstractiondealing with circuit, logic and architecture design.

We hope that the material selection and the writing style will approach yourexpectations; we welcome your suggestions and comments.

Daniel Gajski, Andreas Gerstlauer, Samar Abdi, Gunar Schirner

Acknowledgments

This book was in the making for many years: from concepts to methodologiesto experiments. Many generations of researchers at the Center for EmbeddedSystems at UCI participated in finding and proving what works and what doesnot. We would like to thank the members of the first generation that establishedbasic principles of embedded systems: Frank Vahid, Sanjiv Narayan, Jie Gongand Smita Bakshi. We would also like to acknowledge the second generationthat brought us SpecC and System on Chip Environment: Jianwen Zhu, RainerDoemer, Lukai Cai, Haobo Yu, Sequin Zhao, Dongwan Shin, and Jerry Peng.And the third generation that made Embedded System Environment available:Lochi Yu, Hansu Cho, Yongyun Hwang, Ines Viskic. In addition, we would liketo acknowledge the NISC team: Mehrdad Reshadi, Bita Gorjiara and JelenaTrajkovic for their high-level synthesis contributions and Pramod Chandrariafor his work on design drivers.

We would also like to thank Quoc-Viet Dang, who helped us with bookformatting, figure creation, generation, and without whom this book would notbe possible. We also want to thank our editors Matt Nelson and Brian Thillwho made the sentences readable and ideas flow without interruptions. We alsowant to thank Simone Lacina from grafikdesign-lacina.de for an excellent andartistic cover.

However, the highest credits go to Grace Wu and Melanie Kilian for makingour center work flawlessly while we were working and thinking about the book.

Last but not the least, we would like to thank Carl Harris from Springerfor encouragement and asking at every conference in the last 5 years the samequestion: "When is the Orange book coming?"

Contents

Preface vAcknowledgments xiList of Figures xixList of Tables xxv

1. INTRODUCTION 11.1 System-Design Challenges 11.2 Abstraction Levels 3

1.2.1 Y-Chart 31.2.2 Processor-Level Behavioral Model 51.2.3 Processor-level structural model 71.2.4 Processor-level synthesis 101.2.5 System-Level Behavioral Model 131.2.6 System Structural Model 141.2.7 System Synthesis 14

1.3 System Design Methodology 181.3.1 Missing semantics 201.3.2 Model Algebra 21

1.4 System-Level Models 231.5 Platform Design 271.6 System Design Tools 291.7 Summary 32

2. SYSTEM DESIGN METHODOLOGIES 352.1 Bottom-up Methodology 352.2 Top-down Methodology 372.3 Meet-in-the-middle Methodology 38

xiv EMBEDDED SYSTEM DESIGN:

2.4 Platform Methodology 402.5 FPGA Methodology 432.6 System-level Synthesis 442.7 Processor Synthesis 452.8 Summary 47

3. MODELING 493.1 Models of Computation 50

3.1.1 Process-Based Models 523.1.2 State-Based Models 58

3.2 System Design Languages 653.2.1 Netlists and Schematics 663.2.2 Hardware-Description Languages 663.2.3 System-Level Design Languages 68

3.3 System Modeling 683.3.1 Design Process 693.3.2 Abstraction Levels 71

3.4 Processor Modeling 723.4.1 Application Layer 733.4.2 Operating System Layer 753.4.3 Hardware Abstraction Layer 783.4.4 Hardware Layer 80

3.5 Communication Modeling 833.5.1 Application Layer 843.5.2 Presentation Layer 883.5.3 Session Layer 903.5.4 Network Layer 923.5.5 Transport Layer 933.5.6 Link Layer 943.5.7 Stream Layer 983.5.8 Media Access Layer 993.5.9 Protocol and Physical Layers 100

3.6 System Models 1023.6.1 Specification Model 1033.6.2 Network TLM 1043.6.3 Protocol TLM 1063.6.4 Bus Cycle-Accurate Model (BCAM) 1073.6.5 Cycle-Accurate Model (CAM) 108

Contents xv

3.7 Summary 109

4. SYSTEM SYNTHESIS 1134.1 System Design Trends 1144.2 TLM Based Design 1174.3 Automatic TLM Generation 120

4.3.1 Application Modeling 1224.3.2 Platform Definition 1234.3.3 Application to Platform Mapping 1244.3.4 TLM Based Performance Estimation 1264.3.5 TLM Semantics 130

4.4 Automatic Mapping 1324.4.1 GSM Encoder Application 1344.4.2 Application Profiling 1354.4.3 Load Balancing Algorithm 1384.4.4 Longest Processing Time Algorithm 142

4.5 Platform Synthesis 1464.5.1 Component data models 1474.5.2 Platform Generation Algorithm 1484.5.3 Cycle Accurate Model Generation 1514.5.4 Summary 152

5. SOFTWARE SYNTHESIS 1555.1 Preliminaries 156

5.1.1 Target Languages for Embedded Systems 1575.1.2 RTOS 159

5.2 Software Synthesis Overview 1625.2.1 Example Input TLM 1645.2.2 Target Architecture 166

5.3 Code Generation 1675.4 Multi-Task Synthesis 173

5.4.1 RTOS-based Multi-Tasking 1735.4.2 Interrupt-based Multi-Tasking 176

5.5 Internal Communication 1815.6 External Communication 182

5.6.1 Data Formatting 1835.6.2 Packetization 1855.6.3 Synchronization 1865.6.4 Media Access Control 191

xvi EMBEDDED SYSTEM DESIGN:

5.7 Startup Code 1935.8 Binary Image Generation 1945.9 Execution 1955.10Summary 196

6. HARDWARE SYNTHESIS 1996.1 RTL Architecture 2016.2 Input Models 204

6.2.1 C-code specification 2046.2.2 Control-Data Flow Graph specification 2056.2.3 Finite State Machine with Data specification 2076.2.4 RTL specification 2086.2.5 HDL specification 209

6.3 Estimation and Optimization 2116.4 Register Sharing 2166.5 Functional Unit Sharing 2206.6 Connection Sharing 2246.7 Register Merging 2276.8 Chaining and Multi-Cycling 2296.9 Functional-Unit Pipelining 2326.10Datapath Pipelining 2356.11Control and Datapath Pipelining 2376.12Scheduling 240

6.12.1RC scheduling 2436.12.2TC scheduling 244

6.13Interface Synthesis 2486.14Summary 253

7. VERIFICATION 2557.1 Simulation Based Methods 257

7.1.1 Stimulus Optimization 2607.1.2 Monitor Optimization 2627.1.3 SpeedUp Techniques 2637.1.4 Modeling Techniques 264

7.2 Formal Verification Methods 2657.2.1 Logic Equivalence Checking 2667.2.2 FSM Equivalence Checking 268

Contents xvii

7.2.3 Model Checking 2707.2.4 Theorem Proving 2737.2.5 Drawbacks of Formal Verification 2757.2.6 Improvements to Formal Verification Methods 2757.2.7 Semi-formal Methods: Symbolic Simulation 276

7.3 Comparative Analysis of Verification Methods 2767.4 System Level Verification 278

7.4.1 Formal Modeling 2807.4.2 Model Algebra 2827.4.3 Verification by Correct Refinement 283

7.5 Summary 285

8. EMBEDDED DESIGN PRACTICE 2878.1 System Level Design Tools 287

8.1.1 Academic Tools 2898.1.2 Commercial Tools 2968.1.3 Outlook 299

8.2 Embedded Software Design Tools 3008.2.1 Academic Tools 3018.2.2 Commercial Tools 3038.2.3 Outlook 305

8.3 Hardware Design Tools 3068.3.1 Academic Tools 3088.3.2 Commercial Tools 3148.3.3 Outlook 319

8.4 Case Study 3198.4.1 Embedded System Environment 3208.4.2 Design Driver: MP3 Decoder 3248.4.3 Results 327

8.5 Summary 333

References 335

Index 349

List of Figures

1.1 Y-Chart 31.2 FSMD model 51.3 CDFG model 61.4 Instruction-set flow chart 81.5 Processor structural model 91.6 Processor synthesis 111.7 System behavioral model 131.8 System structural model 151.9 System synthesis 161.10 Evolution of design flow over the past 50 years 171.11 Missing semantics 201.12 Model equivalence 221.13 SER Methodology 231.14 System TLM 251.15 System CAM 261.16 Platform architecture 281.17 General system environment 291.18 System tools 312.1 Bottom-up methodology 362.2 Top-down methodology 372.3 Meet-in-the-middle methodology (option 1) 392.4 Meet-in-the-middle methodology (option 2) 402.5 Platform methodology 412.6 System methodology 422.7 FPGA methodology 43

xx List of Figures

2.8 System-level synthesis 442.9 Processor synthesis 463.1 Kahn Process Network (KPN) example 543.2 Synchronous Data Flow (SDF) example 563.3 Finite State Machine with Data (FSMD) example 603.4 Hierarchical, Concurrent Finite State Machine (HCFSM) example 613.5 Process State Machine (PSM) example 643.6 System design and modeling flow 693.7 Model granularities 713.8 Processor modeling layers 733.9 Application layer 743.10 Operating system layer 753.11 Operating system modeling 763.12 Task scheduling 773.13 Hardware abstraction layer 793.14 Interrupt scheduling 803.15 Hardware layer 813.16 Application layer synchronization 863.17 Application layer storage 873.18 Application layer channels 883.19 Presentation layer 893.20 Session layer 913.21 Network layer 923.22 Communication elements 933.23 Link layer 953.24 Link layer synchronization 963.24 Link layer synchronization (con’t) 973.25 Media access layer 993.26 Protocol layer 1003.27 Physical layer 1013.28 System models 1023.29 Specification model 1043.30 Network TLM 1053.31 Protocol TLM 1063.32 Bus Cycle-Accurate Model (BCAM) 1073.33 Cycle-Accurate Model (CAM) 108

List of Figures xxi

3.34 Modeling results 1104.1 A traditional board-based system design process. 1144.2 A virtual platform based development environment. 1154.3 A model based development flow of the future. 1164.4 TLM based design flow. 1174.5 Modeling layers for TLM. 1184.6 System synthesis flow with given platform and mapping. 1204.7 A simple application expressed in PSM model of computation. 1224.8 A multicore platform specification. 1234.9 Mapping from application model to platform. 1244.10 Computation timing estimation. 1254.11 Communication timing estimation. 1284.12 Synchronization Modeling with Flags and Events. 1284.13 Automatically Generated TLM from system specification. 1314.14 System synthesis with fixed platform. 1334.15 Application example: GSM Encoder 1344.16 Application profiling steps. 1354.17 Profiled statistics of GSM encoder. 1374.18 Abstraction of profiled statistics into an application graph. 1384.19 Creation of platform graph. 1394.20 Flowchart of load balancing algorithm for mapping generation. 1404.21 Platform graph with communication costs. 1424.22 LPT cost function computation. 1434.23 Flowchart of LPT algorithm for mapping generation. 1454.24 System synthesis from application and constraints. 1464.25 Flowchart of a greedy algorithm for platform generation. 1494.26 Illustration of platform generation on a GSM Encoder example. 1504.27 Cycle accurate model generation from TLM. 1525.1 Synthesis overview 1555.2 Software synthesis flow 1635.3 Input system TLM example 1645.4 Generic target architecture 1665.5 Task specification 1695.6 Software execution stack for RTOS-based multi-tasking 1735.7 Multi-task example model 1755.8 Software execution stack for interrupt-based multi-tasking 177

xxii List of Figures

5.9 Interrupt-based multi-tasking example 1785.10 Internal communication 1815.11 External communication 1835.12 Marshalling example 1845.13 Packetization 1855.14 Chain for interrupt-based synchronization 1875.15 Events in interrupt-based synchronization 1885.16 Polling-based synchronization 1905.17 Events in polling-based synchronization 1905.18 Transferring a packet using bus primitives 1915.19 Binary image generation 1955.20 ISS-based Virtual platform 1966.1 HW synthesis design flow 1996.2 High-level block diagram 2016.3 RTL diagram with FSM controller 2026.4 RTL diagram with programmable controller 2036.5 CDFG for Ones counter 2066.6 FSMD specification 2076.7 RTL Specification 2086.8 Square-root algorithm (SRA) 2126.9 Gain in register sharing 2176.10 General partitioning algorithm 2186.11 Variable merging for SRA example 2196.12 SRA datapath with register sharing 2206.13 Gain in functional unit sharing 2216.14 Functional unit merging for SRA 2226.15 SRA design after register and unit merging 2246.16 SRA Datapath with labeled connections 2256.17 Connection merging for SRA 2276.18 SRA Datapath after connection merging 2276.19 Register merging 2286.20 Datapath schematic after register merging 2296.21 Modified FSMD models for SRA algorithm 2306.22 Datapath with chained functional units 2316.23 SRA datapath with chained and multi-cycle functional units 2326.24 Functional unit pipelining 234

List of Figures xxiii

6.25 Datapath pipelining 2366.26 Control and datapath pipelining 2396.27 C and CDFG 2416.28 ASAP, ALAP, and RC schedules for SRA 2436.29 RC algorithm 2456.30 TC algorithm 2456.31 ASAP, ALAP, and RC schedules for SRA 2466.32 Distribution graphs for TC scheduling of the SRA example 2476.33 HW Synthesis timing constraints 2496.34 FSMD for MAC driver 2506.35 Custom HW component with bus interface 2516.36 A typical bus protocol 2526.37 Transducer structure 2537.1 A typical simulation environment 2577.2 A test case that covers only part of the design. 2617.3 Coverage analysis results in a more useful test case. 2627.4 Graphical visualization of the design helps debugging. 2637.5 A typical emulation setup. 2637.6 Logic equivalence checking by matching of cones. 2667.7 DeMorgan’s law illustrated by ROBDD equivalence. 2677.8 Equivalence checking of sequential design using product FSMs. 2697.9 Product FSM for with a reachable error state. 2707.10 A typical model checking scenario. 2707.11 A computation tree derived from a state transition diagram. 2717.12 Various temporal properties shown on the computation tree. 2727.13 Proof generation process using a theorem prover. 2737.14 Associativity of parallel behavior composition. 2737.15 Basic laws for a theory of system models. 2747.16 Symbolic simulation of Boolean circuits. 2777.17 System level models. 2797.18 A simple hierarchical specification model. 2807.19 Behavior partitioning and the equivalence of models. 2807.20 Equivalence of models resulting from channel mapping. 2817.21 Model refinement using functionality preserving transformations.2848.1 Metropolis framework 2898.2 SystemCoDesigner tool flow 290

xxiv List of Figures

8.3 Daedalus tool flow 2928.4 PeaCE tool flow 2938.5 SCE tool flow 2958.6 NISC technology tools 3108.7 The SPARK Synthesis Methodology 3118.8 xPilot Synthesis System 3138.9 ESE tool flow 3208.10 System level design with ESE front end 3218.11 SW-HW synthesis with ESE back end 3238.12 MP3 decoder application model 3248.13 MP3 decoder platform SW+4 3268.14 Execution speed and accuracy trade-offs for embedded sys-

tem models 3288.15 MP3 manual design quality 3298.16 Automatically generated MP3 design quality 3308.17 Development productivity gains from model automation 3318.18 Validation productivity gain from using TLM vs. CAM 332

List of Tables

3.1 Processor models 823.2 Communication layers 844.1 A sample capacity table of platform components. 1476.1 Input logic table 2096.2 Output logic table 2096.3 Variable usage 2136.4 Operation usage 2146.5 SRA connectivity 2156.6 Connection usage table 2267.1 A comparison of various verification schemes. 278