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ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4...

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ENGR 303 – Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College
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Page 1: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

ENGR 303 – Introduction to Logic Design Lecture 4

Dr. Chuck BrownEngineering and Computer Information Science

Folsom Lake College

Page 2: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<2>

• Logic to Gates

• Karnaugh Maps (K-Maps)

Outline for Todays Lecture

ENGR 303

Page 3: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<3>

• Two-level logic: ANDs followed by ORs

• Example: Y = ABC + ABC + ABC

BA C

Y

minterm: ABC

minterm: ABC

minterm: ABC

A B C

From Logic to Gates

ENGR 303

Page 4: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<4>

• Inputs on the left (or top)

• Outputs on right (or bottom)

• Gates flow from left to right

• Straight wires are best

Circuit Schematics Rules

ENGR 303

Page 5: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<5>

A1

A0

0 00 11 01 1

Y3Y2

Y1

Y0A

3A2

0 00 00 00 0

0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

A0

A1

PRIORITY

CiIRCUIT

A2

A3

Y0

Y1

Y2

Y3

• Example: Priority Circuit

Output asserted

corresponding to

most significant

TRUE input

Multiple-Output Circuits

ENGR 303

Page 6: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<6>

0

A1

A0

0 00 11 01 1

0

00

Y3Y2

Y1

Y0

0000

0011

0100

A3

A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A0

A1

PRIORITY

CiIRCUIT

A2

A3

Y0

Y1

Y2

Y3

• Example: Priority Circuit

Output asserted

corresponding to

most significant

TRUE input

Multiple-Output Circuits

ENGR 303

Page 7: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<7>

A1

A0

0 00 11 01 1

0000

Y3Y2

Y1

Y0

0000

0011

0100

A3

A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A3A

2A

1A

0

Y3

Y2

Y1

Y0

Don’t Care Simplification

ENGR 303

A1

A0

0 00 11 XX X

0000

Y3Y2

Y1

Y0

0001

0010

0100

A3

A2

0 00 00 00 1

X X 1 0 0 01 X

But is there an easier way?

Page 8: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<8>

A1

A0

0 00 11 01 1

0000

Y3Y2

Y1

Y0

0000

0011

0100

A3

A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A1

A0

0 00 11 XX X

0000

Y3Y2

Y1

Y0

0001

0010

0100

A3

A2

0 00 00 00 1

X X 1 0 0 01 X

Don’t Cares

ENGR 303

Page 9: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<9>

• Boolean expressions can be minimized by combining terms

• E.g. Y=A’B’C’ + A’B’C -> A’B’(C’+C) -> Y=A’B’

• K-maps minimize equations graphically

Karnaugh Maps (K-Maps)

ENGR 303

A B C Y

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

A’B’C’ A’B’C A’BC A’BC’

AB’C’ AB’C ABC ABC’

A B’C’ B’C BC BC’

A’

A

BC

1 1 0 0

0 0 0 0

A 00 01 11 10

0

1

BC

Page 10: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<10>

• Circle 1’s in adjacent squares

• In Boolean expression, include only

literals whose true and complement form

are not in the circle

Y = A’B’

B C0 0

0 1

1 0

1 1

A0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

1

1

0

0

0

0

0

0

Y

K-Map

ENGR 303

1 1 0 0

0 0 0 0

A 00 01 11 10

0

1

BC

Page 11: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<11>

• Complement: variable with a bar over it

A, B, C

• Literal: variable or its complement

A, A, B, B, C, C

• Implicant: product of literals

ABC, AC, BC

• Prime implicant: implicant corresponding to the largest circle in a K-map

K-Map Definitions

ENGR 303

Page 12: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<12>

• Every 1 must be circled at least once

• Each circle must span a power of 2 (i.e. 1, 2, 4) squares in each direction

• Each circle must be as large as possible

• A circle may wrap around the edges

• A “don't care” (X) is circled only if it helps minimize the equation

K-Map Rules

ENGR 303

Page 13: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<13>

3-Input K-Map

ENGR 303

A B C Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 1

0 0 1 1

0 0 1 0

A 00 01 11 10

0

1

BC

A’B’C’ A’B’C A’BC A’BC’

AB’C’ AB’C ABC ABC’

A B’C’ B’C BC BC’

A’

A

BC

Y = A’B + BC

Page 14: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<14>

0

C D0 0

0 1

1 0

1 1

B0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

1

1

1

0

1

1

1

YA0

0

0

0

0

0

0

0

0 0

0 1

1 0

1 1

0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

4-Input K-Map

ENGR 303

00

1 0 1 1

0 1 1 1

0 0 0 0

1 1 0 1

ABCD

01 11 10

00

01

11

10

Y = A’C + A’BD + AB’C’ + B’D’

Page 15: ENGR 303 Introduction to Logic Design Lecture 4...ENGR 303 –Introduction to Logic Design Lecture 4 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

<15>

0

C D0 0

0 1

1 0

1 1

B0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

1

1

1

0

X

1

1

YA0

0

0

0

0

0

0

0

0 0

0 1

1 0

1 1

0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

X

X

X

X

X

X

K-Maps with Don’t Cares

ENGR 303

00

1 0 1 1

0 X 1 1

X X X X

1 1 X X

ABCD

01 11 10

00

01

11

10

Y = A + B’D’ + C


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