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ENGR 303 – Introduction to Logic Design Lecture 8 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College
ENGR 303 – Introduction to Logic Design Lecture 8
Dr. Chuck BrownEngineering and Computer Information Science
Folsom Lake College
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• Hardware Descriptive Language (HDL)– Verilog & VHDL
• Simulation/Synthesis• Logic, Numbers, Types, Operators• Module Structure• Bitwise/Reduction Operators• Conditional Assignment• Internal Variables• Precedence• Numbers• Bit manipulation
Outline for Todays Lecture
ENGR 303
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• Hardware description language (HDL): – specifies logic function only– Computer-aided design (CAD) tool produces or
synthesizes the optimized gates
• Most commercial designs built using HDLs• Two leading HDLs:
– Verilog & SystemVerilog• developed in 1984 by Gateway Design Automation• Verilog IEEE standard (1364) in 1995• SystemVerilog extended in 2005 (IEEE STD 1800-2009)
– VHDL 2008• Developed in 1981 by the Department of Defense• IEEE standard (1076) in 1987• Updated in 2008 (IEEE STD 1076-2008)
HDL Introduction
ENGR 303
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System Verilog – Logic & Numbers
ENGR 303
• Logic Values• 0 – logic zero, or false condition • 1 – logic 1, or true condition • x, X – unknown logic value • z, Z - high-impedance state
• Number formats • b, B binary • d, D decimal (default) • h, H hexadecimal • o, O octal
• 16’H789A – 16-bit number in hex format • 1’b0 – 1-bit logic zero
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System Verilog – Types
ENGR 303
• Constants• parameter DIME = 10; • parameter width = 32, nickel = 5;• parameter quarter = 8’b0001_1001;
• Nets (internal connections)• wire clock, reset_n; • wire[7:0] a_bus;
• Registers• reg clock, reset_n; • reg[7:0] a_bus;
• Integer – for use as general purpose variables in loops• integer n;
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System Verilog – Operators
ENGR 303
• Bitwise• ~ negation y = ~a;• & and y = a & b; • | inclusive or y = a | b; • ^ exclusive or y = a ^ b;
• Reduction - accept single bus and return single bit result• & and y = & a_bus; //true if all 1s• ~& nand y = ~&a_bus; //true if all 0s• | or y = | a_bus; //true if any 1s• ^ exclusive OR y = ^ a_bus; //true if odd #1s
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System Verilog – Operators cont’d
ENGR 303
• Relational (return 1 for true, 0 for false) • < less than <= less than equal• > greater than >= greater than equal
• Equality• == logical equality • != logical inequality
• Logical Comparison Operators• ! logical negation • && logical and • || logical or
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System Verilog – Operators cont’d
ENGR 303
• Arithmetic Operators• + addition• - subtraction• * multiplication
• Shift• << logical shift left (<<< arithmetic) • >> logical shift right (>>> arithmetic)
• Conditional – selects one of pair of expressions • ? : Logical expression before ? is evaluated • If true, expression before : is assigned to output • If false, expression after : is assigned to output• Y = (A > B) ? 1 : 0 • Y = (A == B) ? A + B : A – B
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ab yc
Verilog
Module
Two types of Modules:
– Behavioral: describes what a module does
– Structural: describes how a module can be built
from simpler modules (Hierarchical structure)
SystemVerilog Modules
ENGR 303
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module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Verilog module structure:
Behavioral – Combinatorial Example
• module/endmodule - required to begin/end of module• example - name of the module (must being with a letter)• assign - defines an operation• ; semicolon signifies the end of a statement
• Recall Logical Operators:~: NOT&: AND ~&: NAND|: OR ~|: NOR^: XOR ~^: XNOR
ENGR 303
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module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Verilog: input/outputs are 2-state; 0 & 1
Behavioral – Combinatorial Example
ENGR 303
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
SystemVerilog: adds logic data type; 0, 1, X, Z
• logic – reserved for SystemVerilog to specify extended data type
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• Case sensitive– Example: reset and Reset are not the same signal.
• Module names can’t start with numbers – 2mux is an invalid module name
• Whitespace ignored
• Comments:– // single line comment
– /* multiline
comment */
Verilog Syntax
ENGR 303
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• Simulation
– Inputs applied to circuit
– Outputs checked for correctness
– Time savings by debugging in simulation instead of
hardware
• Synthesis
– Transforms HDL code into a netlist describing the
hardware (i.e., a list of gates and the wires connecting
them)
IMPORTANT:
When using an HDL, think of the hardware the HDL
should produce
HDL to Gates
ENGR 303
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HDL Simulation
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Verilog:
ENGR 303
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un5_y
un8_y
y
yc
b
a
HDL Synthesis
module example(input a, b, c,
output y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
Verilog:
Synthesis:
ENGR 303
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module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
Buses & Bitwise OperatorsExample - 4-bite wide I/O buses
ENGR 303
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module and8(input [7:0] a,
output y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
// a[3] & a[2] & a[1] & a[0];
endmodule
Reduction OperatorsA means to operate on the entire bus
ENGR 303
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module mux2(input [3:0] d0, d1,
input s,
output [3:0] y);
assign y = s ? d1 : d0;
endmodule
// y equals d1 if S is true or 1, else y = d0
// if S is false or 0
? : is also called a ternary operator because it
operates on 3 inputs: s, d1, and d0.
Conditional AssignmentExample - 4-bit 2 to 1 Mux
ENGR 303
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module fulladder(input a, b, cin,
output s, cout);
wire p, g; // internal nodes
assign p = a ^ b;
assign g = a & b;
assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule
p
g s
un1_cout cout
cout
s
cin
b
a
Net - Internal VariablesVerilog data object wire
ENGR 303
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module fulladder(input a, b, cin,
output s, cout);
wire p, g, un1_cout;
xor (p,a,b); // logical xor operator
and (g,a,b); // logical and operator
and (un1_cout,cin,p);
xor (s,p,cin);
or (cout,g,un1_cout); // logical or operator
endmodule
p
g s
un1_cout cout
cout
s
cin
b
a
Logical Operators
ENGR 303
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Structural Module Instantiation
ENGR 303
• Modules can be instantiated (called) from within other modules
• When a module is instantiated, connections to the ports of the module must be specified
• Two Methods of Connection– Ordered instantiation
• The order of the ports must match the order appearing in the instantiated module
• Unused ports may be left unconnected
– Named instantiation• Variables connected to each of module inputs or
outputs are specified in a set of parenthesis following the name of the ports.
• Order of connections is not significant.• You may not leave any port unconnected
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Ordered Module Instantiation
ENGR 303
module dff (clk, d, q); //a D Flip-flop
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
dff inst_1 (clock, data, net_1); //instance 1
dff inst_2 (clock, net_1, q_out); //instance 2
endmodule
The order of the ports must match the
order appearing in the instantiated module
Instance name
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Named Module Instantiation
ENGR 303
module dff (clk, d, q);
input clk, d;
output q;
reg q;
always @(posedge clk) q = d;
endmodule
module top;
reg data, clock;
wire q_out, net_1;
dff inst_1 (.d(data), .q(net_1), .clk(clock));
dff inst_2 (.clk(clock), .d(net_1), .q(q_out));
endmodule
Connections are made by the name of port,
order doesn’t matter
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module and3(input a, b, c,
output y);
assign y = a & b & c;
endmodule
module inv(input a,
output y);
assign y = ~a;
endmodule
module nand3(input a, b, c
output y);
wire n1; // internal signal n1
and3 andgate(a, b, c, n1); // instance of and3
inv inverter(n1, y); // instance of inv
endmodule
Multiple InstancesExample – multiple ordered instantiations
ENGR 303
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Array of InstancesRange of instance names follows the module name
ENGR 303
module my_module (a, b, c);
input a, b;
output c;
assign c = a & b ;
endmodule
module top (a, b, c) ;
input [3:0] a, b;
output [3:0] c;
my_module inst [3:0] (a, b, c);
endmodule
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primitive UDP (input a,b,
output f);
//Truth table for f=SOP(0,2,3)
table
// a b : f //column header comment
0 0 : 1
0 1 : 0
1 0 : 1
1 1 : 1
endtable
endprimitive
module Circuit_with_TruthTable(input [3:0] a, b,
output [3:0] y1);
UDP (a,b,y1)
endmodule
Hierarchy - User Defined Primitive Example - Truth Table
ENGR 303
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~ NOT
*, /, % mult, div, mod
+, - add,sub
<<, >> shift
<<<, >>> arithmetic shift
<, <=, >, >= comparison
==, != equal, not equal
&, ~& AND, NAND
^, ~^ XOR, XNOR
|, ~| OR, NOR
?: ternary operator
Order of operations
Highest
Lowest
Precedence
ENGR 303
<28> ENGR 303
Verilog Keywords*
* The keywords are reserved identifiers, which contain only lowercase letters. The user cannot redefine any of them.
alwaysandassignbeginbufbufif0bufif1casecasexcasezcmosdeassigndefaultdefparamdisableedgeelseendendcaseendfunctionendmoduleendprimitiveendspecifyendtableendtaskeventforforceforeverforkfunctionhighz0highz1
ifinitialinoutinputintegerjoinlargemacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpmosposedgeprimitivepull0pull1pulldownpulluprcmosregreleaserepeatrnmosrpmosrtran
rtranif0rtranif1scalaredsmallspecifyspecparamstrong0strong1supply0supply1tabletasktimetrantranif0tranif1tritri0tri1triandtriorvectoredwaitwandweak0weak1whilewireworxnorxor
