782 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 19, NO. 4, DECEMBER 2019

ESD Protection Design for Open-Drain PowerAmplifier in CMOS Technology

Chun-Yu Lin , Senior Member, IEEE, and Guan-Yi Li

Abstract—The on-chip electrostatic discharge (ESD) protec-tion device for radio-frequency (RF) power amplifier (PA) withopen-drain structure is studied in this work. The conventionalESD protection device of stacked diodes and the proposedESD protection device of stacked diodes with embedded silicon-controlled rectifiers (SCRs) are compared in silicon and appliedto the 2.4GHz PAs. The proposed ESD protection device has theadvantages including higher ESD-current-handling ability, lowerESD-clamping voltage, and sufficiently low parasitic capacitance.Besides, the proposed ESD protection device does not degradethe PA performances. Therefore, the proposed ESD protectiondevice of stacked diodes with embedded SCRs is more suitablefor CMOS PAs.

Index Terms—Electrostatic discharge (ESD), open-drain,power amplifier (PA), silicon-controlled rectifier (SCR), diodes.

I. INTRODUCTION

IN RECENT years, the demand for commercial mobileand wireless applications has led to the development

of radio-frequency (RF) integrated circuits in nanoscaleCMOS technologies [1], [2]. Nanoscale CMOS technologiesare attractive to implement the RF circuits for mass produc-tion due to the main advantages of high integration capabilityand low cost. The power amplifier (PA) in the RF transmitterrequires Watt-level peak power, which was traditionally real-ized by means of the external PA to achieve high efficiencyand high linearity for a wide power range. With the advanceof CMOS technologies, the CMOS PA has recently becomemore and more common [3]–[5].

The RF circuits realized in CMOS technologies are sus-ceptible to electrostatic discharge (ESD) events that maydamage the IC products [6], [7]. The input/output pads ofRF transceiver, including the input pad of low-noise ampli-fier (LNA) and the output pad of PA, may be stressed byESD. Once the RF circuits are damaged by ESD, they can-not be recovered and the functionality will be lost. The ESDdamage has become one of the most important reliabilityissues for the integrated circuits [8]. The RF circuits must

Manuscript received August 22, 2019; revised October 16, 2019; acceptedNovember 4, 2019. Date of publication November 6, 2019; date of currentversion December 18, 2019. This work was supported by the Ministry ofScience and Technology (MOST), Taiwan, under Contract MOST 108-2221-E-003-018. (Corresponding author: Chun-Yu Lin.)

The authors are with the Department of Electrical Engineering, NationalTaiwan Normal University, Taipei 106, Taiwan (e-mail: cy.lin@ieee.org).

Color versions of one or more of the figures in this article are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TDMR.2019.2951939

Fig. 1. ESD current paths in PA with on-chip output matching network.

pass the ESD test before mass production. A typical specifica-tion for IC products on ESD robustness is to pass 2000V testunder human-body model (HBM) [9]. Although this require-ment has been reduced to 1kV or 500V recently due tothe enhanced control methods at manufacturing and assem-bly areas [9], [10], the IC providers still endeavor to offerthe higher ESD robustness in the limited area and the spe-cific circuit performance [11]. Besides, another ESD test ofhuman-metal model (HMM) is recently requested from theindustry [12]. The HMM uses the system-level ESD gun todirectly zap the I/O pads of the IC chips, and the ESD cur-rent of HMM is much larger than that of HBM. Although theHMM is still in the standard practice stage, the required ESDrobustness on IC product may be even higher in the future.

The typical RF PA is based on the common-source or cas-code configuration, and its output matching network includesinductor [4]. With the careful layout design, the parasitic diodein MOSFET and the inductor in output matching network canserve as the ESD current paths, as shown in Fig. 1. Besides,additional power-rail ESD clamp circuit is needed betweenVDD and VSS to achieve whole-chip ESD protection [13]. Aspositive or negative ESD stresses happen between the outputpad of PA (PAout) and VDD or VSS, the PA with self-protectionability can bypass the ESD currents, as shown in Fig. 1.However, some open-drain PAs with off-chip output match-ing network cannot provide the ESD current paths betweenthe VDD and output pad of PA on chip (PAout_chip), as shownin Fig. 2. For the circuits without ESD current path betweenVDD and output pad, additional ESD clamp is needed to pro-vide the ESD current path from the output pad to VSS, andthen the power-rail ESD clamp circuit helps to provide theESD current path from VSS to VDD [14]. Thus, the PA withoff-chip output matching network can still bypass the positive

1530-4388 c© 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

LIN AND LI: ESD PROTECTION DESIGN FOR OPEN-DRAIN PA IN CMOS TECHNOLOGY 783

Fig. 2. ESD current paths in PA with off-chip output matching network.

or negative ESD currents from the PAout_chip to VDD or VSS,as shown in Fig. 2. The design of the ESD clamp circuit fromPAout_chip to VSS is therefore the important design task. SomeESD clamp circuits for the PAs with off-chip output matchingnetwork have been presented, such as the inductor [15], diodesor stacked diodes, [16], [17] and the Zener-diode-triggeredsilicon-controlled rectifier (SCR) [18]. However, these designscould be further improved, including lowering the clampingvoltage of the stacked diodes, and avoiding the ESD implanta-tion in the Zener-diode-triggered SCR. In this work, the ESDprotection design based on the stacked diodes is presented.Besides, with the embedded SCRs to enhance the ESD pro-tection ability [19], [20], the ESD protection design of stackeddiodes with embedded SCRs to protect a 2.4GHz CMOS PA ispresented and characterized for the first time.

II. ESD PROTECTION CONSIDERATION

During ESD stresses, the on-chip ESD protection circuitshould clamp the voltage to a designed range, i.e., an ESDdesign window [21]. Fig. 3 shows the ESD design window ofan IC, which is defined by the upper bound of IC operatingarea, and the lower bound of IC reliability area. The triggervoltage (Vt1) and holding voltage (Vh) of ESD protection cir-cuit must be lower than the voltage of IC reliability area toprevent the IC from damage during ESD stresses. Besides, thetrigger voltage and holding voltage of ESD protection circuitmust be higher than the voltage of IC operating area to preventthe ESD protection circuit from being mis-triggered undernormal circuit operating condition. Moreover, the turn-onresistance (Ron) of ESD protection circuit should be minimizedto reduce the joule heat generated in the ESD protection cir-cuit and the clamping voltage of the ESD protection circuitduring ESD stresses.

For the PA comprising cascode architecture, its breakdownvoltage is limited either by the 2-times gate oxide breakdownvoltage or by the drain breakdown voltage [22]. If the break-down voltage of PA is 15V, and the PA utilizes 3.6V VDDsupply, the ESD design window ranges from ∼4V to ∼15V.

III. DESIGN AND IMPLEMENTATION

A. Power Amplifier

The 2.4GHz PA with cascode configuration and off-chipoutput matching network is designed in this work, as shown

Fig. 3. ESD design window outside the IC operating and reliability areas.

Fig. 4. Schematic circuit of 2.4GHz PA.

in Fig. 4. The cascode configuration is adopted because itsgain and high frequency response are relatively better thanthose of the single-stage common-source amplifier. Since thePA is used for amplifying the input signal, the MOSFET isdesigned to operate in the saturation region. When the biasvoltage is fixed, the bias current should be larger to obtainhigher output power of PA. The transconductance (and thusthe gain) is higher when the channel length of the MOSFETis shorter. Due to this reason, the channel length is chosen as0.18µm in this work. The gate width of M1 or M2 is 8µmand the number of fingers is 64. The VDD supply is 3.6V, andthe voltage swing at output pad is ranged within 0 and VDD.For impedance matching of the PA, the conjugate matchingmethod is used for the input matching network, whereas theoutput matching network is used to convert the load impedanceto the optimal output impedance. With the output impedancebeing optimal, PA can deliver the maximum output power.

The simulated S-parameters of the designed PA are shownin Fig. 5. The gain and return loss at 2.4GHz are 21.2dB and−13.6dB, respectively.

B. Stacked Diodes

The stacked diodes can be used as the ESD clamp toprotect the PA output, as shown in Fig. 6(a). The con-ventional stacked diodes utilize P+/N-well diodes in CMOStechnology [23], [24]. Fig. 7(a) shows the cross-sectional view

784 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 19, NO. 4, DECEMBER 2019

Fig. 5. Simulated gain (S21) and return loss (S22) of 2.4GHz PA.

Fig. 6. PA with on-chip ESD protection of (a) stacked diodes and (b) stackeddiodes with embedded SCRs.

of the conventional stacked diodes, in which the anode isarranged in the center and connected to PAout_chip, and thecathode is arranged to the outside and connected to VSS.Stacked more diodes can increase the clamping voltage, andit can tolerate the larger voltage swing at PAout_chip. However,this design is adverse to ESD protection because the over-all turn-on resistance (Ron) of the stacked diodes is increasedas well.

C. Stacked Diodes With Embedded SCRs

To enhance the ESD protection ability of stacked diodes,the SCR devices are embedded into the diodes [25], [26]. Thestacked diodes with embedded SCRs have been used to pro-vide the ESD current path from VSS to I/O or from I/O toVDD. In this work, the stacked diodes with embedded SCRsto provide the ESD current path from PAout_chip to VSS ispresented, as shown in Fig. 6(b). The stacked diodes utilizeP+/N-well and P-well/N+ diodes alternatingly. As the P+/N-well and P-well/N+ diodes are put together in layout, theembedded SCR is formed, as shown in Fig. 7(b). The SCRdevice has been reported to be useful for ESD protectionwith low turn-on resistance, low parasitic effects, and highESD robustness [27]–[30]. The equivalent circuit of the SCRconsists of the cross-coupled PNP and NPN BJTs. The deepN-well layer is used to separate each P-well from the com-mon P-substrate, which layer is typically used against substratecoupling in CMOS mixed-signal/RF circuits [31]–[33].

During ESD stresses, the stacked diodes will be forwardbiased to discharge the initial ESD current, and then theembedded SCRs will be turned on to discharge the primaryESD current. The positive-feedback regenerative mechanismof conductive to make the SCR very robust against ESD

stresses. PNP and NPN BJTs results in the SCR device becom-ing highly During normal circuit operating conditions, thestacked diodes and the embedded SCRs are kept off if thereare sufficient numbers of diodes.

IV. EXPERIMENTAL RESULTS OF ESD PROTECTION

CIRCUITS

The test circuits of stacked diodes with and without embed-ded SCRs are compared. The numbers of diodes are selectedto be 8 and 12. The test circuits include the stacked 8 diodes(SD_8), stacked 12 diodes (SD_12), stacked 8 diodes with4 embedded SCRs (SD-SCR_8), and stacked 12 diodes with6 embedded SCRs (SD-SCR_12). Fig. 8 shows the layout topviews of SD_8 and SD-SCR_8. In the stacked diodes, eachdiode width is 25µm. In the stacked diodes with embeddedSCRs, each SCR width is also 25µm, while each diode widthis reduced to 5µm (2.5µm*2, as shown in Fig. 8(b)). The pur-pose of reducing the diode width is to force the ESD current tobe discharged through the robust SCR path [20]. To facilitatethe on-wafer RF measurement, these test circuits are arrangedwith ground-signal-ground (G-S-G) pads in layout. The testcircuits of SD_8, SD_12, SD-SCR_8, and SD-SCR_12 havebeen fabricated in a 0.18µm standard CMOS process.

A. Parasitic Capacitance

With the on-wafer measurement, the two-port S-parametersof the test circuits are measured by using the vector networkanalyzer, and then transferred to the capacitances. In orderto extract the intrinsic characteristics of the test circuits inhigh frequencies, the parasitic effects of the G-S-G pads havebeen removed by using the standard open-short de-embeddingtechnique. The parasitic capacitance of each test circuit can beobtained. Fig. 9 shows the extracted parasitic capacitances oftest circuits. With zero bias at PAout_chip (PAout_chip = 0V),the parasitic capacitances of test circuits range from 40fFto 65fF within the frequency band of 2-10GHz, as shownin Fig. 9(a). As the bias voltage at PAout_chip increases, theparasitic capacitances of test circuits slightly increase. At2.4GHz, the maximum parasitic capacitances of SD_8, SD_12,SD-SCR_8, and SD-SCR_12 in the given bias voltage range(0-3.6V) are 64.1fF, 62.6fF, 66.9fF, and 65.6fF, respectively,as shown in Fig. 9(b). The parasitic capacitances of stackeddiodes with embedded SCRs are close to those of stack diodes.

B. I-V Characteristics

To simulate the HBM ESD stresses and investigate the turn-on behaviors in high-current regions of the ESD protectioncircuits, the transmission-line-pulsing (TLP) system with 10nsrise time and 100ns pulse width is used. The TLP-measuredI-V characteristics of test circuits between PAout_chip and VSSare shown in Fig. 10. The trigger voltage (Vt1) and holdingvoltage (Vh) of ESD protection circuits can be characterizedfrom the TLP-measured I-V curves. The voltage range ofPA output swing is limited by the trigger voltage of ESD pro-tection circuit. Besides, the current-handling ability of eachtest circuit before internal circuit breakdown (IBV) can be

LIN AND LI: ESD PROTECTION DESIGN FOR OPEN-DRAIN PA IN CMOS TECHNOLOGY 785

Fig. 7. Device cross-sectional views of (a) stacked diodes and (b) stacked diodes with embedded SCRs.

TABLE IMEASUREMENT RESULTS OF ESD PROTECTION DEVICES

obtained from the TLP-measured I-V curves. If the break-down voltage is 15V, the IBV of SD_8, SD_12, SD-SCR_8,and SD-SCR_12 are 3.4A, 1.3A, 4.1A, and 2.9A, respectively.Although the Darlington configuration of PNP (P+/N-well/P-substrate) in conventional stacked diodes gives a higher currentthan each diode taken separately [34], the turn-on efficiencystill needs to be further improved. With the higher IBV andthe reduced clamping voltage during ESD stresses, the stackeddiodes with embedded SCRs can provide more efficient ESDprotection. Besides, the trigger voltages (Vt1) of the test cir-cuits are higher than 4V, which means the ESD protectioncircuit can sustain more than 4V signal swing during normalcircuit operating conditions. The holding voltages (Vh) of thetest circuits are higher than 3.6V (VDD = 3.6V for the follow-ing application); therefore, the ESD protection circuit shouldbe free from latchup issue. All these measurement results arelisted in Table I.

A very-fast TLP (VF-TLP) with 0.2ns rise time and 1nspulse duration is used to evaluate the effectiveness of the testcircuits in the time domain of charged-device-model (CDM)event. Fig. 11 shows the VF-TLP I-V curves of test circuits.The SD-SCR_8 and SD-SCR_12 provide better clampingability than SD_8 and SD_12. Fig. 11 also shows the tran-sient voltage waveforms at VF-TLP I=0.5A of SD_8 andSD-SCR_8, which will be utilized to protect PAs in nextSection. The overshoot and clamping voltages of SD_8 maynot be low [35], while those voltages of SD-SCR_8 can beslightly lower.

To extract the leakage currents of test circuits, the dc I-Vcharacteristics are measured. Fig. 12 shows the measureddc I-V curves of test circuits at 100◦C. The Darlington configu-ration in SD_8 or SD_12 may lead to higher currents than thatin SD-SCR_8 or SD-SCR_12. The leakage currents of SD_8and SD_12 under VDD bias (3.6V in this work) at 100◦C are

786 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 19, NO. 4, DECEMBER 2019

Fig. 8. Layout top views of (a) stacked 8 diodes (SD_8) and (b) stacked8 diodes with embedded SCRs (SD-SCR_8).

7.3µA and 0.5µA, respectively. With the same condition, theleakage currents of SD-SCR_8 and SD-SCR_12 are reducedto 0.7µA and 0.1µA, respectively.

C. Discussion

Since this work is aimed at the ESD protection circuits con-nected between PAout_chip and VSS, the stacked diodes arewished to have low parasitic capacitance under normal circuitoperating conditions, and good current-discharging ability dur-ing ESD stress conditions. A figure of merit (FOM) related tothe parasitic capacitance at 2.4GHz and 3.6V (C2.4GHz/3.6V)and the TLP IBV are defined in this work, as shown in Eq. (1).

FOM = IBV

C2.4GHz/3.6V(1)

Fig. 9. Measured parasitic capacitances of test circuits at (a) PAout_chip = 0Vand (b) frequency = 2.4GHz.

The FOM of SD_8 and SD_12 are 53.0mA/fF and20.8mA/fF, respectively, and those of SD-SCR_8 and SD-SCR_12 are improved to 61.3mA/fF and 44.2mA/fF, respec-tively. The stacked diodes with embedded SCRs can providethe better ESD-current-discharging ability and the lower par-asitic capacitance.

V. EXPERIMENTAL RESULTS OF PAS

The stacked diodes with and without embedded SCRs havebeen applied to the PA, as shown in Fig. 6. The stacked8 diodes with and without embedded SCRs (SD_8 and SD-SCR_8) are selected to protect the PAout_chip. For comparisonpurpose, the PA without ESD protection is also implemented.The test circuits of PA, PA with SD_8, and PA with SD-SCR_8 have been fabricated in 0.18µm CMOS process.Fig. 13 shows the chip photograph of the PA with SD_8 andPA with SD-SCR_8. The PAin and PAout_chip pads are arrangedin G-S-G style for RF measurement, and the VG1 and VG2 padsare arranged in P-G-P style for dc voltage supply. The layoutarea of each PA is 610x510µm2, including all pads.

A. Before ESD Tests

The load-pull system is used to simulate the output matchingnetwork. The output matching network is then implementedon a PCB. The RF characteristics of three PAs are measured.Each PA circuit operates with the 3.6V VDD supply, and thebias voltages VG1 and VG2 are 0.8V and 2.6V. The measuredS21 parameters of PA without ESD protection, PA with SD_8,and PA with SD-SCR_8 are shown in Fig. 14. The peak gain

LIN AND LI: ESD PROTECTION DESIGN FOR OPEN-DRAIN PA IN CMOS TECHNOLOGY 787

Fig. 10. TLP I-V curves of test circuits with (a) 8 and (b) 12 diodes.

Fig. 11. VF-TLP I-V curves of test circuits.

frequencies of the PAs are shifted to ∼2.6GHz. The maximalS21 of PA, PA with SD_8, and PA with SD-SCR_8 are 21.7dB,21.5dB, and 21.5dB, respectively. The output power of thesePAs are 17.8dBm, 13.0dBm, and 18.8dBm, and the powergain are 19.8dB, 21.1dB, and 21.4dB, respectively. The ESDprotection circuit of stacked diodes with embedded SCR doesnot degrade the RF performances of the PA.

B. HBM Robustness Specified by RF Performance

To verify the ESD protection ability of the on-chip ESDprotection stacked diodes, the RF performances after ESD testsof the three PAs are re-measured. The HBM ESD stresses areperformed from PAout_chip to VSS. The S21 parameters afterESD tests of PA, PA with SD_8, and PA with SD-SCR_8 are

Fig. 12. Measured leakage currents of test circuits at 100◦C.

Fig. 13. Chip photograph of PA with SD-SCR_8 and PA with SD_8.

Fig. 14. Measured S21 parameters of PAs before ESD tests.

Fig. 15. Measured S21 parameters of PA before and after ESD tests.

shown in Figs. 15-17. Besides, the output power and powergain before and after ESD tests of the three PAs are measuredand summarized in Table II. The maximal S21, output power,and power gain of the PA are severely degraded after 3kVHBM ESD tests, which indicated the HBM robustness of PA is2kV. The maximal S21 of PA with SD_8 is degraded after 6kVHBM ESD tests, while the output power and power gain are

788 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 19, NO. 4, DECEMBER 2019

TABLE IIMEASUREMENT RESULTS OF POWER AMPLIFIERS

Fig. 16. Measured S21 parameters of PA with SD_8 before and after ESDtests.

degraded after 5kV HBM ESD tests, which indicated the HBMrobustness of PA with SD_8 is 4kV. The failure position ofPA with SD_8 is located at the transistor M1. The maximalS21, output power, and power gain of PA with SD-SCR_8 arenot degraded even after 8kV HBM ESD tests (8kV is thelimitation of the given HBM tester). The HBM ESD robustnessof PA with SD-SCR_8 is improved to >8kV. Besides, thenegative HBM robustness of all PAs are over −8kV.

C. HBM Robustness Specified by Leakage Current

Besides specifying by the RF performance, the ESD robust-ness of the three PAs are specified by the leakage current. TheHBM ESD tests are applied onto the test circuits. The criterionof ESD robustness is specified by the leakage current of the

Fig. 17. Measured S21 parameters of PA with SD-SCR_8 before and afterESD tests.

test circuit. Once the leakage current shifts over 30% from itsoriginal one after ESD stress, the test circuit is judged to befailure. The HBM robustness specified by leakage current ofthe three PAs are listed in Table II. The HBM robustness ofPA, PA with SD_8, and PA with SD-SCR_8 are 3kV, 5kV, and>8kV, respectively. The SD-SCR can even provide the betterESD protection for PA.

D. Comparison Among ESD Protection Designs

Several 2.4GHz PAs with ESD protection are comparedin Table III. These prior PAs can pass 3kV, 5.3kV, and3.25kV HBM ESD tests, while the proposed PA with SD-SCR_8 can pass >8kV HBM ESD tests. The stacked diodes

LIN AND LI: ESD PROTECTION DESIGN FOR OPEN-DRAIN PA IN CMOS TECHNOLOGY 789

TABLE IIICOMPARISON OF POWER AMPLIFIERS WITH ESD PROTECTION

with embedded SCR can provide the better ESD protectionfor PA.

VI. CONCLUSION

The on-chip ESD protection of stacked diodes with embed-ded SCRs has been developed for the gigahertz open-drain PAsin this work. This work aims to achieve the low trigger volt-age, low holding voltage, low turn-on resistance, and high ESDrobustness during ESD stresses, and to prevent from signal lossand mis-triggering under normal circuit operating conditions.The FOM of IBV/C2.4GHz is wished to be as high as possible.According to the experimental results in the 0.18µm CMOSprocess, SD_8 and SD_12 perform the FOM of 53.1mA/fFand 20.6mA/fF, and SD-SCR_8 and SD-SCR_12 improve theFOM to 60.3mA/fF and 42.6mA/fF. The SD-SCR_8 showsthe better FOM among the test circuits. Furthermore, the ESDprotection circuits have been applied to protect the PAs. TheSD-SCR_8 provides >8kV HBM ESD robustness withoutdegrading the PA performances, while the stand-alone PA andPA with SD_8 can only sustain 2kV and 4kV HBM ESD tests.Therefore, the proposed on-chip ESD protection of stackeddiodes with embedded SCRs can be a good solution for thegigahertz open-drain PAs.

ACKNOWLEDGMENT

The authors would like to thank Taiwan SemiconductorResearch Institute (TSRI), Taiwan, for the support of chip fab-rication, Hanwa Electronic Ind. Co., Ltd., Japan, for setting upthe ESD tester, and Prof. M.-D. Ker and his research group inNational Chiao Tung University, Taiwan, for their help duringmeasurement.

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