ESE 570: Digital Integrated Circuits and VLSI …ese570/spring2016/handouts/...VLSI Fundamentals Lec...

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 8: February 9, 2016 MOS Inverter: Static Characteristics

Penn ESE 570 Spring 2016 – Khanna

Lecture Outline

!  Voltage Transfer Characteristic (VTC) "  Static Discipline Noise Margins

!  Resistive Load Inverter Analysis !  Design Perspective

2 Penn ESE 570 Spring 2016 – Khanna

Voltage Transfer Characteristic (VTC)


Ideal Voltage Transfer Characteristic (VTC)

4

Vin Vout

0

Logic “0” = 0 V Logic “1” = VDD

VDD


Actual Voltage Transfer Characteristic (VTC)

5

VDD

0 VDD VOL VT0n

VOH ≤ VDD

VOL ≥ 0

For DC steady-state Cout is open circuit.

Cout

o.c.

VDD


Noise Immunity and Noise Margins

6

VDD

NOTE: VIL ≥ VOL and VIH ≤ VOH

VOH ≤ VDD → max output voltage when the logic output is “1” VOL ≥ 0 → min output voltage when the logic output is “0” VIL → max input voltage that can be interpreted as a logic “0” VIH → min input voltage that can be interpreted as a logic “1”


7

Slope of VTC or

inverter gain

Noise Immunity and Noise Margins


Resistive Load Inverter Analysis


Resistive Load Inverter

9

VSB



10

VSB

IL =VDD −Vout

RL

Resistor:



11

VSB

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

Vin =VGS <VT 0,nSubthreshold:

Resistor: IL =

VDD −VoutRL



12

VSB

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

ID =µn ⋅Cox

2WL2 Vin −VT 0,n( )Vout −V 2

out( )

Vin =VGS <VT 0,n

Vin =VGS ≥VT 0,n,Vout =VDS ≤Vin −VT 0,n

Subthreshold:

Linear:

Resistor: IL =

VDD −VoutRL



13

VSB

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

ID =µn ⋅Cox


out( )

ID =µn ⋅Cox

2WLVin −VT 0,n( )2

Vin =VGS <VT 0,n


Vin =VGS ≥VT 0,n,Vout =VDS >Vin −VT 0,n

Subthreshold:

Linear:

Saturation:

Resistor: IL =

VDD −VoutRL



14

VSB

ID = ISWL

!

"#

$

%&e

Vin−VT 0,nnkT /q

!

"#

$

%&

1− e−VoutkT /q!

"#

$

%&!

"

##

$

%

&&

ID =µn ⋅Cox


out( )

ID =µn ⋅Cox


Vin =VGS <VT 0,n


Vin =VGS ≥VT 0,n,Vout =VDS >Vin −VT 0,n

Subthreshold:

Linear:

Saturation:

Resistor: IL =

VDD −VoutRL

ID = 0



15

VSB


Resistive Load Inverter: VOH

16

VSB

Resistor/Load: Transistor: Subthreshold


Resistive Load Inverter: VOH

17

VSB

IL =VDD −Vout

RLID = 0

Resistor/Load: Transistor: Subthreshold

0 = VDD −VoutRL

⇒Vout =VDD =VOH


Resistive Load Inverter: VOL

18

VSB

Resistor/Load: Transistor: Linear


Resistive Load Inverter: VOL

19

VSB

IL =VDD −Vout

RL


Vin =VDD,Vout =VOL

ID =µn ⋅Cox


out( )

VDD −VOLRL

=µn ⋅Cox

2WL2 VDD −VT 0,n( )VOL −V 2

OL( )Penn ESE 570 Spring 2016 – Khanna

Resistive Load Inverter: VOL (con’t)

20

IL =VDD −Vout

RL


Vin =VDD,Vout =VOL

ID =µn ⋅Cox


out( )

VDD −VOLRL

=µn ⋅Cox

2WL2 VDD −VT 0,n( )VOL −V 2

OL( )

kn = µn ⋅CoxWL

VDD −VOLRL

=kn22 VDD −VT 0,n( )VOL −V 2

OL( )

2kn⋅1RL

#

$%

&

'( VDD −VOL( ) = 2 VDD −VT 0,n( )VOL −V 2

OL

V 2OL − 2 VDD −VT 0,n +

1knRL

#

$%

&

'(VOL +

2VDDknRL

= 0



21

IL =VDD −Vout

RL


Vin =VDD,Vout =VOL

ID =µn ⋅Cox


out( )

V 2OL − 2 VDD −VT 0,n +

1knRL

"

#$

%

&'VOL +

2VDDknRL

= 0

VOL =2 VDD −VT 0,n +

1knRL

"

#$

%

&'± 2 VDD −VT 0,n +

1knRL

"

#$

%

&'

"

#$

%

&'

2

− 4 2VDDknRL

2

VOL = VDD −VT 0,n +1

knRL

"

#$

%

&'± VDD −VT 0,n +

1knRL

"

#$

%

&'

2

−2VDDknRL

kn = µn ⋅CoxWL



22

IL =VDD −Vout

RL


ID =µn ⋅Cox


out( )

V 2OL − 2 VDD −VT 0,n +

1knRL

"

#$

%

&'VOL +

2VDDknRL

= 0

VOL =2 VDD −VT 0,n +

1knRL

"

#$

%

&'± 2 VDD −VT 0,n +

1knRL

"

#$

%

&'

"

#$

%

&'

2

− 4 2VDDknRL

2

VOL = VDD −VT 0,n +1

knRL

"

#$

%

&'± VDD −VT 0,n +

1knRL

"

#$

%

&'

2

−2VDDknRL

0 <VOL <VT 0,n

Vin =VDD,Vout =VOL

kn = µn ⋅CoxWL


Resistive Load Inverter: VIL

23

VSB

Resistor/Load: Transistor: Saturation


Resistive Load Inverter: VIL

24

VSB

IL =VDD −Vout

RL

Resistor/Load: Transistor: Saturation

ID =µn ⋅Cox


VDD −VoutRL

=µn ⋅Cox



Resistive Load Inverter: VIL (con’t)

25

Differentiate W.R.T. Vin:

VDD −VoutRL

=µn ⋅Cox


−1RL

dVoutdVin

= µn ⋅CoxWLVin −VT 0,n( )

1RL

= µn ⋅CoxWLVIL −VT 0,n( )

VIL =1

knRL+VT 0,n

VDD −Vout Vin=VILRL

=kn2VIL −VT 0,n( )2

Vout Vin=VIL =VDD −knRL2

VIL −VT 0,n( )2

Vout Vin=VIL =VDD −1

2knRL

Vout @ Vin=VIL:


Resistive Load Inverter: VIH

26

VSB




27

VSB

IL =VDD −Vout

RL


ID =µn ⋅Cox


out( )

VDD −VoutRL

=µn ⋅Cox


out( )



28

Differentiate W.R.T. Vin:

−1RL

dVoutdVin

=kn22 Vin −VT 0,n( ) dVout

dVin+ 2Vout − 2Vout

dVoutdVin

"

#$

%

&'

1RL

=kn2−2 VIH −VT 0,n( )+ 4Vout( )

1knRL

=VT 0,n −VIH + 2Vout

VIH =VT 0,n + 2Vout −1

knRL

VDD −VoutRL

=µn ⋅Cox


out( )



29

VIH =VT 0,n + 2Vout −1

knRL

VDD −VoutRL

=µn ⋅Cox


out( )

VDD −VoutRL

=kn22 VT 0,n + 2Vout −

1knRL

−VT 0,n"

#$

%

&'Vout −V

2out

"

#$$

%

&''

VDD −VoutRL

=kn24V 2

out −2

knRLVout −V

2out

"

#$

%

&'

VDDRL

=kn23V 2

out −2

knRLVout

"

#$

%

&'+VoutRL

VDDRL

=32knV

2out −

VoutRL

+VoutRL

VDDRL

=32knV

2out ⇒Vout Vin=VIH =

23VDDknRL

VIH =VT 0,n + 223VDDknRL

−1

knRL

Substitute:


Inverter Threshold: Vth

30

Kenneth R. Laker,

University of Pennsylvania,

updated 12Feb15

VDD −VoutRL

=µn ⋅Cox


VDD −VthRL

=kn2Vth −VT 0,n( )2

2kn

VDD −VthRL

=V 2th − 2VthVT 0,n +V

2T 0,n

0 =V 2th − 2 VT 0,n −

1knRL

#

$%

&

'(Vth +V

2T 0,n −

2VDDknRL

Vth =2 VT 0,n +

1knRL

#

$%

&

'(± 2 VT 0,n −

1knRL

#

$%

&

'(

#

$%

&

'(

2

− 4 V 2T 0,n −

2VDDknRL

#

$%

&

'(

2

Vth =VT 0,n +1

knRL± VT 0,n −

1knRL

#

$%

&

'(

2

− V 2T 0,n −

2VDDknRL

#

$%

&

'(


Summary: Resistive Load Inverter

31 VT0n

VDD

0 VDD Penn ESE 570 Spring 2016 – Khanna

Summary: Resistive Load Inverter

32 VT0n

VDD

0 VDD

Take Limit as knRL -> ∞

-> VT0n

-> VT0n -> VDD

-> VT0n -> 0

-> 0

-> VDD VDD

Vout

VDD Vin VT0n

knRL -> ∞

0

semi-ideal VTC


Example

33

VOL = 0.147 V or 8.503 V ?


Preferred Design

Example (con’t)


Design Perspective


Noise Implications

!  What is the output when all inputs are all 1s?


Noise Implications

!  What is the output when all inputs are all 1.0 and NAND(A, B) = 1-A*B?


Noise Implications

!  What is the output when all inputs are all 0.95 and NAND(A, B) = 1-A*B?


Degradation

!  Cannot have signal degrade across cascaded gates !  Want to be able to cascade arbitrary set of gates

"  No limit on number of gates to maintain signal integrity


Gate Creed

!  Gates should leave the signal “better” than they found it "  “better” # closer to the rails


Regeneration Discipline

!  Define legal inputs "  Gate works if Vin “close enough” to the rail

!  Regeneration "  Gate produces Vout “closer to rail”

"  This tolerates some drop between one gate and next (between out and in)

"  Call this our “Noise Margin”

Regeneration/Restoration/Static Discipline


Noise Margin

!  VOH – output high !  VOL – output low

!  VIH – input high !  VIL – input low

!  NMH = VOH-VIH

!  NML = VIL-VOL

“1”

“0”

VOH

VOL

VIL

VIHNMH

NML

Undefined region

Gate Output Stage M

Gate Input Stage M + 1


Regeneration Discipline (getting precise)

!  Define legal inputs "  Gate works if Vin “close

enough” to the rail "  Vin > VIH or Vin < VIL

!  Regeneration "  Gate produces Vout “closer to

rail” "  Vout < VOL or Vout > VOH

“1”

“0”

VOH

VOL

VIL

VIHNMH

NML

Undefined region

Gate Output Stage M

Gate Input Stage M + 1


Decomposing

!  An input closer to rail than VIL, VIH doesn’t make much difference on Vout

"  i.e transfer function is flat close to rails

!  Defining VIL lower (VIH higher) would reduce NMs and increase our undefined region

-1

-1

VIL VIH

VOL

VOH

VIL

VIH

NML

NMH

δVoutδVin VIL

=δVoutδVin VIH

= −1

VOH = f (VIL )VOL = f (VIH )


Big Idea

!  Need robust logic "  Can design into any (feed forward) graph with logic gates

and tolerate loss and noise, while maintaining digital abstraction

!  Regeneration and noise margins "  Every gate makes signal “better” "  Design level of noise tolerance


-1

-1

VIL VIH

VOL

VOH

VIL

VIH

NML

NMH

Admin

!  HW 2 handback !  HW 4 due Thursday, 2/18

"  If you submit online and in-class only the online one will be graded.

!  Journal Thursday "  Gregory Fredeman, et. al., A 14 nm 1.1 Mb Embedded

DRAM Macro With 1 ns Access, pp 230 - 239


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