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GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture.Vladimir Gromov, Ruud Kluit, Harry van der Graaf.NIKHEF, Amsterdam,The Netherlands.April 18, 2008.

Outline Drift time measurements in the GOSSIP detector. Time-to-Digital Conversion with local oscillator. GOSSIPO-2 chip: history, structure and features. Characterization and performance of the pixel array of the chip. Conclusions and plans. V.GromovRD51 Workshop, 4/18/20082GOSSIP detector: principles of operation.Cluster3 Cathode (drift) planeIntegrated Grid (InGrid) Cluster2 Cluster1 Slimmed Silicon Readout chip Input pixel1mm,400V50um, 400V50um3-D track reconstruction Clusters drift time measurements

low capacitance on the pixel ( down to 10 fF). narrow drift gap (1 mm). fast charge collection time (20 ns). low diffusion of the primary electrons (70 um/1.6 ns)XYZGas On Slimmed Silicon Pixel (GOSSIP): a detector combining a thin gas layer as signal generator with a CMOS readout pixel array. High resolutionTDC

V.GromovRD51 Workshop, 4/18/2008

3Time-to-Digital Conversion based on local oscillator.StartStopLocal oscillatorPixel_1HitPixel_2Clock Bus Clock signal sourceHit signalClock signal(period is Tslow)Local oscillator: output signal (period is Tfast) Drift timeMeasured time StartStopThe number of clocks (Nfast) at the output of the local oscillator gives the value of the drift time as follows: Tdrift = Tslow - Nfast Tfast Time resolution is determined by the frequency (Tfast) and performance of the local oscillator circuit.

The local oscillator is active only within restricted space of time. Only slow Clock signal is being distributed across the chip. Low powerconsumptionOut

V.GromovRD51 Workshop, 4/18/2008

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GOSSIPO-2 chip: history, structure and main features.History.2006. GOSSIPO-1 (0.13um CMOS): analog front-end:fast, low-noise (ENC=70 e- ) threshold =350 e-, low-power (2 uW per channel).

2007. GOSSIPO-2 (0.13um CMOS) : read-out pixel array. sensitive area: 0.88 mm2 (16 pixels x 16 pixels) pixel size: 55 um. high resolution TDC-per-pixel architecture (bin=1.8 ns). -separate TDC block. -separate local oscillator circuit. -analog monitor block.

Performance of the local oscillator circuit.NANDENOUTDelay = Tfast/2 = Function (Temp, Vdd) ENTfast (1.8 ns)OUT

Power supply voltage, VoltsTemperature, C Tfast ,ns Tfast ,ns - 12% / 100mV 2% / 10 CChannel-to-channel statistical spread is 4%Effect of the power supply voltage .Effect of the temperature.0nsTslow (25 ns)

015 (4-bit TDC)If the power supply changes within 50 mVIf the temperature changes within 30 C Accumulated error will be kept within 6% (1.8 ns or 1 bin of the 4bit TDC).Schematic of the local oscillator.

V.GromovRD51 Workshop, 4/18/2008

6Performance of the TDC block.StartStopLocal oscillatorHitOutIn4bitslow clockCounterTDCControl

OutIn4bitfast clockCounterOutClock Trigger ReadResetHit signalSignal at the input of the fast clock counter (period is Tfast = 1.8 ns) StartStopSignal at the input of the slow clock counter (period is Tslow = 25 ns).Trigger signalStopNslowNfastDATA _FORMAT = 4bit (Nslow) + 4bit (Nfast) Clock - Time resolution is ( Tfast ) is 1.8 ns. - Differential non-linearity is about 0.3 1.8 ns. - Dynamic range is 4bit (Tslow = 25 ns) is 350 ns. Data

Output code, converted asNslow 25 ns + Nfast 1.8 ns delay of the Hit signal, ns Transition region is about 30 ps! Discontinuity occurs when the Hit signal goes over the leading edge of the slow clock (slow) signal. Will be solved. Vdd=1.3 VVdd=1.2 VVdd=1.1 VTDC structure.

V.GromovRD51 Workshop, 4/18/2008

7GOSSIPO-2 chip: charge-sensitive preamplifier.Ib=1 nAVb2Vb1Vdd=1.2 VOutputInputCpar 30 fF Cfb = 1 fF Features.Low parasitic capacitance at the input (30fF): - low power consumption (2 W per channel). - pulse response rise-time is 20 ns - low noise (n=70 e- ENC) threshold =350 e-

In order to confine time jitter to the TDC bin size (1.8 ns) the signal must be larger then 4000 e-. The DC feedback circuit is not tolerant for variation of the fabrication process. This results in a number of not operational channels (15 %-30 %). This will be solved in the future.

020Time, ns406080Threshold =350 e- Signal size = 2400 e-Signal size = 800 e-time jitter / internal delay 8 nstime jitter / internal delay 3 nsTime jitter / internal delay = Rise_time 5n / Signal size CinVOPAMP

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8GOSSIPO-2 chip: voltage comparator.Features.The comparator is an OPAMP based on current mirrors architecture.

the internal delay is inverse proportional to the size of the input signal (as usual).the minimum value of the internal delay (tmin) is much larger than one bin of theTDC (1.8 ns). tmin depends on the value of the tail current (Itail) and thereforetmin is temperature dependenttmin is power supply voltage dependenttmin takes different values due to channel-to-channel mismatch.

1000tmin =15 ns Threshold =350 e- I tail = 0.2 uASignal size, electrons Comparator delayItail = 0.4 uA I tail = 0.8 uA200030004000 Currently we are developing a faster comparator having internal delay close to 1.8 ns (one bin of the TDC) even at low tail currents (0.4 A). Instability and spread of the value of tmin will be negligible. VthrOutputInputItailVdd=1.2 Vtmin =10 ns tmin =7 ns

V.GromovRD51 Workshop, 4/18/2008

9GOSSIPO-2 chip: read-out pixel array. Functionality.Only Slow clock (40 MHz) is being distributed across the array.

All 256 pixel will be read out serially when the Read (Trigger) signal arrives.

Clear_ON mode: data on the pixel will be RESET locally if the Read signal is not available within 350ns after the hit signal. Clear_OFF mode: data on the pixel will be KEPT UNCHANGED even if the Read signal is not available within 350ns after the hit signal.

4 bit DAC for threshold tuning.

- Control registers for masking and test-pulse enabling.Pixel_1 InTDCblockOutRead (Trigger)ResetClockDataPreampComp4bit Threshold DACCommon thresholdDataLocal thresholdInputpadTest pulsePixel_2Pixel_16Pixel_256Front-end

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10Test set-up for the GOSSIPO-2 read-out pixel array.PCB with GOSSIPO-2PCB with FPGA & USB portPC with LabView

FPGA & software:Upload configuration data (threshold DACs and mask registers).Readout chip data.Read(trigger) signal and test pulse.

GOSSIPO-2FPGADC sourcePulse generatorCommonthresholdpower supply voltageUSBGPIBtest pulseRead (trigger)Clock (slow) generator 40MHz.Clock

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11Time resolution as a function of threshold value. - Low threshold operation (350 e-) in combination with large signal size (larger than 4000 e-) will allow for high time resolution (jitter less than 1bin of the TDC = 1.8 ns). Threshold scan.Read (Trigger) signalV(Qin)Test pulseMeasured time

160150Measured time (converted output code), ns140time jitter 4bin1.8 ns = 7.2 ns130120110100908070300400500600700300400500600300400500Thresholdvoltage, mVThresholdvoltage, mVThresholdvoltage, mVnoise

time jitter 2bin1.8 ns = 3.6 nstime jitter 1bin1.8 ns = 1.8 nsSignal size = 1200 e-Signal size = 3000 e-Signal size = 12000 e-InTDCblockOutRead (Trigger)ResetClockDataFront-endThresholdTest pulsePixel cell structure.

V.GromovRD51 Workshop, 4/18/2008

12Time scan.

Read (Trigger) signalV(Qin >4000e-)Test pulseMeasured timeInTDCblockOutRead (Trigger)ResetClockDataFront-endThreshold (350e- )Test pulsePixel cell structure. Delay of the Test pulse, nstransition region 1 nsMeasured time (converted output code) [ns]Measured time (converted output code ) as a function of the delay of the Test pulse.Large signal (> 4000 e- ) and low threshold operation (350 e-). delayDistortion occurs when the Hit signal goes over the leading edge of the slow clock (slow) signal. - The complete read-out chain demonstrates good time resolution (transition region is 1ns) when the threshold is low (350e-) and the input signal is large (>4000e-).

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Threshold equalization in the pixel array.

4bit Threshold DACCommon thresholdvoltageLocal thresholdvoltageConfiguration memorySerial LinkSerial LinkGeneration of the pixels threshold voltage. Common thresholdBefore equalization. After equalization. Common thresholdPreamp output Preamp output Offset Pixel_1- Threshold spread after equalization per pixel: 150 e-. Pixel number 050100150200250Thresholdoffset, mV200300400500Offset Pixel_2Offset Pixel_3600Thresholdoffset, mV200300400500

Not operational pixels (15%).These pixels should be maskedPrecision = 160 mV/16(4bit DAC) = 10 mV (150e-) 160mV

V.GromovRD51 Workshop, 4/18/2008

14Channel-to-channel spread of the measured time. Pixel_1Output Code_1 Pixel_2Pixel_256ReadResetClockTest pulsePixel array. Distribution of the value of the measured time (converted output code ).Threshold equalization has been done. Large signal (> 4000 e- ) and low threshold operation (350 e-). Output Code_2 Output Code_256

Measured time (converted output code), ns115 118 121 124 127 130Entries3060901200time interval 4bin1.8 ns = 7.2 nsDue to uneven delay inside the read-out circuit the pixels will give different values for the measured time (converted output code). These values are spread across 4 bins of the TDC (7.2ns). - In the future we will solve this problem by means of using a faster comparator (internal delay close to 1.8 ns).

V.GromovRD51 Workshop, 4/18/2008

15Conclusions and plans. A small chip sensor array has successfully been prototyped in the GOSSIP0-2 chip in 0.13 m CMOS technology. The TDC per pixel with local oscillator satisfies the design requirements: low power consumption, high time resolution (1.8 ns bin) and simplicity.The front-end circuit of the pixels readout will benefit from the low detector parasitic capacitance and no need to compensate for the leakage current.Low threshold (350 e-) and fast peaking time (20 ns) enable for high quality drift time measurements (jitters 1.8 ns) at large input signals (>4000 e-) and after accurate threshold equalization.Plans:The DC feedback in the preamplifier will be revised (matching).A faster comparator circuit is required in order to reduce internal delay, spread and jitter.A small-area detector will be constructed on top of the GOSSIPO-2 chip. This detector will be tested on the beam in the end of 2008.

V.GromovRD51 Workshop, 4/18/2008

16Additional slide.Protection against discharges.

Metal layer LMMetal layer TDPolymideOxideHigh Resistive Amorphous Silicon

20um3umLayout of the input padRfbCp-sub 10fFQdischargeOutputACp-grid 0.5fFRprot 1M- protective resistor causes neither signal distortionnor noise increase as long as RprotCp-grid is less than 1ns.

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17Additional slide.

Integrated Grids.

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Additional slide. Time scan.Delay of the Test pulse, nsMeasured time (converted output code) [ns]Measured time (converted output code) [ns]Threshold equalization has been done. Low threshold operation (350 e-). Signal = 3000 e- Signal = 1200 e-