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Hynix Semiconductor Inc. June 24, 2009 TSV (Through Silicon Via) 소개
Hynix Semiconductor Inc.
June 24, 2009
TSV (Through Silicon Via) 소개
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Contents
Background
TSV Process
Example Of TSV
3 / 47Source: Yole Development, Semicon Korea 2008
Advanced Packaging Tech Platforms
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Source : Seiko Epson사, IEEE Trans. Adv. Pack., 28(3), Aug., 2005, pp. 367
Through Silicon Via Technology
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TSV 3D Stack Package
TSV 3D Stack Package
Wafer에 via hole을 형성하여 chip to chip, chip to wafer 또는 wafer to wafer contact으로 3D stack
High density 및 small size package 구현 가능
High speed 구현 가능
Source : 3D IC Report, Yole Development, 2007
<TSV> Through Si Via<MCP> Multi Chip Package
2D configuration
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Global interconnection length : SOC vs 3D
TSV 3D Stack Package
Wafer에 via hole을 형성하여 chip to chip, chip to wafer 또는 wafer to wafer contact으로 3D stack
High density 및 small size package 구현 가능
High speed 구현 가능
TSV 3D Stack Package
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Patent
US 3,648,131 ‘Hourglass-shaped conductive connection through semiconductor structures’ IBM (1972) Terminated
US 4,239,312 ‘Parallel interconnect for planar arrays’ Huges Aircraft Company (1978) Terminated
Number of patent increase rapidly after 2001 Growth stage in the technology life
Development of enabling technology for TSV such as RIE, Bosch process, wafer thinning …
Development of enabling technology
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Source: Yole Development, 2007
3D TSV Market Drivers
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3D Interconnection Tech Roadmap
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TSV Impact for Image Sensors
Source: Yole Development, 2007
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2006 2007 2008 2009 2010 2011 CAGR(%)
All Wire Bonded 1,495 1,747 2,080 2,515 3,073 3,690 19.8
WB + FC 160 155 244 372 544 758 36.6
All Flip Chip 38 124 152 189 234 287 49.8
Through-ViaInterconnection
21 21 74 166 309 470 86.6
Other 21 19 18 20 21 21 0.1
Total 1,735 2,065 2,568 3,262 4,182 5,227 24.7
Interconnection of Stacked Package
Source : Advanced IC Packaging, 2007 Edition
Units (M)
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2006 2011
Source : Advanced IC Packaging, 2007 Edition
Interconnection of Stacked Package
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Contents
Background
TSV Process
Example Of TSV
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TSV 3D SiP Module Concept
Source: Yole Development, Semicon Korea 2008
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3D-TSV Process Scheme
Source : TEL, 2009
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3D-TSV Process SchemeProcess Scheme 장점 단점
Via First
Separate TSV before FEOL/BEOL
Via filling process is not temperature limited by the CMOS barrier (~450°C)
Better design flexibility
Poly Si used as via filling mater. → High resistivity
High alignment accuracy is required
Low compatibility with conventional PKG
Via MidBetter design flexibility
Cu used as via filling mater. → High conductance
Low compatibility with conventional PKG
Via Last from Front
side
Cu used as via filling mater. → High conductance
High compatibility with conventional PKG
Cost merit (no CMP)
Low design flexibility
Space Factor
Via Last from Back
side
Cu used as via filling mater. → High conductance
High compatibility with conventional PKG
Better design flexibility
Cost merit (no CMP)
back side patterning
After Bonding
No use of carrier wafer
Mirror type chip design
Yield Issue
only W2W bonding
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3D-TSV Process SchemeItem Fill metal Process Bonding
Via First
poly Si Y COC Y IBM, NEC, Elpida, OKI, Tohoku, DALSA…
W N COW Y
Cu N WOW Y
Via Mid
poly Si Y COC Y Tezzaron, IMEC, RPI, Ziptronix, Chartered Semiconductor, TSMC…
W YCOW Y
WOW YCu Y
Via Last
from front side
poly Si ? COC Y
Infineon, IZM, ASET, Samsung…
W YCOW Y
Cu YWOW Y
Via Last from back
side
poly Si ? COC Y
ZyCube, Intel, IMEC…
W Y COW Y
Cu Y WOW Y
after bonding
poly Si ? COC N
RPI, RTI, IBM, MIT…
W Y COW N
Cu Y WOW Y
Source : Yole Development, 2007
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Source: Yole Development, Semicon Korea 2008
Different 3D Interconnect Worlds
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TSV Process and Equipment Flow
Source : EMC-3D workshop (2007, Korea)
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TSV Technology
Source : 3D IC Report, Yole Development, 2007
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TSV formation process by BOSCH process
< Schematic of the principle of the BOSCH process >
(a) Etch step(2): Isotropic etching of Si by F containing plasma
(b) Passivation step: Teflon-like polymer deposition as a protection layer
(c) Etch step(1): Etching of polymer layer by ion bombardment
(d) Etch step(2): Isotropic etching of Si by F containing plasma
(b)→(c)→(d) cyclic process
Source : KAIST
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W
D
UC
– Minimize undercut (UC)
• voids/fill issues
– Smooth sidewalls
• Adhesion,
• Dielectric breakdown
– Profile requirements
• Vertical or slight taper to improve deep fill
– High Selectivity to PR
• Device protection
– High ER
• High throughput
Photo Resist
DielectricDevices
TSV Etch Technical Requirements
Source : Lam Research, 2007
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Laser Drilling Bosch processnon-Bosch process
One step forming process for Al, Oxide, Si
Si debris
Side wall bowing
Via diameter is limited (20-25um today)
Accuracy issue (<5um)
Serial process → Throughput issue
Plasma etching by F radical with pressure or power tuning
Smooth side wall
High etch rate compared with Bosch process
Need of several chemical for multilayer etching
Oxide undercut issue
Plasma etching by F radical with repeat of etch and deposition step
High aspect ratio Step coverage issue of adhesion/seed layer process
Need of several chemical for multilayer etching
Side wall roughness
Relatively slow etch rate
Under development of equipment for 300mm wafer
“Laser” or “DRIE”?
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Via Filling
Source : 3D IC Report, Yole Development, 2007
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W2W vs. C2W
Source : 3D IC Report, Yole Development, 2007
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W2W vs. C2W
Source : 3D IC Report, Yole Development, 2007
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Temporary Bonding (Principle)
Source : 3D IC Report, Yole Development, 2007
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Wafer Thinning Technology
Source : 3D IC Report, Yole Development, 2007
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Dicing Before Grinding
Source : 3D IC Report, Yole Development, 2007
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Bonding Technology
Source : 3D IC Report, Yole Development, 2007
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Bonding Technology
Source : 3D IC Report, Yole Development, 2007
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Contents
Background
TSV Process
Example Of TSV
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Companies and R&D Institutes with TSV Design3D PlusAssociation of Super-Advanced Electronic Technologies (ASET)Elpida MemoryEpson America/Seiko EpsonERSO/ITRI's Advanced Packaging Technology Center (APC)Fraunhofer Institute and Reliabilirt and Microintegration IZMHong Kong University of Science and TechnologyIBMIMEC's Advanced Packaging and Interconnect Center (APIC)Infineon TechnologiesIntel CorporationInvine Sensors (routing on the sides of Neo-Stacks)Korea Advanced Institute of Science and Technology (KAIST)Micron Semiconductor Asia Pte. Ltd.NEC ElectronicsOki Electric InductoryRensselaer Polytechnic InstituteRTI InternationalSamsung Electronics Co., Ltd.State University of New York at BinghamtonTezzaron Semiconductor Corp.University of AlbanyZiptronixZycube Co., Ltd. (furthering ASET technology)
Source : Advanced IC Packaging (2007)
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Example for CPU + Memory Stacking : Intel
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Source : Michael W. Newman, ECTC2006
Intel
Via process DRIE, Via last technology
Via profile tapered via profile
Via depth 120um
Via material electroplating Cu
Bump process One-step plating of via filling and bump plating
Image
Example for CPU + Memory Stacking : Intel
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Samsung has started TSV R&D in 2002.
Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for Laser Drilling : Samsung
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Core techniques for WSP of SamsungTSV formation : Laser Drill, Electroplating Via FillingMulti-Chip BondingWafer Thinning : ~50umThin Wafer Handling Process
Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for Laser Drilling : Samsung
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In April 2006, Samsung has announced the development of a wafer-level stack package (WSP) of high density memory chips
Using laser drilled through-silicon via (TSV) interconnection technology
16Gb memory density (2Gb NAND × 8 chip, 560um)
30% thinner and 15% smaller footprint than an equivalent wire-bonded MCP solution
Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for Laser Drilling : Samsung
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In April 2007, Samsung Electronics announced that it has developed the first all-DRAM stacked memory package using TSV technology
the TSV is housed within an aluminum (Al) pad to escape the performance-slow-down effect caused by the redistribution layer
four 512 Mb DDR2 DRAM chips that offer a combined 2 Gb of high density memory
4 GB DIMM (dual in-line memory module)
Source : Digital Daily News, April 2007
Example for Laser Drilling : Samsung
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Jointly develop 3D TSV stacked packageNEDO grant program8 DRAM Core & 1 controller chip
Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for DRAM Stacking : Elpida, NEC, Oki
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TSV formation within DRAM dieVia first process & Polysilicon TSVSpread-out functions
Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for DRAM Stacking : Elpida, NEC, Oki
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Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Example for DRAM Stacking : Elpida, NEC, Oki
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Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Via first process Polysilicon TSVCascaded interconnection
Example for DRAM Stacking : Elpida, NEC, Oki
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Source : 3D Architecture for Semiconductor Integration and Packaging, RTI, 2006
Bump structure
Example for DRAM Stacking : Elpida, NEC, Oki
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Example for Via Last & From backside : IMEC
Source : IMEC
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Example for Via Last & From backside : IMEC
Source : IMEC
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Example for Via First & After CMOS : IMEC
Source : IMEC
