Implementation of a BPSK Transceiver for use with KUAR
Ryan ReedM.S. CandidateInformation and Telecommunication Technology CenterElectrical Engineering and Computer ScienceThe University of [email protected]
2May 8, 2006
Outline• Motivation• KUAR Overview• Thesis Objectives• Proposed Transceiver Design
– Simulink, Xilinx, Modelsim• Results• Conclusion• Future Work
3May 8, 2006
Motivation• Development of the KUAR
– Experimental radio• Radiates between 5-6 GHz• Bank of modulation schemes• Media access protocols• Adaptation mechanisms
– Policy development– JTRS Test bed
[1]
4May 8, 2006
KUAR Overview• Several Components
– Battery– Digital board
• FPGA, DAC, ADC
– CPH– RF Front End– Antennas
[1]Images of the KUAR
Vertix-II ProXC2VP20
ADCAD664580 Msps
DACAD9777160Msps
SRAM4 MB
32
3232
32Rx_IRx_Q
Tx_ITx_Q
To/FromRF Board
FLASH32 MB
PPCIBM405EP
Ethernet
SDRAM32MB
CPHDigital Board
5May 8, 2006
Thesis Objectives• Design and construct 1 Mbaud BPSK
Transceiver– 5 MHz Carrier, 80 Msps– Synchronize the carrier– Synchronize the symbol– Use minimal resources
6May 8, 2006
Method of Carrier Synchronization
[2]Rice’s digital Costas loop
7May 8, 2006
Method of Symbol Synchronization
z+1
+
-
[3]
Integrate
z-1
sign Decision
Georghiades Early-Late Algorithm
8May 8, 2006
Proposed Transceiver
Addr Ph Direct Digital
Synthesizer
[ ] [ ]⎟⎠⎞
⎜⎝⎛ += nnns φπ
8052cos
Block diagram of transmitter
9May 8, 2006
Proposed Transceiver
Block diagram of receiver
10May 8, 2006
Simulink Simulation• Proposed Transceiver Design (Simulink)
– Transmitter• Expected outputs
– Receiver modules• Carrier synchronization• Symbol synchronization• SNR vs. BER
11May 8, 2006
Simulink Simulation
1
cos
cos
cosine
1/z
Rate T ransi tion
Product
pi
Gain1
2*pi
Gain
Int_Carrier_Freq
Constant
Clock
1
Bi t
Simulink model of transmitter
12May 8, 2006
Simulink Simulation
Ideal constellation of the transmitter
13May 8, 2006
Simulink Simulation
Ideal waveform of the transmitter
14May 8, 2006
Simulink Simulation
Uniform RandomNum ber
sin
T rigonom etricFunction1
cos
T rigonom etricFunction
Phase sin
T ransm i tter
DSP
Sine Wave3
DSP
Sine Wave2
Sign
Scope6
Scope5
Scope1
round
RoundingFunction
I_RxQ_Rxcos_adjs in_adj
I_out
Q_out
Rotate
Rate T ransi tion
Product1
Product
I_In
Q_InPh_adj
Loop Fi l ter
Lookup T able
-125Z
In teger Delay
Error Rate Calculation
T x
Rx
Error RateCalculation
SamplesSy m bols
Correction
Early/LateBi t Recovery
In1 Out1
Dum p1
In1 Out1
Dum p
num (z)
80 Discrete Fi l ter1
num (z)
80 Discrete Fi l ter
Add
|u|
Abs
AWGN
AWGNChannel
Top level of the simulation of the receiver
15May 8, 2006
Simulink Simulation
z
1
Uni t Delay2
z
1
Uni t Delay1
z
1
Uni t Delay Sign
Scope6
Early
Current
Late
Early Sam ple
Current Sample
Late Sample
Sam pler
Correction Pulse
Sam ple T im er
RepeatingSequence
Product1
Product
uy
fcnEm beddedM AT LAB Function
num (z)
80
Discrete Fi l ter
Early-late algorithm simulation
16May 8, 2006
Simulink Simulation
Example of the early-late algorithm synchronizing to a signal
17May 8, 2006
Simulink Simulation
sin
Trigonometric
Function1
cos
Trigonometric
Function
Sign
I_Rx
Q_Rx
cos_adj
sin_adj
I_out
Q_out
Rotate
I_In
Q_In
Ph_adj
Loop Filter
The loop filter section
18May 8, 2006
Simulink Simulation
Transmitted
Estimated
Correction
The loop filter synchronizing under constant phase error
19May 8, 2006
Simulink Simulation
Transmitted
Estimated
Correction
The loop filter synchronizing under constant frequency error
20May 8, 2006
Simulink Simulation
-2 -1 0 1 2 3 4 510
-7
10-6
10-5
10-4
10-3
10-2
10-1
100
SNR (dB)
BE
R
SNR vs. BER Results
Simulated
Gevargiz
Simulation of the proposed receiver compared to Gevargiz’s receiver
21May 8, 2006
Xilinx Implementation• System overview• Boxcar filter implementation• Loop filter implementation• Synthesis sizing
22May 8, 2006
Xilinx Implementation
Top level of the Xilinx schematic of the receiver
23May 8, 2006
Xilinx Implementation
+
+
-
⎯ (n)xx(n)
x(79), x(78),…,x(1),x(0)
Xilinx schematic of the boxcar filter
24May 8, 2006
Xilinx Implementation
Xilinx schematic of the loop filter
25May 8, 2006
Xilinx SynthesisTable of resource usage
Receiver Transmitter Total
Slices 1481/9280 158/9280 1639/9280
Multipliers 10/88 0/88 10/88
BRAMs 5/88 4/88 9/88
Maximum Freq. 151.469 MHz 250.062 MHz 151.469 MHz
26May 8, 2006
Modelsim Results• Transmitter output• Loop filter response• Early-late gate loop response
27May 8, 2006
Modelsim Results
Output
-40000-30000-20000-10000
010000200003000040000
0 20 40 60 80 100 120
Time
Ampl
itude
Output waveform of the transmitter
28May 8, 2006
Modelsim Results
Loop Filter Results
-300,000-200,000-100,000
0100,000200,000300,000400,000
0 2 4 6 8
Time sample
Valu
e PredictedCalculated
Output of the loop filter compared to expected results
29May 8, 2006
Modelsim Results
Simulated output of the symbol synchronizer with flat input
30May 8, 2006
Modelsim Results
Simulated output of the symbol synchronizer with increasing input
31May 8, 2006
Modelsim Results
Simulated output of the symbol synchronizer with decreasing input
32May 8, 2006
Concluding Remarks• Communicated 1 Mbaud of information
with carrier of 5 MHz• Synchronized with the transmitted carrier• Synchronized the symbol• Minimized resources• Provided a tool for researching SDR and
communications
33May 8, 2006
Future Work• This was stepping stone
– M-PSK, SSB-AM– Channel sounding, equalization, fading, multi-
path, pulse shaping• Library of modulation schemes
34May 8, 2006
References[1] G. J. Minden, “KU Agile Radio Overview,”
University of Kansas, Lawrence, Kansas, 2005.
[2] M. Rice, “Introduction to Digital Communication Theory,” 2004, http://www.ee.byu.edu/class/ee485public/ee485.fall.04/. (Will be a book soon)
[3] C. Georghiades, “Synchronization,” The Communications Handbook, 2nd ed., Ed. J. Gibson, Boca Raton: CRC Press, 2002.
Questions?