Introduction to VHDLIntroduction to VHDLJoseph Collins, 3A Software Eng.Joseph Collins, 3A Software Eng.with files from Dr. W.D. Bishop, with files from Dr. W.D. Bishop, P.EngP.EngEmail: Email: j4collin@engmail.uwaterloo.caj4collin@engmail.uwaterloo.ca

What is VHDL?What is VHDL? Very High-Speed Integrated CircuitVery High-Speed Integrated Circuit HardwareHardware DescriptionDescription LanguageLanguage

A popular tool for designing digital A popular tool for designing digital hardwarehardware

Important ConceptsImportant Concepts EntityEntity

– What the hardware looks like to the What the hardware looks like to the outside worldoutside world

– Defines inputs and outputsDefines inputs and outputs

ENTITY lab1 IS PORT ( r1, r0 : in std_logic; x, y, z : in std_logic; a, d0, d1 : out std_logic );END lab1;

Important ConceptsImportant Concepts ArchitectureArchitecture

– This is the implementation of your This is the implementation of your entity.entity.

– This is where you put your gates and This is where you put your gates and stuff.stuff.

ARCHITECTURE main OF lab1 ISSIGNAL temp : std_logic;

BEGINa <= r0 AND r1;temp <= y OR z;d0 <= x AND temp;d1 <= (r0 AND x) OR temp;

END main;

VHDL Data TypesVHDL Data Types std_logicstd_logic

– A wireA wire– Can be set to ‘1’ or ‘0’ (among other Can be set to ‘1’ or ‘0’ (among other

things)things)– SIGNAL a : std_logic;SIGNAL a : std_logic;– use ieee.std_logic_1164.alluse ieee.std_logic_1164.all

VHDL Data TypesVHDL Data Types std_logic_vectorstd_logic_vector

– A group of wires with a similar purposeA group of wires with a similar purpose– SIGNAL v : std_logic_vector (3 DOWNTO 0);SIGNAL v : std_logic_vector (3 DOWNTO 0);

– Wires can be assigned:Wires can be assigned: individually: individually: v(3) <= ‘0’;v(3) <= ‘0’; in groups: in groups: v(1 DOWNTO 0) <= v(3 DOWNTO 2);v(1 DOWNTO 0) <= v(3 DOWNTO 2); all at once: all at once: v <= “1001”;v <= “1001”;

– use ieee.std_logic_1164.alluse ieee.std_logic_1164.all

VHDL Data TypesVHDL Data Types signed/unsignedsigned/unsigned

– Used to represent signed and Used to represent signed and unsigned numbersunsigned numbers

– SIGNAL num : signed (2 downto 0);SIGNAL num : signed (2 downto 0);– Assignment similar to Assignment similar to std_logic_vectorstd_logic_vectorss

– Can do arithmetic on theseCan do arithmetic on these This includes, addition, subtraction, This includes, addition, subtraction,

multiplication, and comparisonsmultiplication, and comparisons– use ieee.numeric_std.alluse ieee.numeric_std.all

Converting Between Converting Between Data TypesData Types One can convert between signed, One can convert between signed,

unsigned and std_logic_vector unsigned and std_logic_vector explicitlyexplicitly– SIGNAL x : std_logic;SIGNAL x : std_logic;– SIGNAL num : unsigned (3 DOWNTO 0);SIGNAL num : unsigned (3 DOWNTO 0);– SIGNAL v : std_logic_vector (3 SIGNAL v : std_logic_vector (3 DOWNTO 0);DOWNTO 0);

– ……– num <= unsigned(v);num <= unsigned(v);– v <= std_logic_vector(num);v <= std_logic_vector(num);– x <= v(1);x <= v(1);

Combinational Combinational CircuitryCircuitry Statements that may be helpfulStatements that may be helpful

– When-else statementsWhen-else statements

– Case statementsCase statements

--a is std_logic, b is std_logic_vector (3 DOWNTO 0)--x and s are unsigned (3 DOWNTO 0)s <= x – 10;b <= “0000” WHEN a = ‘1’ ELSE std_logic_vector(x) WHEN x < 10 ELSE std_logic_vector(s);

s <= x – 10;WITH x(3 DOWNTO 1) SELECTb <= std_logic_vector(s) WHEN “101” | “110” | “111”, std_logic_vector(x) WHEN OTHERS;

What questions do What questions do you have so far?you have so far?

ProcessesProcesses So far, we’ve covered basic So far, we’ve covered basic

combinational circuitrycombinational circuitry Processes allow for much more Processes allow for much more

human-readable designshuman-readable designs Processes can be combinational or Processes can be combinational or

sequentialsequential– Will not cover combinational because Will not cover combinational because

they are frowned upon by SE141 TAsthey are frowned upon by SE141 TAs

Sequential ProcessesSequential Processes Sequential processes run on a Sequential processes run on a

clock signalclock signal– Usually involve one or more flip-flopsUsually involve one or more flip-flops

They are NOT sequential in the They are NOT sequential in the sense that the hardware will sense that the hardware will execute one step at a timeexecute one step at a time– Hardware runs in parallelHardware runs in parallel– You can make things run You can make things run

sequentially by separating tasks into sequentially by separating tasks into multiple clock cycles.multiple clock cycles.

D Flip-Flop with Chip D Flip-Flop with Chip EnableEnable Probably the second-simplest Probably the second-simplest

sequential process you will ever sequential process you will ever run intorun into

PROCESSBEGIN

WAIT UNTIL RISING_EDGE(clock);IF (ce = ‘1’) THEN

q <= d;END IF;

END PROCESS;

State MachinesState Machines Flip Flops that represent a state in Flip Flops that represent a state in

your systemyour system Multiple encoding typesMultiple encoding types

– One-hotOne-hot– GrayGray– BinaryBinary

Usually used in sequential Usually used in sequential processesprocesses

What questions do What questions do you have?you have?

Hardware InterfacingHardware Interfacing You can easily use a provided piece You can easily use a provided piece

of hardware as part of a larger circuitof hardware as part of a larger circuit– Make sure you understand the specsMake sure you understand the specs– You needn’t know the VHDL code You needn’t know the VHDL code

behind this piece of hardwarebehind this piece of hardware This allows you to work This allows you to work

independently on separate parts of independently on separate parts of your labyour lab

Interfacing a Block of Interfacing a Block of MemoryMemory We wish to integrate a piece of We wish to integrate a piece of

256x256 memory into our circuit256x256 memory into our circuitARCHITECTURE main OF circ IS

COMPONENT mem ISPORT (

i_add : in std_logic_vector (7 DOWNTO 0);i_wren : in std_logic;i_clock : in std_logic;i_data : in std_logic_vector (7 DOWNTO 0);o_q : out std_logic_vector (7 DOWNTO 0)

);END COMPONENT mem;SIGNAL address, data, q : std_logic_vector (7 DOWNTO 0);SIGNAL wren, clk : std_logic;

BEGIN…

mem1: mem PORT MAP (address, wren, clk, data, q);…END main

SimulationSimulation We have covered hardware that We have covered hardware that

you can synthesize nicely for use you can synthesize nicely for use on an FPGA boardon an FPGA board

VHDL can be used to simulate VHDL can be used to simulate these circuitsthese circuits– Note: we will be using non-Note: we will be using non-

synthesizable VHDL for doing synthesizable VHDL for doing simulationssimulations

How to SimulateHow to Simulate Develop your simulation planDevelop your simulation plan Prepare a new entity and do a Prepare a new entity and do a

port mapport map Use wait statements to assignUse wait statements to assign

your inputsyour inputsclock_proc: PROCESS BEGIN -- 50 MHz clockclock_proc: PROCESS BEGIN -- 50 MHz clockclk <= ‘0’;clk <= ‘0’;wait for 10 ns;wait for 10 ns;clk <= ‘1’;clk <= ‘1’;wait for 10 ns;wait for 10 ns;

END PROCESSEND PROCESS

Simulation ExampleSimulation ExampleENTITY tb_lab1 ISENTITY tb_lab1 ISEND tb_lab1END tb_lab1

ARCHITECTURE main OF tb_lab1 ISARCHITECTURE main OF tb_lab1 ISCOMPONENT lab1 ISCOMPONENT lab1 IS

PORT (PORT (r0, r1, x, y, z : in std_logic;r0, r1, x, y, z : in std_logic;a, d0, d1 : out std_logica, d0, d1 : out std_logic

););END COMPONENT lab1;END COMPONENT lab1;SIGNAL r0, r1, x, y, z, a, d0, d1 : std_logic;SIGNAL r0, r1, x, y, z, a, d0, d1 : std_logic;

BEGINBEGINlab1_inst : lab1 PORT MAP (r0, r1, x, y, z, a, d0, d1);lab1_inst : lab1 PORT MAP (r0, r1, x, y, z, a, d0, d1);

r0_proc : PROCESS BEGINr0_proc : PROCESS BEGINr0 <= ‘0’;r0 <= ‘0’;wait for 10 ns;wait for 10 ns;r0 <= ‘1’;r0 <= ‘1’;wait for 10 ns;wait for 10 ns;

END PROCESS;END PROCESS;

r1_proc : PROCESS BEGINr1_proc : PROCESS BEGINr1 <= ‘0’;r1 <= ‘0’;wait for 20 ns;wait for 20 ns;r1 <= ‘1’;r1 <= ‘1’;wait for 20 ns;wait for 20 ns;

END PROCESS;END PROCESS;--etc.--etc.

END main;END main;

What questions do What questions do you have?you have?

Common PitfallsCommon Pitfalls Multiple Signal DriversMultiple Signal Drivers

– When you assign to a signal in When you assign to a signal in multiple locations (without multiple locations (without appropriate ifs)appropriate ifs)

Usually in multiple processesUsually in multiple processes– Best preventative measure: avoid Best preventative measure: avoid

assigning to more than one signal in a assigning to more than one signal in a given processgiven process

Processes run parallel to each otherProcesses run parallel to each other

Common PitfallsCommon Pitfalls Invalid State = Undefined Invalid State = Undefined

BehaviourBehaviour– If your state machine enters an If your state machine enters an

invalid state, it should return to a invalid state, it should return to a pre-defined “reset” statepre-defined “reset” state

– This can happen by programmer This can happen by programmer error or due to environmental error or due to environmental factorsfactors

What questions do What questions do you have?you have?This is about all I have.This is about all I have.

Do not hesitate to Do not hesitate to contact me!contact me!- Email: - Email: j4collin@engmail.uwaterloo.caj4collin@engmail.uwaterloo.ca- I often hang out in SE lounge/lab - I often hang out in SE lounge/lab and/or MathSoc (MC 3038)and/or MathSoc (MC 3038)- Have a good Pi Day tomorrow- Have a good Pi Day tomorrow