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1 Introduction to VHDL Spring 09
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Introduction to VHDL
Spring 09
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What is VHDL?• VHDL can be uses to model and synthesise digital
systems.• VHDL = VHSIC Hardware Description Language
– VHSIC = Very High Speed Integrated Circuit
• Developed in early 1980’s by DOD.• Veralog is an older hardware description language.
– Some (for example ASIC designers) prefer Veralog.
• ANSI/IEEE Std 1076-1993 is the version we will use.– ANSI/IEEE Std 1076-2002 is the newest version.
• VHDL is a very complex language.• VHDL descriptions can be synthesized and implemented
in programmable logic.– Synthesis tools can accept a only subset of VHDL.
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VHDL• Primarily for modeling digital systems.
– Lesser extent analog
• Reasons for modeling– Specify requirements– Simulation, testing, verification– Synthesis
• Advantage– Increase reliability– Minimize cost and design time– Increase flexibility and ease with which a system can be modified.– Avoid design errors through use of simulation.
• Problem – We model our conception of the system.– May not accurately reflect reality.
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Types• The concept of type is important and fundamental when describing data in
VHDL.• The type of a data object defines the set of values that an object can assume,
as well as the set of operations that can be performed on those values.– For example data object of type bit can assume a value of either ‘0’ or ‘1’, and
can support operators such as “and”, “or”, “xor”, “nand”, etc.
• VHDL is a strongly typed language.• Scalar data types consists of single, indivisible values.• Besides the usual types such as integer and real, VHDL also provides other
types such as time and bit.• User defined types are frequently employed.• We will make extensive use of standard libraries that define special types
such as stdlogic. – We will use stdlogic in place of bit. Stdlogic can assume more values that 0 and
1. For example high impedance and don’t care values.
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VHDL type classification
See DG p 47.
10 ns
“101110001110001”
‘1’
125
FALSE‘A’
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Operations that can be performed on type integer. See p 35
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Operations on type Boolean and type Bit. See p44
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Constants, variables, and signals
• An object is a named item in a VHDL model that has a value of a specific type. There are four classes of objects: constants, variables, signals, and files.
• The use of constants and variables in VHDL is similar to what you are already familiar with from other programming languages.
• The idea of a signal is a new concept required because in VHDL we are modeling electrical (digital) systems.– Signals usually represent voltages on wires.– But you can also use a signal in place of a variable. – Sometimes it may not matter if you use a signal or a variable.– Other times there may be subtle reasons for using one over the other.– Initially you may tend to be confused by the distinction between signals and
variables, but this will be made clear later.
• We will discuss of files if needed.• Objects must be declared prior to use.
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Constantsconstant CONST_NAME: <type_spec> := <value>;-- Examples of Declaration of Constants:constant GO: BOOLEAN := TRUE;constant Max: INTEGER := 31;constant HexMax: INTEGER := 16#FF#; -- hex (base 16) integerconstant ONE: BIT := '1';constant S0: BIT_VECTOR (3 downto 0) := "0000";constant S1: bit_vector(15 downto 0) := X"AB3F“; -- hex stringconstant HiZ: STD_LOGIC := 'Z'; -- Here Z is high impedance.constant Ready: STD_LOGIC_VECTOR (3 downto 0) := "0-0-"; -- 0’s &
don’t caresNote: VHDL is not case sensitive.• BOOLEAN, INTEGER, BIT, etc are examples of predefined VHDL types.
– VHDL is a strongly typed language.– Cannot for example directly assign a bit or std_logic value to an integer type.
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VariablesVAR_NAME := <expression>;-- exampleCount := 10;Vbit := '0';• Declarationvariable VAR_NAME: <type_spec>;-- example:variable Test: BOOLEAN;variable Count: INTEGER range 0 to 31 := 15; -- Set initial value to 15.variable vBIT: BIT;variable VAR: BIT_VECTOR (3 downto 0);variable VAR_X: STD_LOGIC := ‘0’; -- Set initial value to ‘0’.variable VAR_Y: STD_LOGIC_VECTOR (0 to 3);
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Signals
SIG_NAME <= <expression>;-- ExamplesBitX <= ‘1’;• Declarationsignal SIG_NAME: <type_spec>;-- example:signal Flag: BOOLEAN := TRUE; -- TRUE is the initial vlauesignal intX: INTEGER range 0 to 31;signal BitX: BIT := ‘1’;signal Control_Bus: BIT_VECTOR (3 downto 0);signal X: STD_LOGIC;signal Y: STD_LOGIC_VECTOR (0 to 3) := “0000”;
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SignalsEvents, Propagation Delay, and Concurrency
• Signals– Signals of type bit take on values of 0 and 1.– Digital components (gates, flip-flops, etc.) respond to input signals to
produce output signals.– A signal change is called an event.– The effect of an event is delayed by the propagation delay through the
component. VHDL allows for associating a delay with a signal.• Z <= X and Y after 2 ns;
– Signals may propagate through several components concurrently.Z <= X and Y after 2 ns;V <= (Z xor not W) nand X after 3 ns;W <= X or Y after 1 ns;
– VHDL is an event driven concurrent programming language.• Statements may not execute sequentially.• This makes VHDL “hard.”
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VHDL example EX 1-- EX1 - Signal example
entity ex1 is
end entity ex1;
architecture ex1_arc of ex1 is
signal X: BIT;
begin
-- concurrent signals assignments
X <= not X after 10 ns;
end architecture ex1_arc;
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-- EX2
-- Signal example
-- File: ex2.vhd
-- created: 09/19/01
entity ex2 is
end entity ex2;
architecture ex_arc of ex2 is
signal X: BIT;
signal Y: BIT;
begin
-- concurrent signals assignments
X <= not X after 10 ns;
Y <= '1' after 15 ns, '0' after 25 ns;
end architecture ex_arc;
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std_logic_1164 multi-value logic system
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care );
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resolution function – resolves two drives for a single signal. Std_logic has a built in resolution function.
CONSTANT resolution_table : stdlogic_table := (-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
S <= ‘1’;
S <= ‘0’;
Don’t drive signal from multiple sources!
‘X’ indicates an unknown value. This can be caused by the resolution function as shown below.
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Why have ‘U’ in std_logic types?
• Any uninitialized type assumes the left most value of that type.– TYPE std_ulogic IS ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' );
– TYPE BIT is (‘0’, ‘1’);
• What is the initial value?
variable vBIT: BIT;
variable VAR_X: STD_LOGIC := ‘0’;signal BitX: BIT := ‘1’;signal X: STD_LOGIC;Signal N: integer;
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-- EX2
-- Signal example
-- File: ex2.vhd
-- created: 09/19/01
entity ex2 is
end entity ex2;
architecture ex_arc of ex2 is
signal X: BIT;
signal Y: BIT;
begin
-- concurrent signals assignments
X <= not X after 10 ns;
Y <= '1' after 15 ns, '0' after 25 ns;
end architecture ex_arc;
Recall EX2: Lets use std_logic in place of bit.
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-- EX3 - Signal example
-- File: ex3.vhd
-- created: 09/19/01
library IEEE;
use IEEE.std_logic_1164.all;
entity ex3 is
end entity ex3;
architecture ex_arc of ex3 is
signal X: STD_LOGIC;
signal Y: STD_LOGIC;
begin
X <= not X after 10 ns;
Y <= '1' after 15 ns, '0' after 25 ns;
end architecture ex_arc;
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What happened?
• In VHDL uninitialized signals and variables assume the left most value of the type.
– STD_LOGIC initializes to “U”.
X <= not X after 10 ns;
Y <= '1' after 15 ns, '0' after 25 ns;-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
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-- EX3 - Signal example
-- File: ex2.vhd
-- created: 09/19/01
library IEEE;
use IEEE.std_logic_1164.all;
entity ex3b is
end entity ex3b;
architecture ex_arc of ex3b is
signal X: STD_LOGIC := '1'; -- init X
signal Y: STD_LOGIC := '0'; -- init Y
begin
-- concurrent signals assignments
X <= not X after 10 ns;
Y <= '1' after 15 ns, '0' after 25 ns;
end architecture ex_arc;
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Another ExampleLIBRARY IEEE;USE work.ALL;USE IEEE.std_logic_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY tb is END tb;ARCHITECTURE test OF tb IS constant ALL_ONES: std_logic_vector(3 downto 0) := X"F"; constant Some_Ones: std_logic_vector(3 downto 0) := X"A"; SIGNAL Q : std_logic_vector(3 downto 0) := (others => '0'); --"0000"; signal X : std_logic_vector(3 downto 0);BEGIN Q <= Q(2 downto 0) & not Q(3) after 5 ns; X <= ALL_ONES after 10 ns, Some_Ones after 15 ns, "0000" after 20 ns;END test;
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And Or gate example
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ABorC is port (A : in std_logic; B : in std_logic; C : in std_logic; F : out std_logic);end ABorC; architecture arch of ABorC is signal X : std_logic;begin X <= A and B after 1 ns; F <= X or C after 1 ns;end;
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3C
FBX
A1
2
3
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Test bench for and or example
LIBRARY IEEE;USE work.all;USE IEEE.Std_Logic_1164.all;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY tb IS END ENTITY tb;Architecture TEST of tb is SIGNAL X: std_logic_vector (2 downto 0) := "000"; SIGNAL Y: std_logic;begin U1: ENTITY work.ABorC(arch) PORT MAP(A => X(2), B => X(1), C => X(0), F => Y); X <= X + 1 after 10 ns;end test;
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U1: entity work.or3 port map (A => AB, B => ACin , C => BCin , F => Cout);U2: entity work.and2 port map (A => A, B => B, F => AB);U3: entity work.and2 port map (A => B, B => Cin, F => BCin);U4: entity work.and2 port map (A => A, B => Cin, F => ACin);U5: entity work.xor2 port map (A, B, AxorB);U6: entity work.xor2 port map (Cin, AxorB, S);
AB
BA
U5
XOR2
FA
B
ACin
Cin
CoutCin
AB
U4AND2
FA
B
U3
AND2
FA
BBCin
U6
XOR2
FA
B S
U1
OR3
FABC
AxorB
U2
AND2
FA
B
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VHDL design units
• Configuration• Package• Package Body• Entity
– Describes Interface• Describes how the circuit appears form the outside.• Similar to a schematic symbol.
• Architecture– Specifies function
• Describes how the circuit does what it does.
– Data Flow or RTL– Behavioral – Defines in terms of its operation over time.– Structural – A collection of components.
• Initially we will focus on the Entity and Architecture.– Both are always necessary the others are optional.
See DG chapter 5
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library IEEE;use IEEE.std_logic_1164.all;ENTITY and2 is GENERIC(trise : time := 10 ns; tfall : time := 5 ns); PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic);END and2;
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ARCHITECTURE behav OF and2 ISBEGIN one : PROCESS (a,b) BEGIN IF (a = '1' AND b = '1') THEN c <= '1' AFTER trise; ELSIF (a = '0' OR b = '0') THEN c <= '0' AFTER tfall; ELSE c<= 'X' AFTER (trise+tfall)/2; END IF; END PROCESS one;END behav;
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library IEEE; use IEEE.std_logic_1164.all; ENTITY tb IS END tb;ARCHITECTURE test OF tb IS SIGNAL a, b, y, z: std_logic;BEGIN and_y: entity work.and2(behav) GENERIC MAP(tfall => 15 ns) PORT MAP(a, b, y); and_z: entity work.and2(behav) PORT MAP(a, b, z); PROCESS CONSTANT period: time := 40 ns; BEGIN a <= '1'; b <= '0'; WAIT FOR period; a <= '1'; b <= '1'; WAIT FOR period; a <= '0'; b <= '1'; WAIT FOR period; a <= '0'; b <= '0'; WAIT; END PROCESS;END TEST;
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Development steps
• Typical programming language– Compilation
– Link and Load
– Execute
• VHDL
– Analysis• Check design unit for
errors
– Elaboration• Check design hierarchy
– Simulation
– Synthesis
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Modeling Interfaces
• Entity declaration (see Fig 1-7 p 9)– describes the input/output ports of a module
entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );end entity reg4;
entity name port names port mode (direction)
port typereserved words
punctuation
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Modeling Behavior
• Architecture body– describes an implementation of an entity
– may be several per entity
• Behavioral architecture– describes the algorithm performed by the module
– contains• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements
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Behavior Examplearchitecture behav of reg4 isbegin
storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
beginif en = '1' and clk = '1' then
stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;
end if;q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;
wait on d0, d1, d2, d3, en, clk;end process storage;
end architecture behav;
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Modeling Structure
• Structural architecture– implements the module as a composition of subsystems
– contains• signal declarations, for internal interconnections
– the entity ports are also treated as signals
• component instances
– instances of previously declared entity/architecture pairs
• port maps in component instances
– connect signals to component ports
• wait statements
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Structure Example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
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Structure Example
• First declare D-latch and and-gate entities and architectures
entity d_latch isport ( d, clk : in bit; q : out bit );
end entity d_latch;
architecture basic of d_latch isbegin
latch_behavior : process isbegin
if clk = ‘1’ thenq <= d after 2 ns;
end if;wait on clk, d;
end process latch_behavior;
end architecture basic;
entity and2 isport ( a, b : in bit; y : out bit );
end entity and2;
architecture basic of and2 isbegin
and2_behavior : process isbegin
y <= a and b after 2 ns;wait on a, b;
end process and2_behavior;
end architecture basic;
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Structure Example• Now use them to implement a register
architecture struct of reg4 is
signal int_clk : bit;
begin
bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 );
bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 );
bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 );
bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 );
gate : entity work.and2(basic)port map ( en, clk, int_clk );
end architecture struct;
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VHDL Reserved Words
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