ISPD 2000, San DiegoApr 10, 2000 --1--

Requirements for Models ofRequirements for Models ofAchievable RoutingAchievable Routing

Andrew B. Kahng, UCLA

Stefanus Mantik, UCLA

Dirk Stroobandt, Ghent Univ.

Supported by Cadence Design Systems, Inc. and

the MARCO Gigascale Silicon Research Center

ISPD 2000, San DiegoApr 10, 2000 --2--

Outline

• Models of achievable routing • Review of existing models• Validation of models through experiments!• Experimental analysis of assumptions• Future model requirements • Conclusions

ISPD 2000, San DiegoApr 10, 2000 --3--

– wirelength estimation models (Donath, …)– actual placement information

Models of achievable routing

• Required versus available resources• Required versus available resources

ISPD 2000, San DiegoApr 10, 2000 --4--

Models of achievable routing

• Required versus available resourceslimited by routing efficiency factor r

ISPD 2000, San DiegoApr 10, 2000 --5--

Models of achievable routing

• Required versus available resourceslimited by power/ground (signal net fraction si)

ISPD 2000, San DiegoApr 10, 2000 --6--

Models of achievable routing

• Required versus available resourceslimited by via impact factor vi (ripple effect)

utilization factor Ui (available / supplied area)

iiri svU )1(

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Use of achievable routing models

• Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer, ...)

• With given layer characteristics: predict the number of layers needed

• If number of layers fixed: oracle “(not) routable!”(SUSPENS, GENESYS, RIPE, BACPAC, GTX)

• Supplying objectives that guide layout tools to promising solutions (wire planning)

ISPD 2000, San DiegoApr 10, 2000 --8--

Validation is key

• Models must be accurate, must support empirical verification and calibration

• No existing model is validated with real place-and-route data

• Our work concentrates on validation:– understanding reasons for validation gap– processes for model validation– improvements needed in future models

ISPD 2000, San DiegoApr 10, 2000 --9--

Review of existing models

• Sai-Halasz [Proc. IEEE, 1995]– power/ground: si 20%– routing efficiency: r = 40%– via impact: each layer blocks 15% on

layers below with same pitch

– model is widely used– model is rather pessimistic

ISPD 2000, San DiegoApr 10, 2000 --10--

Review of existing models (cont.)

• Chong and Brayton [SLIP, 1999]– layer assignment model

• layer pairs form tiers (H and V)• wires are routed on 1 tier• shorter wires on lower tiers

– available resources model• constant routing efficiency for all layers: r = 65%

• via impact factor vi based on actual via area– each wire uses 2 via stacks (block wires on lower layers)

– total number of wires per layer (thus vias) defined by layer assignment model

H

HV

V }} tier

tier

ISPD 2000, San DiegoApr 10, 2000 --11--

Review of existing models (cont.)

• Chen et al. [private communication, 1999]– layer assignment model similar to Chong’s– available resources model

• constant routing efficiency (40% < r < 66%)• via impact model

– terminal vias and turn vias– each wire uses 2 via stacks– number of terminal vias defined

by layer assignment model– sparse via model = Chong– dense via model: give up 1 track every X tracks– results in via impact proportional to sqrt(Chong’s impact

factor)

H

HV

V }} tier

tier

trac

ks

ISPD 2000, San DiegoApr 10, 2000 --12--

Model validation

• Models can be validated only by testing against comparable experimental results– none of reviewed models was validated– even simple comparison: huge differences

70

65

60

55

50

45

40

350 1 3 4 5Via fill rate (%)

Uti

liza

tion

fac

tor/

laye

r (%

)

Sai-Halasz (M4)

Sai-Halasz (M1)

Chong

Chen

Sai-Halasz (M3)

Sai-Halasz (M2)

ISPD 2000, San DiegoApr 10, 2000 --13--

Model validation (cont.)

• Experimental validation– Typical industry standard-cell block design

• 42.000 cells, 1999, 5 layers• Cadence placement and gridded routing tools• same pitch (1 m) for all layers• via size .62 m• all pins for cells are on M1

• Experimental validation– ensure congested design

Via fill rate (%)

Uti

liza

tion

fac

tor

(%)

Sai-Halasz (M4)

Sai-Halasz (M1)

Chong

Chen

Sai-Halasz (M3)

Sai-Halasz (M2)

75

65

60

55

50

45

40

35

30

70

Exp M2

0 1 2 3 4 65

Exp M4

Exp M3

ISPD 2000, San DiegoApr 10, 2000 --14--

Model validation (cont.)

• Experimental validation– adding virtual vias on M3 and M4 (effect of wires

on virtual upper layers)

Exp M4

Exp M3

Via fill rate (%)

Uti

liza

tion

fac

tor

(%)

Sai-Halasz (M4)

Sai-Halasz (M1)

Chong

Chen

Sai-Halasz (M3)

Sai-Halasz (M2)

75

65

60

55

50

45

40

35

30

70

Exp M2

0 1 2 3 4 65

ISPD 2000, San DiegoApr 10, 2000 --15--

Model validation (cont.)

• Predictions for future designs– number of layers >>, die size < : f >>>– via impact severely underestimated– predicted limits on number of layers too high

Via fill rate (%)

Uti

liza

tion

fac

tor

(%)

Chong

Chen

80

70

60

50

40

30

20

10

0

M4

M3

0 10 20 30 40 50

ISPD 2000, San DiegoApr 10, 2000 --16--

Model validation (cont.)

• Predictions for future designs

Layer Chong Chen Experiment

M1 71266 30973 113452

M2 27562 0 23585

M3 0 0 9894

M4 0 0 0

Total 98828 30973 146931

Layers needed 2 2 4

Number of terminal vias

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Outline

• Models of achievable routing • Review of existing models• Validation of models through experiments!• Experimental analysis of assumptions• Future model requirements • Conclusions

ISPD 2000, San DiegoApr 10, 2000 --18--

Routing efficiency

• Constant over all layers?

Via fill rate (%)

Uti

liza

tion

fac

tor

(%)

Chong

Chen

80

70

60

50

40

30

20

10

0

M4

M3

0 10 20 30 40 50

ISPD 2000, San DiegoApr 10, 2000 --19--

Routing efficiency• Are we measuring routing efficiency or

inefficiency?– thought experiment

• given placement of given netlist• route with very good router, measure Ui

• route again with very bad router, measure Ui

– which one has better routing efficiency?– which one has higher utilization factor?– Give credit for completing nets, not for using

metal (use Steiner length instead of actual length for Ui)!

ISPD 2000, San DiegoApr 10, 2000 --20--

Layer assignment assumptions

• shorter wires on lower tiers / wires on 1 tier

Act

ual L

engt

h (%

)

Act

ual N

umbe

r of

Lay

ers

Steiner Length (m)Steiner Length (m)

ISPD 2000, San DiegoApr 10, 2000 --21--

Real Wiring Effects

• Cascade/ripple effect• Effect of vias depends on wire length• Proposal:

l+1 intersections

ISPD 2000, San DiegoApr 10, 2000 --22--

Real Wiring Effects (cont.)

• A simple proposal– probability wire is not blocked:– via impact factor: 1)1(11 l

nbi fPv

1)1( lnb fP

Via fill rate (%)

Uti

liza

tion

fac

tor

(%)

Chong

Chen

80

70

60

50

40

30

20

10

0

M4

M3

0 10 20 30 40 50

Model M3Model M4

ISPD 2000, San DiegoApr 10, 2000 --23--

Conclusion

• Better/more accurate models needed– understanding routing efficiency– layer assignment model allows >1 tier/wire– via impact based on real wiring effects

• wirelength on layer is important• cascade/ripple effect

• Experimental verification of models a must!• There is a lot of work yet to be done

ISPD 2000, San DiegoApr 10, 2000 --24--

Constant via impact factor

• Utilization factor constant?Layer Sai-Halasz Ui/Ui+1

M1/M2 0.85 0.07

M2/M3 0.85 0.56

M3/M4 0.85 1.10

M3/

M4

Uti

liza

tion

fac

tor

rati

o

Via fill rate (%)