ITRS Design ITWG 2006 1

ITRS Design + System Drivers

Hsinchu, December 2006

Design ITWG

Japan: Hiwatashi-san, Asada-sanTaiwan: Chung-Ping ChenEurope: Wolfgang Rosenstiel USA: Andrew Kahng

ITRS Design ITWG 2006 2

Key Thoughts

1. 2004-5: we created a Design Technology Roadmap– System-level, logic/ckt/physical, DFT, Verification, DFM, …

– General dependency: PIDS, Yield, Interconnect, A&P,…

2. 2005-6: we’re creating a Systems Driver roadmap– Consumer, stationary, networking, automotive, …

– Driver-specific dependency: PIDS, interconnect, A&P,…

3. Added value = design technology + design innovation– Design technology: general value add

– Design innovation: driver-specific value add• “more than Moore”

ITRS Design ITWG 2006 3

Design Chapter

ITRS Design ITWG 2006 4

Summary of Update

1. 2005: First quantitative DT roadmapWorld’s first roadmap for DT industry

2. 2006: revisions of figures, dates, and challenge items System-Level, Verification, other

More sections include table relating challenges-solutions

3. 2007: increasing alternative integration methods More than Moore

Heterogenous systems, system-in-package (SIP), etc.

ITRS Design ITWG 2006 5

System Drivers Chapter

ITRS Design ITWG 2006 6

Summary of Update

1. 2005: Added consumer mobile driverFirst new driver not based on microprocessors

2. 2006: added/updated driversConsumer stationary driver complete

Started networking driver

3. 2007: complete system driver roadmapComplete networking driver, update office (processor) driver

Add rest of drivers (medical, defense, automotive)

ITRS Design ITWG 2006 7

ITRS-iNEMI Domain Space

Chip level System level

Techrequirements

Marketrequirements

iNEMI(emulators)

ITRS(Drivers)

ITRS Design ITWG 2006 8

Technology Waves And (VC) Investment

Mainframe/ Mini

PC/Client/server

InternetTelco

Enterprise

Digital mediaEmerging

GeosConsumer

Digital BioMedical

Cleantech

70s 80s 90s 2000s 2010s

$20+B/year

Source: insight from Top VCs including Walden

$5+B/year

ITRS Design ITWG 2006 9

Market Drivers Starting To Drive Roadmap

Network ConsumerPortable

OfficeMedical Automotive Consumerstationary

Defense

MPU

PE(DSP)

AMS

Memory

Fabrics

Markets

2006 2007 2006 2006 200720072007

ITRS Design ITWG 2006 10

Market Drivers As Value Adders

FabricFabric

DriverFabric

DriverDriver

DriverDriver

PIDS Modeling

Canonical blockCanonical block

Canonical blockCanonical block

Interconnect A&P

1

10

100

1000

2006

2008

2010

2012

2014

2016

2018

2020

Year of Production

Tren

d, No

mariz

ed to

2006

# of DPEs 1/ τ : intrinsic switching speed Processing Performance

Technology scalingDesign innovation

Product v

alue

Consumer stationary driver

No

rma

lize

d p

erf

orm

ance

200

6

200

8

201

0

201

2

201

4

201

6

201

8

202

0

-- #DPEs, other-- Intrinsic switching speed-- Performance

Re

qu

ire

men

ts &

so

luti

on

s

ITRS Design ITWG 2006 11

Driver TemplateDriver parameter Example Units

Market requirements

(customers AND suppliers)

Cost,

Performance

Energy consumption / battery life

Time to market

Reliability, environmental?

$ / unit

Pages / sec

Hours

Months

Years

Critical design requirements

Power, Area,

Time per operation / clock speed

Latency / throughput / bandwidth

Design productivity

Hours of operation

Environmental constraints

Watts, mm2

ns,GHz

Gbps

PY/ mm2

Hours

<None>

Critical design parameters

Memory size / bandwidth

# processing units, redundant units

Size and clock speed/BW of each unit

Number of pins

Bytes

<None>

mm2

<None>

ITRS Design ITWG 2006 12

System (Market) Drivers Working TableDriver Market ST/LT

requirementsDesign requirements

Design parameters

Office/PC

(processor)

(General) Performance

Clock cycle

MIPS, FLOPS

#of cores

memory

Consumer (portable)

Energy

cost

W, hours of operation (energy)

# of cores, voltage, clock cycle, etc.

Consumer (stationary)

(Media/emerg) performance

Frames/sec, FLOPS # of SPUs, memory BW, etc., latency

Network (comms)

Bandwidth G/Tbits/sec # of I/Os, BW per I/O, etc.

Automotive

(industrial)

Reliability

Accuracy

Years, max/min T, radiation, sensing accuracy

% redundancy

Medical Heterogeneous Integration?

Analog, digital, chemical, bio, sensors, etc.

#of (bio, chem) sensors on-chip,

Defense Reliability (extreme)

Years, max/min T, radiation,

Redundancy

ITRS Design ITWG 2006 13

Market Drivers Table

Process For Each System Driver

Identify market

requirements

Identify key design

parameters

Select DRIVERrequirements

Create model Generate data

Color data

1

2 3

Select Critical/difficult parameters

PowerAreaHrs. operation

#proc unitsSize per unitMemoryPins

Power

Identify design

requirements

Cost Perf.

Synch with iNEMI market emulatorsIndustry data

ITRS Design ITWG 2006 14

System Drivers ITRS-iNEMI Engagement Model

Driver ITRS iNEMI

Office / large business

US TWG

(A. Kahng, UCSD)

Tom Pearson, Intel

Erich Klink, IBM

Portable /

Consumer

Japan TWG

(Hiwatashi-san, Toshiba)

Susan Noe,

3M

Networking / Communications

US TWG

(Joe Abler, IBM)

Tom Pearson, Intel

Erich Klink, IBM

Automotive EU TWG Jim Spall,

Delphi

Aerospace/ Defense

TBD 2007 William Murphy,

Lockheed Martin

Medical Products

TBD 2007 Terry Dishongh,

Intel

ITRS Design ITWG 2006 15

Generic features of “SOC Consumer Stationary”Contrast with “SOC Consumer Portable”SOC Consumer Stationary SOC Consumer Portable

( SOC Power Efficient)

Core SOC of Consumer Electronics

Applications

Core SOC of Personal Mobile

Electronics ApplicationsMany Data Processing Engines (DPE) with

high processing performance to cope with

high level functions implemented by SW

Many Processing Engines (PE) dedicated for

each function to achieve low power

IO- M

em

ory IF

& C

hip

-to-C

hip

IF -

Main

P

rocesso

r

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

Main

P

rocesso

r

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

D

PE

Function A Function B Function C

Function D Function E

MainMemory

PE

PE

PE

PE

PE

MainProcessor

PE

PE

PE

PE

PE

PE

PE

PE

PE Peripherals

ITRS Design ITWG 2006 16

Design Trend: # of Processors & Processing Performance

5 8 8 13 16 24 2939 47

6177

99120

149

189

248

73

2.0

10.1

0.8

0.256

0

50

100

150

200

250

3002005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

Year of Production

# of Components

0.1

1

10

100

Max Processing Power

[TFLOPS]

# of Main CPUs # of DPEs Max Processing Performance

Max

Pro

cess

ing

Per

form

ance

[T

FL

OP

S]

ITRS Design ITWG 2006 17

Design Trend: Power Consumption – SOC Total

0

100

200

300

400

500

6002005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

Power Consumption [W]

Switching Power, Logic Switching Power, Memory Leakage Power, Logic Leakage Power, Memory

600W

★

SOC total power consumption rapidly increases

ITRS Design ITWG 2006 18

Channel

High-bandwidth host chip High-bandwidth switch chip

Tra

nsm

itte

r co

re

Rec

eive

r co

re

A Networking Driver

ITRS Design ITWG 2006 19

Chip Structure

Very high bandwidth– Key driver

Large size Many high-speed I/Os

– Mixed signal

– Consume lots of power

Key components– I/O

– Switch fabric

– Possible control processor and memory

– CMOS technology

Switch Fabric

Peripherals

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O I/O I/O

I/O I/O I/O

Processor Memory

I/O I/O I/O Memory I/O?

ITRS Design ITWG 2006 20

Evolution of Key Parameters Bandwidth driver

– Combination of technology scaling and bandwidth standards

– Assume I/Os dominate driver

0

1000

2000

3000

4000

5000

6000

7000

8000

2006 2008 2010 2012 2014 2016 2018 2020

Gb

ps

0

10

20

30

40

50

60

70

80

90

Gb

ps

Chip bandwidth

Per-pin bandwidth

ITRS Design ITWG 2006 21

Summary

1. 2005: We created a Design Technology Roadmap– System-level, logic/ckt/phy, DFT, Verification, DFM,

– General dependencies: PIDS, yield, interconnect, A&P,…

2. 2006: We started creating a System Drivers Roadmap– Consumer stationary, networking, automotive

– Driver-specific dependencies: PIDS, interconnect, A&P,…

3. Added value = design technology + design innovation– Design technology: general value add

– Design innovation: driver-specific value add• Increased importance of “More than Moore”