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ECE 255
MOS Current Mirrors and Basic Gain Cell
(Sedra and Smith, 7th Ed., Secs. 8.1-8.3)
Mark Lundstrom School of ECE
Purdue University West Lafayette, IN USA
Lundstrom: Fall 2019
ECE 255: Fall 2019 Purdue University
IC Amplifiers
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For the rest of the course, we will shift our focus to integrated circuit electronics.
Lundstrom: Fall 2019
First question: How do we bias a MOSFET when it’s on an a Si chip?
ID = 100 µA
Classic 4-resistor bias circuit
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VDD
RD RG1
RG2 RS
Not suitable because large resistors are
required.
Why avoid large resistors?
4 http://www.computerhistory.org/revolution/digital-logic/12/281
µA 709 op amp Designed by Robert Widlar
2 transistors 2 resistors
Principles of IC Design
5 Lundstrom: Fall 2019
1) Avoid large value resistors
2) Avoid large value capacitors
3) Use low voltage power supplies
4) Exploit the ability to “size” transistors (W/L for MOSFETs, AE for bipolar)
5) Use CMOS unless bipolar is essential
Outline
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1) Introduction
2) MOS Current Mirrors
3) CS Amplifiers with Active Loads
Lundstrom: Fall 2019
Review: MOSFET DC Design
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VDD = +5 V
R1 = ?kΩ
ID =
kn
2VGS −Vtn( )2
= WL
′kn
2VGS −Vtn( )2
ID = 0.1 VGS −1( )2mA
Design for: ID = 0.5 mA
What region is this MOSFET operating in?
VD
Is VDS ≥ VGS −Vtn( )
VD ≥ VD −1( ) ✓
saturation region
Review: MOSFET DC Design
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VDD = +5 V
R1 = ?kΩ
ID = 0.1 VGS −1( )2
ID = 0.1 VGS −1( )2= 0.5
Design for: ID = 0.5 mA
VGS = 3.24 V
R1 =
5− 3.240.5
= 3.53 kΩ
Lundstrom: Fall 2019
VD =VGS = 3.24 V
VD =VGS
Review: MOSFET DC Analysis
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VDD = +5 V
R1 = 3.53kΩ
ID = 0.1 VGS −1( )2
ID = 0.1 VGS −1( )2
ID = ? mA
VGS =VDD − ID R1
2 equations in 2 unknowns
Solve quadratic eqn.
Lundstrom: Fall 2019
MOSFET “current mirror”
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IG = 0
Q1
VDD = +5 V
R1 = 3.53kΩ
ID = 0.1 VGS −1( )2
ID1 = 0.5 mA
+VGS = 3.24 V−
Q2
VD2
ID2 = ?
ID = 0.1 VGS −1( )2
ID2 = ID1 if
VD2 > VGS –Vtn
VD2 > 2.24 V
VD = 3.24 V
MOSFET current source
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IO = 0.5 mA
VO >VGS −Vtn
Lundstrom: Fall 2019
VO I
VO =VDS2
IO = 0.5 mA
2.24 V
“sizing” transistors
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VDD
R1
ID1 =
WL
⎛⎝⎜
⎞⎠⎟ 1
′kn
2VGS −Vtn( )2
IG = 0
Q1 Q2
IREF
+VGS
−
ID2 =
WL
⎛⎝⎜
⎞⎠⎟ 2
′kn
2VGS −Vtn( )2
ID2
IREF
=W L( )2
W L( )1
VD2
VD2 >VGS −Vtn( ) ID2
Now, let’s look more
closely at the effect of VD2.
MOSFETs
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VDS
IC
act
VGS
“saturation”
VDS > VGS −Vtn( )
VGS −Vtn
“triode”
VDSsat
Q1 VDS1 =VGS
ID =
′kn
2WL
⎛⎝⎜
⎞⎠⎟
VGS −Vtn( )2
VD2
MOSFETs with output conductance
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VDS
IC
act
VGS
VDS > VGS −Vtn( )
VGS −Vtn
VDSsat
ID =
′kn
2WL
⎛⎝⎜
⎞⎠⎟
VGS −Vtn( )21+VDS VA( )
Q1 VDS1 =VGS Q2 VDS2 ≠VDS1
Real MOSFET current mirror
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VDD
R1
IG = 0
Q1 Q2
IREF
+VGS
−
VD
ID1 =
′kn
2WL
⎛⎝⎜
⎞⎠⎟ 1
VGS −Vtn( )21+VDS1 VA( )
ID2 =
′kn
2WL
⎛⎝⎜
⎞⎠⎟ 2
VGS −Vtn( )21+VD2 VA( )
ID2
IREF
=W L( )2
W L( )11+VD2 VA( )1+VGS VA( )
ID2
VDS1 =VGS
IREF =
′kn
2WL
⎛⎝⎜
⎞⎠⎟ 1
VGS −Vtn( )21+VGS VA( )
Real MOSFET current mirror
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VDD
R1
IG = 0
Q1 Q2
IREF
+VGS
−
VD
ID2
IREF
=W L( )2
W L( )11+VD2 VA( )1+VGS VA( )
ID2
ID2
IREF
=W L( )2
W L( )11+
VD2 −VGS( )VA
⎛
⎝⎜
⎞
⎠⎟
Real MOSFET current source
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VDD
R1
Q1 Q2
IREF
IO
Lundstrom: Fall 2019 See Sec. 8.6
RO = ro
VO >VGS −Vtn
IREF
RO =
VA
IO
IO
NMOS vs. PMOS
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VDD
R1
ID =
′kn
2WL
VGS −Vtn( )2
IREF
VDD
R1 IREF
ID =
′kp
2WL
VSG − Vtp( )2
Lundstrom: Fall 2019
+VGS
−
+VSG
−
PMOS Current Mirror
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VDD
R1
Q1 Q2
IREF
IO
IO
VO <VSG − Vtp
VDD
VO
+VSG
−
Outline
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1) Introduction
2) MOS Current Mirror
3) CS Amplifiers with Active Loads
Lundstrom: Fall 2019
Common Source amplifier
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+
υi
−
+
υ0
−
D S
VDD
RD
G
Aυo= υo
υi
= −gmRD
Rin = ∞
Ro = RD
MOSFETs have modest gm, so we need a very large drain resistor.
Lundstrom: Fall 2019
Basic IC gain cell
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+
υi
−
+
υ0
−
D S
VDD
G
Aυo= υo
υi
= ?
Rin = ?
Rout = ?
IO
Ideal current source
RO = ∞
Draw s.s. circuit
Lundstrom: Fall 2019 *
Basic IC gain cell: Results
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+
υi
−
+
υ0
−
D S
VDD
G
Aυo= υo
υi
= −gmro
Rin = ∞
Ro = ro
IO
Ideal current source
RO = ∞
Lundstrom: Fall 2019
Maximum gain (“intrinsic gain” / “self gain”)
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+
υi
−
+
υ0
−
D S
VDD
G
Aυo= −gmro
IO
Ideal current source
RO = ∞
ro =VAID
= 1λID
A0 = Aυo= gmro
VA = ′VAL ∝ LLundstrom: Fall 2019
gm = IDVGS −Vtn( ) 2(1)
gm = 2knID(2)
*
Maximum (intrinsic/self) gain
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+
υi
−
+
υ0
−
D S
VDD
G
IO
Ideal current source
RO = ∞
A0 =VA
VGS −Vtn( ) 2 =′VAL
VGS −Vtn( ) 2
A0 =VA2knID
= ′VAL2knID
Low currents and long channels give high gain
But, they give low transconductance and bandwidth
10 < A0 < 40Lundstrom: Fall 2019
Non-ideal current source
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+
υi
−
+
υ0
−
D S
VDD
G
IO
Real current source
RO
Aυo= −gm ro || RO( )
Lundstrom: Fall 2019
How do we implement the current source?
Implementation
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+
υi
−
+
υ0
−
Q1
VDD
R1 IREF
Q2 Q3 Aυo
= −gm roN || roP( )
roN ≈ roP = ro
Aυo= −gmro = − A0
2
Half of the self-gain
Example 8.4 (p. 453 in Sedra and Smith)
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+
υi
−
+
υ0
−
VDD
Q1 R1
Q2
IREF
Q3
IREF = 0.1mA
kn = 2 mA V2
kp = 0.65 mA V2
Vtn = Vtp = 0.6 V
VAn = 20 V
VAp = 10 V
*
Voltage gain
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+
υi
−
+
υ0
−
VDD
Q1 R1
Q2
IREF
Q3
Aυo= −gm1 roN || roP( )
gm1 = 2knID= 2 × 2 × 0.1 = 0.63mS
ron =VANID
= 200.1
= 200 kΩ
rop =VAPID
= 100.1
= 100 kΩ
Aυo= −0.63 200 ||100( ) = −42
Min and Maximum output voltages
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+
υi
−
+
υ0
−
VDD
Q1 R1
Q2
IREF
Q3
VDS1 >VGS1 −Vtn
υo >VGS1 −Vtn
VSD2 >VSG2 − Vtp
VDD −υo( ) >VSG2 − Vtp
υo <VSS −VSG2 + Vtp
Min and Maximum output voltages
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+
υi
−
+
υ0
−
VDD
Q1 R1
Q2
IREF
Q3
There is a minimum output voltage to keep Q1 in saturation.
There is a maximum output voltage to keep Q2 in saturation.
Basic gain cell
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+
υi
−
+
υ0
−
VDD
Q1 R1
Q2
IREF
Q3
Aυo= −gm roN || roP( )
Question: How can we increase the gain of the basic cell? Answer: Cascode
Summary
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Current mirrors are used extensively in analog IC design.
The basic common source amplifier suffers from low gain when implemented in Si. A solution must be found.
Lundstrom: Fall 2019
Current Mirrors and Basic Gain Cell
Lundstrom: Fall 2019 34
1) Introduction
2) MOS Current Mirror
3) CS Amplifiers with Active Loads
