ECE 342 – Jose Schutt-Aine ECE 342 Electronic Circuits 2. MOS Transistors Jose E. Schutt-Aine...

ECE 342 – Jose Schutt-Aine

ECE 342Electronic Circuits

2. MOS Transistors

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]

1

ECE 342 – Jose Schutt-Aine 2

Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

NMOS Transistor


• NMOS Transistor– N-Channel MOSFET– Built on p-type substrate– MOS devices are smaller than BJTs– MOS devices consume less power than BJTs

NMOS Transistor

3


NMOS Transistor - Layout

Top View

Cross Section

4


GS TV V

GS TV V

GS TV V

Resistive

Nonlinear

Saturation

MOS Regions of Operation

< ( )DS GS TV V V

DS GS TV V V

DSV small

Triode

Active

5


• As VG increases from zero– Holes in the p substrate are repelled from the gate area

leaving negative ions behind– A depletion region is created– No current flows since no carriers are available

MOS Transistor Operation

• As VG increases– The width of the depletion region and the potential at the

oxide-silicon interface also increase– When the interface potential reaches a sufficiently

positive value, electrons flow in the “channel”. The transistor is turned on

• As VG rises further– The charge in the depletion region remains relatively

constant– The channel current continues to increase

6


D ox GS T DS

WI C V V V

L

DS GS TV V V

Cox: gate oxide capacitancem: electron mobilityL: channel lengthW: channel widthVT: threshold voltage

MOS – Triode Region - 1

3.9 ox o

oxox ox

Ct t

7


FET is like a linear resistor with 1

ds

n ox GS T

rW

C V VL

MOS – Triode Region

8


21

2

D n ox GS T DS DS

WI C V V V V

L DS GS TV V V

GS TV V

– Charge distribution is nonuniform across channel– Less charge induced in proximity of drain

MOS – Triode Region - 2

9


MOS – Active Region

Saturation occurs at pinch off when DS GS T DSPV V V V

2

2 D n ox GS T

WI C V V

L DS GS TV V V

GS TV V

(saturation)

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NMOS – Drain Current


NMOS – Circuit Symbols


characteristics for a device with k’n (W/L) = 1.0 mA/V2.

NMOS – IV Characteristics


• Characteristics of the threshold voltage – Depends on equilibrium potential– Controlled by inversion in channel– Adjusted by implantation of dopants into the channel– Can be positive or negative– Influenced by the body effect

MOS Threshold Voltage

The value of VG for which the channel is “inverted” is called the threshold voltage VT (or Vt ).

14


nMOS Device Types

• Enhancement Mode – Normally off & requires positive potential on gate– Good at passing low voltages– Cannot pass full VDD (pinch off)

• Depletion Mode– Normally on (negative threshold voltage)– Channel is implanted with positive ions (VT )– Provides inverter with full output swings

15


Types of MOSFETS


MOS – Active Region

• Saturation– Channel is pinched off– Increase in VDS has little effect on iD– Square-law behavior wrt (VGS-VT)– Acts like a current source

17


GD TV Vfor saturation region. Since VGD is zero, then the device is always in the saturation region.

Diode-Connected Transistor

When the drain and gate of a MOSFET are connected together the result is a two-terminal device known as a diode-connected transistor


2'1

2D n GS t

Wi i k V V

L

2't

Wi k V V

L

1

'

1 1

2 ' t n ov

ir

W WV k V V k VL L

t ovV V V

Diode-Connected Transistor

' '1If we replace by and use

2GS nV V k k

incrementalresistance


An MOS process technology has Lmin= 0.4 mm, tox= 8 nm, m = 450 cm2/V.s, VT = 0.7V

(a)Find Cox and kn’= mnCox

(b) W/L = 8 mm/0.8mm. Calculate VGS, VDSmin for operation in saturation with ID= 100 mA

(c)Find VGS for the device in (b) to operate as a 1 kW resistor for small vDS

Example

20


113 2 2

9

3.45 104.32 10 / 4.32 /

8 10

ox

oxox

C F m fF mt

' 2 2 2450 / . 4.32 / 194 / n n oxk C cm V s fF m A V

For operation in saturation region

2'1

2 D n GS T

Wi k V V

L

21 8100 194 0.7 0.7 0.32 1.02

2 0.8 GS GS GSV V V V V

min 0.32 DS GS TV V V V

Example - Solution

24.32 /oxC fF m

min 0.32DSV V

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'

1

DS

DSDS

D small vn GS T

vr

Wi k V VL

Triode region with vDS very small

6

1100

194 10 10 0.7 GSV

0.7 0.52 GSV V

1.22GSV V

Example – (con’t)

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• The body effect– VT varies with bias between source and body– Leads to modulation of VT

Potential on substrate affects threshold voltage

1/ 2 1/ 2( ) 2 2

T SB To F SB FV V V V

ln

aF

i

NkT

q n

1/ 22

a s

ox

qN

C

Fermi potential of material

Body bias coefficient

Body Effect

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With depletion layer widening, the channel length is in effect reduced from L to L-DL Channel-length modulation

This leads to the following I-V relationship

2'11

2D n GS T DS

Wi k v V v

L

Where l is a process technology parameter

Channel-Length Modulation

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Channel-Length Modulation

Channel-length modulation causes iD to increase with vDS in saturation region

25


VGS(V) VDS(V) ID(mA) 2 1 80 2 8 91

Problem

( ) GS T DS GS Ta V V V V V Pinchoff

( ) 1GS T DS GS Tb V V V V V V Active region

A MOSFET has VT = 1 V with measured data:

Find l

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2'11

2D n GS T DS

WI k V V V

L

2'1 1 1

11

2D n GS T DS

WI k V V V

L

2'2 2 2

11

2D n GS T DS

WI k V V V

L

Find iD at pinchoff VDSP = VGS-VT =1V

Problem (cont’)


1

2

1 911.1375

1 80DS

DS

VR

V

2 11 DS DSV R R V

2 1( ) 1DS DSV RV R

1

2 1

1 1.1375 10.0196

8 1DS DS

RV

V RV

Problem (cont’)


0

100

200

300

400

500

600

700

0 0.5 1 1.5 2 2.5

NMOS

VGS=1.0VGS=1.5VGS=2.0VGS=2.5

IDS

Vds

NMOS IV Curves

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NMOS IV Curves


The MOSFET in the circuit shown has Vt = 1V, kn’= 100mA/V2 and l = 0. Find the required values of W/L and of R so that when vI=VDD=+5 V, rDS=50 W and vo= 50 mV.

5 , 0.05I GS o DSv V V v V V

0.0550 0.001 1

50DS

DS DD

Vr I A mA

I

5 0.054.95

1DD o

D

V vR k

I

MOSFET Circuit at DC – Problem 1


triode regionDS GS tV V V

2

'

2DS

D n GS t DS

VWI k V V V

L

2

3 0.051 100 10 5 1 0.05

2

W

L

50W

L

MOSFET Circuit at DC – Problem 1 (cont’)


The NMOS transistors in the circuit shown have Vt = 1V, mnCox = 120mA/V2, l = 0 and L1=L2=1mm. Find the required values of gate width for each of Q1 and Q2 and the value of R, to obtain the voltage and current values indicated.

1 1.5GSV V

2

2

1120 1.5 1 2

2 1

WA W m

5 3.512.5

0.120R k

2'1Using

2D n GS t

WI k V V

L

MOSFET Circuit at DC – Problem 2


0GTV 0, smallGT DSV V

0, largeGT DSV V

Gate Capacitance

• Capacitance– Depends on bias– Fringing fields are present– Account for overlap C

34


Capacitance

• Gate Capacitance– CG determines the amount of charge to switch gate– Several distributed components– Large discontinuity as device turns on– At saturation capacitance is entirely between gate

and source2

2 11

3 2gs gso ox

XC C WLC

X

22 1

13 2gd gdo oxC C WLC

X

DS

GS T

VX

V VDefine

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MOS Capacitances

• Expect capacitance between every two of the four terminals.

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MOS Parasitics

- Capacitance from gate to other 3 terminals- Diodes to body- Series resistance- Wiring parasitics

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PMOS Transistor

-700

-600

-500

-400

-300

-200

-100

0

-2.5 -2 -1.5 -1 -0.5 0

PMOS

VGS=-1.0VGS=-1.5VGS=-2.0VGS=-2.5

VG

S=

-1.0

Vds

- All polarities are reversed from nMOS- vGS, vDS and Vt are negative- Current iD enters source and leaves through drain - Hole mobility is lower low transconductance- nMOS favored over pMOS

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The PMOS transistor in the circuit shown has Vt = -0.7 V, mpCox = 60mA/V2, l = 0 and L=0.8mm. Find the values required for W and R, in order to establish a drain current of 115 mA and a voltage VD of 3.5 V.

PMOS Circuit

3.53.04

0.115R k

2310.115 60 10 1.5 ( 0.7)

2 0.8

WmA

4.8W m

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ECE 342 – Jose Schutt-Aine ECE 342 Electronic Circuits 2. MOS Transistors Jose E. Schutt-Aine...

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