RF input IQ LO generator MUX OSCin IF I Output Synthesizer LO output IF Q Output External LO input SPI Interface SYNC Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMX8410L SNAS730A – MARCH 2018 – REVISED NOVEMBER 2018 LMX8410L High-Performance Mixer With Integrated Synthesizer 1 1 Features 1• Wideband RF Input: 4 to 10 GHz • Large IF Bandwidth: DC to 1350 MHz • Input IP3: 28 dBm at 5-GHz RF Input • Noise Figure: 15 dB at 5-GHz RF Input • High Voltage Conversion Gain: 11 dB at 5-GHz RF Input • Integrated Wideband RF Input Balun • Automatic Offline DC Offset Correction to ±2 mV • Programmable IMRR Calibration • SYNC Feature for Multiple Devices • High-Performance Integrated LO Synthesizer: 56.5-dBc DSB Integrated Noise at 5-GHz carrier • External LO mode: Integrated LO Synthesizer can be Bypassed; Support External LO Injection • Integrated Low-Noise LDOs • 7-mm × 7-mm 48-pin QFN Package 2 Applications • Test and Measurement Equipment • Wireless Infrastructure • Phased Array Radar • Microwave Backhaul • Satellite Communications • Software-Defined Radio 3 Description The LMX8410L is a high-performance wideband (RF frequency input from 4 to 10 GHz) I/Q demodulator with an integrated LO and IF amplifier. With IIP3 of 28 dBm and NF of 15 dB (both at 5GHz), it provides excellent dynamic range for high performance applications. The device offers large complex bandwidth of 2.7 GHz for high data-rate applications. The LMX8410L offers an automatic DC offset correction algorithm that reduces the offset to less than ±2 mV. Fine control of gain and phase of I and Q channels is enabled using SPI interface to achieve high image rejection. The LMX8410L has a high level of integration providing high performance while saving board space and complexity. It integrates a wideband RF input balun, eliminating the need for external baluns. It integrates a high-performance PLL and VCO, eliminating the need for external LO and LO driver. The device also integrates an IF amplifier and several low noise LDOs, further simplifying the board. The LMX8410L integrates a very low-noise synthesizer, with a PLL FOM of –236 dBc/Hz, providing up to 56.5-dBc DSB integrated noise at 5 GHz carrier. The LO allows for phase synchronization across multiple devices. The high- performance synthesizer output can be brought out to drive another stage or a data converter. The integrated LO can be bypassed for applications that share a common external LO. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) LMX8410L VQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram
Transcript
RF inputIQ LO
generatorMUX
OSCin
IF I Output
Synthesizer
LO output
IF Q Output
External LO input
SPIInterface
SYNC
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX8410LSNAS730A –MARCH 2018–REVISED NOVEMBER 2018
LMX8410L High-Performance Mixer With Integrated Synthesizer
1
1 Features1• Wideband RF Input: 4 to 10 GHz• Large IF Bandwidth: DC to 1350 MHz• Input IP3: 28 dBm at 5-GHz RF Input• Noise Figure: 15 dB at 5-GHz RF Input• High Voltage Conversion Gain: 11 dB at 5-GHz
RF Input• Integrated Wideband RF Input Balun• Automatic Offline DC Offset Correction to ±2 mV• Programmable IMRR Calibration• SYNC Feature for Multiple Devices• High-Performance Integrated LO Synthesizer:
56.5-dBc DSB Integrated Noise at 5-GHz carrier• External LO mode: Integrated LO Synthesizer can
be Bypassed; Support External LO Injection• Integrated Low-Noise LDOs• 7-mm × 7-mm 48-pin QFN Package
2 Applications• Test and Measurement Equipment• Wireless Infrastructure• Phased Array Radar• Microwave Backhaul• Satellite Communications• Software-Defined Radio
3 DescriptionThe LMX8410L is a high-performance wideband (RFfrequency input from 4 to 10 GHz) I/Q demodulatorwith an integrated LO and IF amplifier. With IIP3 of28 dBm and NF of 15 dB (both at 5GHz), it providesexcellent dynamic range for high performanceapplications. The device offers large complexbandwidth of 2.7 GHz for high data-rate applications.
The LMX8410L offers an automatic DC offsetcorrection algorithm that reduces the offset to lessthan ±2 mV. Fine control of gain and phase of I andQ channels is enabled using SPI interface to achievehigh image rejection.
The LMX8410L has a high level of integrationproviding high performance while saving board spaceand complexity. It integrates a wideband RF inputbalun, eliminating the need for external baluns. Itintegrates a high-performance PLL and VCO,eliminating the need for external LO and LO driver.The device also integrates an IF amplifier and severallow noise LDOs, further simplifying the board.
The LMX8410L integrates a very low-noisesynthesizer, with a PLL FOM of –236 dBc/Hz,providing up to 56.5-dBc DSB integrated noise at5 GHz carrier. The LO allows for phasesynchronization across multiple devices. The high-performance synthesizer output can be brought out todrive another stage or a data converter. Theintegrated LO can be bypassed for applications thatshare a common external LO.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)LMX8410L VQFN (48) 7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
11 Device and Documentation Support ................. 6111.1 Documentation Support ........................................ 6111.2 Receiving Notification of Documentation Updates 6111.3 Community Resources.......................................... 6111.4 Trademarks ........................................................... 6111.5 Electrostatic Discharge Caution............................ 6111.6 Glossary ................................................................ 61
12 Mechanical, Packaging, and OrderableInformation ........................................................... 61
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2018) to Revision A Page
• First release of production-data data sheet ........................................................................................................................... 1• Changed many numbers in electrical specifications table. .................................................................................................... 6• Added typical performance characteristics section. ............................................................................................................ 14• Changed and added significant details in detailed descriptions sections. Added sections, changed several portions
of the register map................................................................................................................................................................ 22
I/O DESCRIPTIONNAME NAME1 CE Input Chip Enable input. Active HIGH powers on the device. 1.8V to 3.3V logic.
2 VBIAS_VCO2 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If usingexternal LO, this pin should either be floated or configured the same way as internal LO mode.
3 VBIAS_VCO1 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If usingexternal LO, this pin should either be floated or configured the same way as internal LO mode.
4 GND Ground VCO ground. VBIAS pin capacitors must bypass to this point.5 SYNC Input Trigger pin for synchronizing multiple devices. If using external LO, tie this pin to GND.6 GND Ground Digital ground. VCC_DIG bypass capacitors must bypass to this point.7 VCC_DIG Supply Digital supply. TI recommends connecting 0.1-µF capacitor to digital ground.
8 OSCINP Input Reference input clock (+). High input impedance. Requires connecting series capacitor (0.1 µFrecommended). If using external LO, tie this pin to GND.
9 OSCINM Input Reference input clock (–). High input impedance. Requires connecting series capacitor (0.1 µFrecommended). If using external LO, tie this pin to GND.
10 VREG_OSCIN BypassInternal LDO output. Requires connecting 1-µF capacitor to digital ground. Place close to pin. Ifusing external LO, this pin should either be floated or configured the same way as internal LOmode.
I/O DESCRIPTIONNAME NAME11 MUXOUT Output Readback or lock detect output. Pin mode configured by internal register settings.
12 VCC_CP Supply Charge pump supply. TI recommends connecting 0.1 µF and 100 pF to charge pump ground.Place close to pin. This pin must be connected to VCC, even if using external LO.
13 CP Output Charge pump output. TI recommends connecting C1 of loop filter close to pin. If using externalLO, this pin should either be floated or configured the same way as internal LO mode.
14 GND Ground Charge pump ground. VCC_CP bypass capacitors must bypass to this point.15 GND Ground MASH engine ground. VCC_MASH bypass capacitors must bypass to this point.
16 VCC_MASH Supply MASH engine supply. TI recommends connecting 0.1 µF and 100 pF to MASH engine ground.Place close to pin. This pin must be connected to VCC, even if using external LO.
17 LO_M Input/Output
Internal LO differential output (–) or external LO differential input (–). In differential output mode,requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. In differential inputmode, remove the pull up resistors or inductors. The input should be capacitively coupled withinternal biasing. See LO Interface for more information.
18 LO_P Input/Output
Internal LO differential output (+) or external LO differential input (+). In differential output mode,requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. In differential inputmode, remove the pull up resistors or inductors. The input should be capacitively coupled withinternal biasing. See LO Interface for more information.
19 VCC_BUF Supply LO buffer supply. TI recommends connecting 0.1 µF and 100 pF to VCO ground. This pin mustbe connected to VCC, even if using external LO.
20 GND Ground IF amplifier Q-channel ground. Q-channel VCC5 bypass capacitors must bypass to this point.
21 IF_QM Output IF amplifier Q-channel differential output (–). TI recommends connecting series 50-Ω resistorclose to pin.
22 IF_QP Output IF amplifier Q-channel differential output (+). TI recommends connecting series 50-Ω resistorclose to pin.
23 VCC5_IFQ Supply IF amplifier Q-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifierQ-channel ground. Place close to pin.
24 SCK Input SPI clock signal. High impedance CMOS input. 1.8-V to 3.3-V logic.25 SDI Input SPI data signal. High impedance CMOS input. 1.8-V to 3.3-V logic.26 CSB Input SPI chip select signal. High impedance CMOS input. 1.8-V to 3.3-V logic.27 VCC_IFQ Supply IF mixer Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.28 NC N/A No connect. Pin is not internally connected and may be floated or shorted to other nodes.29 VCC_RFQ Supply RF Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.32 GND Ground RF input path ground.31 RF Input RF input. Single-ended. Must be AC coupled.32 GND Ground RF input path ground.33 VCC_RFI Supply RF I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.34 GND Ground Should be connected IF ground.35 VCC_IFI Supply IF mixer I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
36 VCM_IN Input Common-mode voltage input. When the VCM_CONFIG register is set to external (0xF), thevoltage on this pin sets the common-mode voltage of the IF amplifiers.
37 NC Ground Connect this pin to IF ground.
38 VCC5_IFI Supply IF amplifier I-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier I-channel ground. Place close to pin.
39 IF_IP Output IF amplifier I-channel differential output (+). TI recommends connecting series 50-Ω resistor closeto pin.
40 IF_IM Output IF amplifier I-channel differential output (–). TI recommends connecting series 50-Ω resistor closeto pin.
41 GND Ground IF amplifier I-channel ground. I-channel VCC5 bypass capacitors should bypass to this point.
42 VBIAS_VARAC Bypass VCO varactor bias. Requires connecting 10µF capacitor to VCO ground. If using external LO, thispin should either be floated or configured the same way as internal LO mode.
43 GND Ground VCO ground. Varactor bias bypass capacitor should bypass to this point.
44 VTUNE Input VCO tuning voltage input. If using internal LO, connect the output of the loop filter to this point. Ifusing external LO, tie this pin to GND.
45 VREG_VCO Bypass VCO LDO output node. Requires connecting 10-µF capacitor to VCO ground. Place close to pin.This capacitor must be present even if used in external LO mode.
46 VCC_VCO Supply VCO supply. TI recommends connecting 0.1-µF and 100-pF capacitors to VCO ground. This pinmust be connected to VCC, even if using external LO.
47 VREF_VCO Bypass VCO LDO reference node. Requires connecting 1-µF capacitor to VCO ground. If using externalLO, this pin should either be floated or configured the same way as internal LO mode.
48 GND Ground VCO ground. VCO LDO, LDO reference, and supply bypass capacitors must bypass to this point.
49 PAD Ground Die attach pad. Internally connected to ground. TI recommends shorting ground pins to this padon the same plane, if possible.
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVCC Power supply voltage, 3.3-V rail –0.3 3.6 VVCC5 Power supply voltage, 5-V rail –0.3 5.3 VPD Power dissipation 5 WTJ Junction temperature –40 150 °CTstg Storage temperature –65 150 °C
6.2 ESD RatingsVALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), perANSI/ESDA/JEDEC JS-001, all pins 2500
VCharged device model (CDM), per JEDECspecificationJESD22-C101, all pins 500
6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNITVCC Power supply voltage, 3.3V rail 3.15 3.3 3.45 VVCC5 Power supply voltage, 5V rail 4.75 5 5.25 VTA Ambient temperature –40 25 85 °CTJ Junction temperature 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.
(2) Thermal model based on JEDEC standard coupon, 50.8 mm × 50.8 mm × 1.6 mm, six-layer Cu, 0.5 oz top layer, 2 oz else. 6 × 6thermal vias in DAP, 0.2 mm diameter.
(1) For measurements that require RF input, RF input power is -10dBm unless otherwise specified.(2) For two-tone measurements, tone separation is 17MHz.
6.5 Electrical CharacteristicsMeasurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER SUPPLYVCC Power supply voltage, 3.3-V rail 3.15 3.3 3.45 V
ICC Power supply current, 3.3-V railInternal LO 650
mAExternal LO 330
VCC5 Power supply voltage, 5-V rail 4.75 5 5.25 V
ICC5Power supply current both channels Iand Q, 5-V rail 130 mA
FREQUENCY RANGESFRF RF port frequency range 4000 10000 MHzFLO LO port frequency range 4000 10000 MHz
FIFIF port frequency range (3dBbandwidth) DC 1350 MHz
Electrical Characteristics (continued)Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
Electrical Characteristics (continued)Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(3) Output power, spurs, and harmonics can vary based on board layout and components.(4) For lower VCO frequencies, the N divider minimum value can limit the phase detector frequency.
PERFORMANCE TUNINGGIQ_CAL I/Q gain calibration range IMRR_GCAL register full range ±0.5 dBGIQ_STEP I/Q gain calibration step size 0.05 dBPHIQ_CAL I/Q phase calibration range IMRR_PCAL register full range ±20 Deg
PHIQ_STEP I/Q phase calibration step sizeStep size can be made reducedto 0.25 deg in fine accuracymode
0.45 Deg
VDCOC calibrated differential DC offset +/- 2 mVPORTS
Electrical Characteristics (continued)Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flatcomponents. PLLFLAT = PLLFOM + 20log(FVCO / FPD) + 10log(FPD / 1Hz). PLLFLICKER (offset) = PLLFLICKER_NORM + 20log(FVCO / 1GHz) -10log(offset frequency / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLLNOISE =10log(10PLLFLAT / 10 + 10PLLFLICKER / 10).
LO SYNTHESIZER PHASE DETECTOR AND CHARGE PUMP
FPD Phase detector frequency
Integer Mode (FRAC_ORDER =0) 0.125 400
MHzFractional Mode (FRAC_ORDER= 1,2,3) 5 300
Fractional Mode (FRAC_ORDER= 4) 5 240
ICPOUT
Charge pump leakage current CPG = 0 15 nA
Effective charge pump current (sum ofup and down currents)
Electrical Characteristics (continued)Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(6) See Application and Implementation for more details on the different VCO calibration modes.
Electrical Characteristics (continued)Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwisenoted. Measurements are done with external VCM = 1.7V.
Category 1 or 2 0 1400DIGITAL INTERFACE (SCK, SDI, CSB, MUXOUT, SYNC, CE)VIH High level input voltage 1.4 VCC VVIL Low level input voltage 0 0.4 VIIH High level input current -50 50 µAIIL Low level input current -50 50 µA
VOH High level output voltage IL = –5 mA VCC –0.55 V
VOL High level output current IL = 5 mA 0.55 V
(1) See Figure 1(2) See Figure 2
6.6 Timing RequirementsMIN NOM MAX UNIT
SYNCtSETUP Setup time for pin relative to OSCIN rising edge 2.5 nstHOLD Hold time for pin relative to OSCIN rising edge 2 nsDIGITAL WRITE INTERFACE (1)
FSPI_WRITE SPI write speed 50 MHztES Clock to enable low time 5 nstCS Data to clock setup time 2 nstCH Data to clock hold time 2 nstCWH Clock pulse width high 5 nstCWL Clock pulse width low 10 nstCES Enable to clock setup time 10 nstEWH Enable pulse width high 10 nsDIGITAL READBACK INTERFACE (2)
FSPI_READ SPI readback speed 50 MHztES Clock to enable low time 10 nstCS Clock to data wait time 10 nstCWH Clock pulse width high 10 nstCWL Clock pulse width low 10 nstCES Enable to clock setup time 10 ns
There are several other considerations for writing on the SPI:• The R/W bit must be set to 0.• The signal on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.• The CSB must be held low for data to be clocked. Device ignores clock pulses if CSB is held high.• The CSB transition from high to low must occur when SCK is low.• When SCK and SDI lines are shared between devices, TI recommends holding the CSB line high on any
devices besides the intended programming target.
Figure 2. Serial Data Readback Timing Diagram
There are several other considerations for SPI readback:• The R/W bit must be set to 1.• The MUXOUT pin is always for the address portion of the transaction.• The address on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.• The data portion of the transaction on the SDI line is always ignored.• The data on the MUXOUT pin should be considered valid on each rising edge of the SCK pin, provided all
timing requirements are met.• All CSB considerations for SPI writing also apply to SPI readback.
NF Measured; Temperature = -40NF Calculated; Temperature = -40NF Measured; Temperature = 25NF Calculated; Temperature = 25NF Measured; temperature = 85NF Calculated; Temperature = 85
LO Frequency
S11
(dB
)
4000 6000 8000 10000 12000-25
-20
-15
-10
-5
0
D042
LO Frequency (MHz)
LO to
RF
Lea
kage
(dB
m)
4000 6000 8000 10000 12000-80
-70
-60
-50
-40
-30
-20
-10
0
D036
Temperature = -40Temperature = 25Temperature = 85
LO Frequency (MHz)
OP
1dB
(dB
m)
3900 4400 4900 5400 5900 640010
11
12
13
14
15
16
17
18
19
20
D037
External 6dBm LOInternal LO
20
LMX8410LSNAS730A –MARCH 2018–REVISED NOVEMBER 2018 www.ti.com
Figure 39. LO to RF Leakage Level: External LO Mode
1. The LO frequency is capped at 6600MHz because IP1dBexceeds +10dBm when LO frequency goes beyond 6600MHz;The device can be damaged when input power is more than+10dBm.
Figure 40. OP1dB Across LO Frequency
1. Jammer frequency = 8.8GHz, LO = 7.8GHz, IF = 100MHz.2. Internal LO phase noise values used for calculation at -40, 25,
and 85 degrees C are –155, –154.5 and –154 dBc/Hz,separately.
Figure 41. Noise Figure with JammerFigure 42. RF Port S11
1. Board losses and mismatch are not subtracted out. True outputpower may be higher. This plot shows single-ended LO outputpower only. Differential output power can be higher.
Figure 44. LO Output Power
Measurements are done at 25 degree C unless temperature is specified in the plots.For measurements across LO frequency, IF = 65MHz, and LO injection type is high side injection. For measurementsacross IF frequency, high side injection is appliedFor all measurements that require RF input, RF input power = -10 dBm unless otherwise specified.For two-tone measurements, the separation between two tones is 17MHz.For all measurements, internal 1.7V VCM is applied.For all external LO mode measurements, LO power = +6 dBm.IF baluns used for measurements are: ADT2-18+ from Mini-Circuits™.LO balun used for measurements is: BIB-100G from PPM-Test™.RF combiner used for measurements of IP2, IP3 and NF with jammer is: 4426-2 from Narda-MITEQ™.All path losses are calibrated out.
7.1 OverviewThe LMX8410L is a high-performance I/Q demodulator with an RF input range of 4 to 10 GHz and an IF outputrange of DC to 1350 MHz. This device integrates many components to allow high system performance as well assimplified design. There is an integrated synthesizer that generates wide-band frequencies at very low phasenoise, with signal carefully conditioned for driving the mixer LO port. The RF input is single ended, enabled by anintegrated wide-band RF balun at the front end. The two mixers on each I/Q channel are highly linear withoptimized filtering and interfacing with components on each port. The IF amplifier is a high gain and high linearitycomponent, saving users from matching discrete amplifiers and being restricted by common mode voltagestypically encountered when interfacing mixers and ADC’s. In addition to high linearity and low noise performance,the LMX8410L comes equipped with many features to further optimize certain parameters. The automatic DCoffset calibration is run by an internal automatic algorithm which will sense and tune the DC offset between the Nand P sides of the differential signal of each IF amplifier, thus ensuring optimal performance when directly DCcoupled to the ADC. The I/Q calibration knob allows tuning blocks within the mixer and IF amplifier to balanceboth the gain and the phase of the I/Q output signals, thus giving the user capability to adjust and achieve highimage rejection. The internal synthesizer also has a feature of synchronization, which allows multiple LMX8410Ldesigned in parallel to have synchronized LO signal phase.
7.3.1 Device Configurations and Feature Description
7.3.1.1 RF, LO and IF Interfaces
7.3.1.1.1 RF Interface
LMX8410 RF input stage provides a wideband input matching in complete RF frequency range. The RF interfacerequires an external DC block capacitor.
Figure 45. RF Interface
7.3.1.1.2 LO Interface
LO interface for LMX8410 serves dual functionality:1. Drive the VCO or channel divider output to pin LO_M and LO_P.2. Inject external LO signal in external LO mode where on-chip synthesizer needs to be bypassed.
7.3.1.1.2.1 LO Interface as Output Port
When LO interface operates as output port, it drives either VCO or Channel Divider output to the port. The deviceprovides open collector output. Therefore, a pair of off-chip load resistors or inductors are needed in order tohave LO output power.
Figure 46. LO Port Operating In Output Mode Requires Load Resistors Or Inductors
7.3.1.1.2.2 LO Interface as Input Port
When LO interface operates as input port, the pull-up resistors or inductors must be removed. Device pins mustbe AC coupled with DC block. LO pins offer wideband differential 100 Ohm termination to enable port matching.The value of termination can be set to 100Ohm, 200Ohm or high impedance through registerEXTLO_INT_MATCH_RES (R123<1:0>). It is recommended to keep the termination setting to 100 ohm duringexternal LO injection and to high impedance mode while LO is brought out from the device.
LMX8410 has a low impedance output driver capable of driving the resistive as well as capacitive loads.Therefore, a pair of 50 ohm off-chip resistors can be placed in both IF_P and IF_M paths to provide 100Ohmdifferential matching if IF port matching is required.
Figure 48. IF Interface Requires External Resistors for 100Ohm Differential Matching
7.3.1.2 Device Configurations OverviewFollow below steps to configure the device successfully.
7.3.1.2.1 Initialize the Device
After the device is powered on, follow below setups in sequence.1. Set R127 = 0x00032. Set R6 = 0x01003. Set R127 = 0x00004. Load device configuration bits.
7.3.1.2.2 Configure LO Modes
Refer to Table 5 to set up correct LO modes. After LO mode is configured, In case of internal LO mode, lock theintegrated synthesizer and jump to Perform DCOC (DC Offset Correction). In case of external LO mode, go toSet Up External LO Clock.
Feature Description (continued)7.3.1.2.3 Set Up External LO Clock
Follow below steps to set up external LO clock:1. Set external LO divider. Refer to State Machine Clock2. Provide external LO signal on the pin.3. Enable the divider by setting EXTLO_CLK_DIV_EN (R81<7:6>) to 3. This step should be done only after
valid external LO signal is driven on the pin.4. Select SM clock source towards external LO driven SM clock by setting SM_CLK_SEL (R81<0>) = 1.5. Wait for 100 usec before performing DCOC.
7.3.1.2.4 Perform DCOC (DC Offset Correction)
Perform DCOC for both I and Q channels. Refer to DCOC (DC Offset Correction) for detailed instructions.
7.3.1.2.5 Turn Off SM Clock
Turn off SM clock after DCOC to remove coupling spurs from clock signals.1. In internal LO mode, set SM_CLK_EN (R2<10>) to 0.2. In external LO mode, set EXTLO_CLK_DIV_EN (R81<7:6>) to 0.
Refer to Image Rejection Calibration for detailed instructions.
7.3.1.3 State Machine ClockThe State machine clock can be derived, through a MUX, from division of OSCin frequency in internal LO modeor from division of external LO frequency in external LO mode. The upper bound for State machine clock is200MHz while lower bound is 1MHz/10MHZ in internal/external LO modes. In external LO mode, two sets ofdividers need to be programmed to set the right SM clock frequency. DIV_A is an 8-state divider which drivesDIV_B. Input frequency to DIV_B must be kept less than 1.4GHz. Recommended SM_CLK frequency is100MHz.
Figure 49. Block Diagram of SM Clock
7.3.1.3.1 Set Divider Values For Internal LO Mode
The value of divider in internal LO mode is 2^(value of CAL_CLK_DIV).
Feature Description (continued)7.3.1.3.2 Set Divider Values For External LO Mode
The divider for external LO mode is EXTLO_DIV (R82<5:0>), where R82<5:3> sets DIV_A and R82<2:0> setsDIV_B. The value of DIV_A should be set according to Table 1. The value of DIV_B is 2^(value of R82<2:0>).
Table 1. DIV_A EncodingEXTLO_DIV (R82<5:3>) Division Value
7.3.1.4 DCOC (DC Offset Correction)The DC offset of IF output can be automatically corrected by checking EN_DCOC_ICH_LUT andEN_DCOC_QCH_LUT
Figure 50. DC Offset Correction Diagram
7.3.1.4.1 RF Input Power Restriction During DCOC
For best accuracy, power at the RF input of the LMX8410 should be kept below -50dBm during DCOCcalibration. Additional isolation (~15dB) can be obtained by turning of LNA_PD and LNA_BIAS_OFF.
7.3.1.4.2 Set Up DCOC Clock Divider
DCOC state machine clock can operate from 0.5MHz to 2MHz, preferably set to 1MHz. Calculation of clockfrequency: DCOC clock Frequency = (SM_CLK frequency)/(2*DCOC_CLK_DIV value). Refer to State MachineClock for SM_CLK setup. It is recommended to set and reset DCOC_FSM_RESET (R126<8>) every time the LOfrequency is changed.
7.3.1.5 Image Rejection CalibrationLMX8410 provides registers to vary the gain and phase of the I and Q channel individually to improve imagerejection.
Phase magnitude can be tuned using IMRR_PHCAL (R95<14:9>), polarity of phase calibration can be set byIMRR_PHCAL_POL (R95<15>). If Q channel leads I by > 90 deg. Set polarity to ‘0’, otherwise set it to ‘1’.Typical step size of magnitude tuning is 0.2 deg for fine accuracy mode and 0.45 deg for extended range mode.The fine accuracy mode and extended range mode can be set by IMRR_PHCAL_EXTEND (R126<15>). Refer toFigure 29 and Figure 30 for details of the two modes.
7.3.1.5.2 Gain Calibration
The voltage magnitude of I and Q channel can be tuned by IMRR_GCAL_ICH (R94<7:0>) andIMRR_GCAL_QCH (R94<15:8>). The recommended code range is 128 to 255. In this code range, gain tuningrange is 0.5dB. Extended code range is 0 to 127. In this range, step size is higher and gain tuning range is 1dB.Refer to Figure 31 for details of the two code ranges. Re-calibration may be needed with temperature drift.
7.3.1.6 IF Amplifier Common Mode ConfigurationsIF amplifier common mode voltage can be set by VCM_CONFIG (R83<12:9>). Additional setups are neededdepending on VCM magnitude. Refer to Table 2 for more details. For best common mode voltage accuracy,supply external VCM and choose "External" in VCM_CONFIG.
7.3.1.7 Synchronization Mode (Internal LO Mode Only)
7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input
The LO_OUT pin can be synchronized to the Fosc input in exactly the same way that the LMX2594 can. Forcases where the output frequency is not a multiple of the input frequency, the SYNC pin an be used.
7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
When the internal LO is used, IF outputs of two devices can be synchronized to the Fosc input if and only if theVCO frequency is a multiple of the Fosc frequency and there is no multiplication in the input path (OSC_2X = 0and MULT=1). The device is inherently in SYNC all the time in this condition so therefore there is no need to usethe SYNC pin or to toggle the SYNC_PHASE_PLL bit.
7.4 Device Functional ModesThe LMX8410L can be programmed for two functional modes: internal LO mode (using the integratedsynthesizer) or external LO mode (bypassing the integrated synthesizer). In internal LO mode, when 4GHz <=LO frequency <=7.5 GHz, use divide-by-2 (Div 2) mode; when 7.5 GHz <= LO frequency <= 10 GHz, usepolyphase filter mode (Poly). Refer to Table 3 to set up registers correctly. Under special circumstances whereintegrated synthesizer fails to lock at 7.5 ~ 7.7GHz, refer to VCO Range Uncertainty for 7.5 to 7.7 GHz for moreinstructions.
Table 3. Internal LO Mode and External LO Mode Register ConfigurationsFIELD NAME ADDRESS INTERNAL LO/DIV2 INTERNAL LO/Poly EXTERNAL LO
7.4.1 Internal LO ModeWhen using internal LO mode, the integrated synthesizer is activated to generate the desired LO frequency. TheOSCINP and OSCINM pins are used to provide a reference frequency to the PLL and are required to generatethe internal state machine clock. The CP pin generates the phase detector output for use with an external loopfilter. The filtered phase detector output is fed into the VTUNE pin to control the internal VCO, generatingfrequencies between 7.5 GHz and 15 GHz. The VCO output is divided down to close the loop into the phasedetector. The VCO output may be fed directly into the I/Q generation circuitry.
The I/Q generation circuitry has two paths: a divide-by-2 path, and a polyphase filter path. Depending on thefrequency of the LO, the I/Q generation circuitry used will differ. The divide-by-2 path requires the VCO frequencyto be double that of the LO frequency. When the LO frequency is between 4 GHz and 7.5 GHz, the VCO can beprogrammed to between 8 GHz and 15 GHz, and the VCO output can be fed into the divide-by-2 path. When theLO frequency is greater than 7.5 GHz, the VCO can be programmed to between 7.5 GHz and 15 GHz, and theVCO output can be fed into the polyphase filter path.
In Internal LO mode, the LO pins may be used as outputs (refer to LO Interface as Output Port) for threeseparate signals internal to the device:1. The VCO output may be fed directly to the LO pins.2. The VCO may be divided by any possible combination using the channel divider, and the divided output may
be fed to the LO pins. Refer to the datasheet of LMX2594 for more details.
7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHzAlthough the majority of devices have a VCO range of 7.5 to 15 GHz, this is NOT ensured. In reality, the VCO istested for sure to cover 7.7 to 15 GHz. In the range of 7.5 to 7.7 GHz and 15 to 15.4 GHz, the VCO will cover atleast enough frequency to cover a factor of two in frequency. What this means if using the internal mixer is that ifone wants a LO frequency of 7.6 GHz, then first try this using the poly mode and VCO frequency of 7.6 GHz.However, if the VCO can not do 7.6 GHz, then one has to try DIV2 Mode with the VCO at 15.2 GHz.
Table 4. VCO Ensured FrequencyParameter Symbol Ensured Condition
Minimum VCO Frequency fVCOMin fVCOMin <= 7.7 GHzMaximum VCO Frequency fVCOMax fVCOMax >= Max{ 15 GHz , 2 × f VCOMin }
(1) Refer to LO Interface as Input Port for LO interfacing.
7.4.2 External LO ModeWhen using External LO mode, the integrated synthesizer may be powered down and bypassed. The internalstate machine clock is derived by dividing down the LO input. Since the frequency range of the LO circuit isbounded below the operational frequency of the divide-by-2 path, I/Q generation must be done using thepolyphase filter path.
In External LO mode, some pins must be configured differently than in Internal LO mode. Even when thesynthesizer circuitry is bypassed, VCC should be applied to all power pins (though bypass capacitors are nolonger required). Table 5 contains a summary of the External LO requirements.
Table 5. External LO Pin ConfigurationPIN NO. NAME I/O EXTERNAL LO REQUIREMENTS
2 VBIAS_VCO2 Bypass Floating (no connection) or sameconfiguration with internal LO mode
3 VBIAS_VCO1 Bypass Floating (no connection) or sameconfiguration with internal LO mode
42 VBIAS_VARAC Bypass Floating (no connection) or sameconfiguration with internal LO mode
44 VTUNE Input Grounded
47 VREF_VCO Bypass Floating (no connection) or sameconfiguration with internal LO mode
7.5 Programming
7.5.1 General Comments Regarding ProgrammingThis device is programmed using 24-bit shift registers. The shift register consists of a R/W bit (MSB), followed bya 7-bit address field and a 16-bit data field. For the R/W bit, 0 is for write, and 1 is for read. The address fieldADDRESS[6:0] is used to decode the internal register address. The remaining 16 bits form the data fieldDATA[15:0]. While CSB is low, serial data is clocked into the shift register upon the rising edge of clock (data isprogrammed MSB first). When CSB goes
Programming (continued)7.5.2 Recommended Initial Power Up SequenceFor the most reliable programming, TI recommends this procedure: 1. 2. Program RESET = 1 to reset registers.3. Program RESET = 0 to remove reset. 4. Program registers as shown in the register map in REVERSE orderfrom highest to lowest. 5. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCOcalibration runs from a stable state.1. Apply power to device.2. Program Register R127 to value 0x7F00033. Program Register R6 to value 0x0601004. Program registers R127 to R0 in REVERSE Order5. If using internal LO, wait 10 ms and then Program register R0 again
7.5.3 Recommended and Power on Reset Bit ValuesThere a few points of clarification for power on reset values and recommended values.1. Whenever power is cycled on the chip, the registers are reset to their power on reset (not necessarily
recommended) state.2. In the main register map, there are several registers with only 1's and 0's and no defined words. DO NOT
ASSUME that these registers do not need to be programmed. In many cases, these 1's and 0's are differentthan the power on reset values.
3. In the register description, the word 'RESET" is used, but what is really meant is "Recommended" State
7.6 Register MapThis device has 128 registers from R0 to R127. They must be programmed in REVERSE order. Note that thereare several registers that have no description, but they still need to be programmed as the power on reset valueis not always the correct value. The complete listing for all registers, including those not described in thisdatasheet are available on the Registers tab on the TI TICSPro software.
Table 7 lists the memory-mapped registers for the Device registers. All register offset addresses not listed inTable 7 should be considered as reserved locations and the register contents should not be modified.
Table 7. Device RegistersAddress Acronym Register Name Section
Table 8. Device Access Type CodesAccess Type Code DescriptionRead TypeR R ReadWrite TypeW W WriteReset or Default Value-n Value after reset or the default
value
7.6.1 R0 Register (Address = 0x0) [reset = X]R0 is shown in Figure 52 and described in Table 9.
Return to Summary Table.
Figure 52. R0 Register
7 6 5 4 3 2 1 0FCAL_HPFD_A
DJRESERVED FCAL_EN MUXOUT_SEL RESET_PLL PLL_PD
R/W-0x0 R-0x0 R/W-0x1 R/W-0x1 R/W-0x0 R/W-0x0
Table 9. R0 Register Field DescriptionsBit Field Type Reset Description14 SYNC_PHASE_PLL R/W X Puts PLL in SYNC mode so that the channel divider can be
synchronized13-10 RESERVED R X
9 OUT_MUTE R/W X Output buffer automute.0x0 = Disabled0x1 = Mutes output buffer during FCAL and when PLL not locked
Table 10. R1 Register Field DescriptionsBit Field Type Reset Description7-3 RESERVED R 0x02-0 CAL_CLK_DIV R/W 0x3 Divides down for state machine clock [SM clock =
Fosc/2CAL_CLK_DIV]. Maximum state machine clock frequency is200MHz. For fastest calibration speed, choose value which will makestate machine clock closest to 200 MHz.
7.6.3 R2 Register (Address = 0x2) [reset = X]R2 is shown in Figure 54 and described in Table 11.
Return to Summary Table.
Figure 54. R2 Register
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 11. R2 Register Field DescriptionsBit Field Type Reset Description10 SM_CLK_EN R/W X Enables state machine clock9-0 RESERVED R 0x0
7.6.4 R9 Register (Address = 0x9) [reset = X]R9 is shown in Figure 55 and described in Table 12.
Return to Summary Table.
Figure 55. R9 Register
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 12. R9 Register Field DescriptionsBit Field Type Reset Description12 OSC_2X R/W X Enables the frequency doubler after the input reference signal.
0x0 = Bypass0x1 = Enable doubler
11-0 RESERVED R 0x0
7.6.5 R10 Register (Address = 0xA) [reset = 0x80]R10 is shown in Figure 56 and described in Table 13.
Table 13. R10 Register Field DescriptionsBit Field Type Reset Description
11-7 MULT R/W 0x1 Input signal multiplier. When not in bypass, input range is 40-70MHz,output range is 180-250MHz. 1,3,4,5,6, and 7 are the only validvalues.0x1 = Bypass0x3 = x30x4 = x40x5 = x50x6 = x6
6-0 RESERVED R 0x0
7.6.6 R11 Register (Address = 0xB) [reset = 0x10]R11 is shown in Figure 57 and described in Table 14.
Return to Summary Table.
Figure 57. R11 Register
7 6 5 4 3 2 1 0PLL_R RESERVED
R/W-0x1 R-0x0
Table 14. R11 Register Field DescriptionsBit Field Type Reset Description
11-4 PLL_R R/W 0x1 PLL R dividerthat is after the input mulitplier.3-0 RESERVED R 0x0
7.6.7 R14 Register (Address = 0xE) [reset = 0x70]R14 is shown in Figure 58 and described in Table 15.
Table 21. R41 Register Field DescriptionsBit Field Type Reset Description
15-0 MASH_SEED R/W 0x0 The MASH_SEED can be used for optimizing fractional mode (seesimulation tool) and also phase adjustment feature. Phaseadjustment writing to this register will trigger a phase shift (indegrees) = 360 x [MASH_SEED] x [PLL_N_PRE] / [N-dividerdenominator] / [Channel divider]. MASH_SEED must be less than N-divider denominator For example, for MASH_SEED = 100,PLL_N_PRE=2, PLL_DEN = 200, CHDIV=3, Phase Shift = 360 * 100* 2 / 200 / 3 = 120 degrees
7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]R42 is shown in Figure 65 and described in Table 22.
Table 24. R44 Register Field DescriptionsBit Field Type Reset Description
15-8 RESERVED R 0x07 LO_OUT_PD R/W 0x1 Disable output buffer of output A
0x0 = Enable0x1 = Disable (disable if not using output B)
6 RESERVED R 0x05 MASH_RESET_N R/W 0x1 MASH enable. Should be set to 1 in fractional mode. To reset the
MASH toggle from 0 to 1.4-3 RESERVED R 0x02-0 MASH_ORDER R/W 0x2 Fractional-N divider sigma-delta MASH engine order. This sets the
algorithm used in fractional-N mode generation and has impact onfractional spurs. Refer to the datasheet for more information.Recommended values are as follows, but other values may alsowork.
7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]R46 is shown in Figure 68 and described in Table 25.
Return to Summary Table.
Figure 68. R46 Register
15 14 13 12 11 10 9 8RESERVED
R-0x0
7 6 5 4 3 2 1 0RESERVED LO_OUT_MUX
R-0x0 R/W-0x1
Table 25. R46 Register Field DescriptionsBit Field Type Reset Description
15-2 RESERVED R 0x01-0 LO_OUT_MUX R/W 0x1 Selects signal to route to output B
0x0 = Selects the output from channel divider MUX0x1 = Selects output from VCO
7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]R58 is shown in Figure 69 and described in Table 26.
Table 26. R58 Register Field DescriptionsBit Field Type Reset Description15 SYNC_PIN_IGNORE R/W 0x1 Enable this bit when NOT using SYNC mode as the SYNC pin
interferes with lock detect in this case. When PLL_PHASE_SYNC=1,this bit may be disabled with no issues with lock detect.
14-0 RESERVED R 0x0
7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]R59 is shown in Figure 70 and described in Table 27.
Return to Summary Table.
Figure 70. R59 Register
15 14 13 12 11 10 9 8RESERVED
R-0x0
7 6 5 4 3 2 1 0RESERVED LD_TYPE
R-0x0 R/W-0x1
Table 27. R59 Register Field DescriptionsBit Field Type Reset Description
15-1 RESERVED R 0x00 LD_TYPE R/W 0x1 Lock detect type. VCOCal lock detect is high except when the VCO
is calibrating and also during a timeout count right after calibrationset LD_DLY. Vtune and VCOCal lock detect is high wheneverVCOCal lock detect would be high and the VCO tuning voltage iswithin an acceptable range.0x0 = VCOCal0x1 = Vtune and VCOCal.
7.6.20 R69 Register (Address = 0x45) [reset = 0x0]R69 is shown in Figure 71 and described in Table 28.
Table 29. R70 Register Field DescriptionsBit Field Type Reset Description
15-0 MASH_RST_COUNT R/W 0xC350 When using a fractional N value with PLL_PHASE_SYNC=1, this isused to set a delay to allow the SYNC to work properly. In general, itshould be set to a count equal to 4X the analog settling time of thePLL. (LSB)
7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]R75 is shown in Figure 73 and described in Table 30.
Return to Summary Table.
Figure 73. R75 Register
15 14 13 12 11 10 9 8RESERVED CHDIV
R-0x0 R/W-0x0
7 6 5 4 3 2 1 0CHDIV RESERVED
R/W-0x0 R-0x0
Table 30. R75 Register Field DescriptionsBit Field Type Reset Description
15-11 RESERVED R 0x010-6 CHDIV R/W 0x0 Channel divider that divides the VCO frequency.5-0 RESERVED R 0x0
7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]R78 is shown in Figure 74 and described in Table 31.
Return to Summary Table.
Figure 74. R78 Register
15 14 13 12 11 10 9 8RESERVED VCO_CALSTA
RT_CLOSERESERVED
R-0x0 R/W-0x0 R-0x0
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 31. R78 Register Field DescriptionsBit Field Type Reset Description
15-10 RESERVED R 0x09 VCO_CALSTART_CLOS
ER/W 0x0 Uses current values for VCO core, frequency band, and amplitude
as the starting point for the next VCO calibration. Enable this if theVCO frequency change is close, on the order of 50 MHz or less.
7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]R79 is shown in Figure 75 and described in Table 32.
Return to Summary Table.
Figure 75. R79 Register
15 14 13 12 11 10 9 8RESERVED LO_PATH_EN RESERVED
R-0x0 R/W-0x7 R-0x0
7 6 5 4 3 2 1 0RESERVED IFA_PULLUP_
ENRESERVED LNA_PD SIGPATH_RST SIGCHAIN_PD
R-0x0 R/W-0x0 R-0x0 R/W-0x0 R/W-0x0 R/W-0x0
Table 32. R79 Register Field DescriptionsBit Field Type Reset Description15 RESERVED R 0x0
14-12 LO_PATH_EN R/W 0x7 Enables various parts of the Poly and DIV2 Path11-7 RESERVED R 0x0
6 IFA_PULLUP_EN R/W 0x0 Enable the pull up resistor at the input of the IFA. Needed when theoutput comoon mode is <1.4V
5-3 RESERVED R 0x02 LNA_PD R/W 0x0 LNA power down1 SIGPATH_RST R/W 0x0 Master reset for the signal chain0 SIGCHAIN_PD R/W 0x0 Master power down for the signal chain.
7.6.25 R80 Register (Address = 0x50) [reset = 0xA]R80 is shown in Figure 76 and described in Table 33.
Return to Summary Table.
Figure 76. R80 Register
15 14 13 12 11 10 9 8RESERVED SYNC_PHASE
_MIXLOSYNC_DRV2_
ENSYNC_DRV1_
ENRESERVED
R-0x0 R/W-0x0 R/W-0x0 R/W-0x0 R-0x0
7 6 5 4 3 2 1 0RESERVED LO_MUX
R-0x0 R/W-0xA
Table 33. R80 Register Field DescriptionsBit Field Type Reset Description
15-12 RESERVED R 0x011 SYNC_PHASE_MIXLO R/W 0x0 Sync bit to close the loop from Mixer LO back to synthesizer10 SYNC_DRV2_EN R/W 0x0 Enables the SYNC 2nd stage driver from the LO output path. It
should be enabled in SYNC mode.0x0 = Disabled0x1 = Enabled
9 SYNC_DRV1_EN R/W 0x0 Enables the SYNC first stage driver from the LO output path. Itshould be enabled in SYNC mode.0x0 = Disabled0x1 = Enabled
Table 34. R81 Register Field DescriptionsBit Field Type Reset Description
15-12 RESERVED R 0x011-8 LO_POLY_MODE1 R/W 0x0 Sets up parameters for the poly path
0x0 = Internal LO Poly0x15 = External LO0x19 = Internal LO DIV2
7-6 EXTLO_CLK_DIV_EN R/W 0x0 Selects driver for SMCLK0x0 = Internal LO0x1 = Reserved0x2 = Reserved0x3 = External LO
5-4 LO_DRVR_MODE R/W 0x0 Sets up drivers for LO quadrature path0x0 = Internal LO Poly0x1 = Internal LO DIV20x2 = Reserved0x3 = External LO
3 RESERVED R 0x02-1 EXTLO_CLK_DRV_EN R/W 0x0 Enables drivers for state machine clock.0 SM_CLK_SEL R/W 0x0 Selects the state machine clock source for the signal path
0x0 = Internal LO0x1 = External LO
7.6.27 R82 Register (Address = 0x52) [reset = 0x23]R82 is shown in Figure 78 and described in Table 35.
Table 36. R83 Register Field DescriptionsBit Field Type Reset Description
15-13 IFA_PULLUP R/W 0x1 IFA virtual node pull up resistor to set the biasing of the IFA inputstage correct when the output common mode is <1.4V. Should beused in conjunction with the corresponding EN bit in first register.0x2 = Invalid0x4 = Invalid0x5 = Invalid0x6 = Invalid
12-9 VCM_CONFIG R/W 0x0 Output Common mode (VOCM) configuration for IFA. Only one bit tobe set as high at a time. Only valid states are 0,3,5,9.0x0 = 1.70x3 = 2V0x5 = External0x9 = 1.4V
8-0 RESERVED R 0x0
7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]R84 is shown in Figure 80 and described in Table 37.
Table 37. R84 Register Field DescriptionsBit Field Type Reset Description
15-6 DCOC_CLK_DIV R/W 0x64 DCOC clock division controlled5-2 RESERVED R 0x01 EN_DCOC_QCH_LUT R/W 0x0 Enable offset calibration for Q channel. Write 1 to trigger calibration.
To re-trigger, clear this bit and then write 1 again.0 EN_DCOC_ICH_LUT R/W 0x0 Enable offset calibration for I channel. Write 1 to trigger calibration.
To re-trigger, clear this bit and then write 1 again.
7.6.30 R88 Register (Address = 0x58) [reset = 0x0]R88 is shown in Figure 81 and described in Table 38.
Table 38. R88 Register Field DescriptionsBit Field Type Reset Description15 RESERVED R 0x014 rb_DCOC_CAL R 0x0 Status bit. Indicates whether I channel DC offset calibration is done.
0x0 = Neither Channel Done 1 I Channel Done0x2 = Q Channel Done0x3 = Both Channels Done
13-0 RESERVED R 0x0
7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]R94 is shown in Figure 82 and described in Table 39.
Table 39. R94 Register Field DescriptionsBit Field Type Reset Description
15-8 IMRR_GCAL_QCH R/W 0x80 IMRR gain ontrol for the Q channel.7-0 IMRR_GCAL_ICH R/W 0x80 IMRR gain control for the I channel.
7.6.32 R95 Register (Address = 0x5F) [reset = X]R95 is shown in Figure 83 and described in Table 40.
Return to Summary Table.
Figure 83. R95 Register
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 40. R95 Register Field DescriptionsBit Field Type Reset Description15 IMRR_PHCAL_POL R/W X IMRR Phase polarity control using the phase interpolar.
14-9 IMRR_PHCAL R/W X IMRR Phase control using the phase interpolar. Preferred method ofthe IMRR phase correction.
8 LODRV_IMRR_PHCAL_POLCTRL
R/W X IMRR Phase polarity control using the slew control driver.
7-0 RESERVED R 0x0
7.6.33 R103 Register (Address = 0x67) [reset = X]R103 is shown in Figure 84 and described in Table 41.
Return to Summary Table.
Figure 84. R103 Register
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 41. R103 Register Field DescriptionsBit Field Type Reset Description
13-10 LO_POLY_MODE2 R/W X Selects configurations between Poly and DIV2 Mode9-0 RESERVED R 0x0
7.6.34 R110 Register (Address = 0x6E) [reset = X]R110 is shown in Figure 85 and described in Table 42.
7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]R111 is shown in Figure 86 and described in Table 43.
Return to Summary Table.
Figure 86. R111 Register
7 6 5 4 3 2 1 0rb_VCO_CAPCTRL
R-0x0
Table 43. R111 Register Field DescriptionsBit Field Type Reset Description7-0 rb_VCO_CAPCTRL R 0x0 Readback word for the actual value of VCO_CAPCTRL chosen by
the VCO frequency calibration.
7.6.36 R112 Register (Address = 0x70) [reset = 0x0]R112 is shown in Figure 87 and described in Table 44.
Return to Summary Table.
Figure 87. R112 Register
7 6 5 4 3 2 1 0rb_VCO_DACISET
R-0x0
Table 44. R112 Register Field DescriptionsBit Field Type Reset Description8-0 rb_VCO_DACISET R 0x0 Readback word for the actual value of VCO_DACISET chosen by
Table 45. R121 Register Field DescriptionsBit Field Type Reset Description7 RESERVED R 0x0
6-5 BIAS_LNA_CUR_CONFIG_2
R/W 0x0
4-0 RESERVED R 0x0
7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]R123 is shown in Figure 89 and described in Table 46.
Return to Summary Table.
Figure 89. R123 Register
7 6 5 4 3 2 1 0RESERVED EXTLO_INT_MATCH_RES
R-0x0 R/W-0x3
Table 46. R123 Register Field DescriptionsBit Field Type Reset Description7-2 RESERVED R 0x01-0 EXTLO_INT_MATCH_RE
SR/W 0x3 Control internal resistor termination at EXTLO input pin
0x0 = No termination0x1 = 200 Ohms differential termination0x2 = Same as 10x3 = 100 Ohms differential termination
7.6.39 R126 Register (Address = 0x7E) [reset = X]R126 is shown in Figure 90 and described in Table 47.
Return to Summary Table.
Figure 90. R126 Register
7 6 5 4 3 2 1 0RESERVED
R-0x0
Table 47. R126 Register Field DescriptionsBit Field Type Reset Description15 IMRR_PHCAL_EXTEND R/W X Increase the range of the IMRR phase interpolator DAC by 2x
14-9 RESERVED R X8 DCOC_FSM_RST R/W X Reset DC offset
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
8.1 Application InformationTypical Application shows a typical usage of the LMX8410L with internal synthesizer and shows the basiccomponents needed for the operation of the device. There is also guidance on how to design the loop externalloop filter which is part of the LMX8410L synthesizer. The PLLatinum Sim is a tool that allows users to enter theinformation regarding the input reference and target LO frequency they need and simulate the expected phasenoise and performance parameters for the synthesizer.
8.2 Typical Application
Figure 91. Typical Application Schematic
8.2.1 Design RequirementsThe design of the loop filter is complex and is typically done with software. The PLLatinum Sim software is anexcellent resource for doing this and the design is shown in the following figure. For those interested in theequations involved, the PLL Performance, Simulation, and Design Handbook listed in the end of this documentgoes into great detail as to theory and design of PLL loop filters. PLLatinum Sim does not model the mixers andLNAs in this device, but it can be used for the PLL. To use this tool, it can be modeled as the LMX2594 PLL.
Typical Application (continued)8.2.2 Detailed Design ProcedureThe integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates tosignal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noiseoutside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if loop bandwidth is designed tothe point where the two intersect. A higher phase margin loop filter design has less peaking at the loopbandwidth and thus lower jitter. The tradeoff with this is that longer lock times and spurs must be considered indesign as well.
As for software programming, it is highly recommended to use the TICSPro software. In addition to simplifyingthe process, it also gives the user recommended programming default values for the undisclosed registers notmentioned in the datasheet.
9 Power Supply Recommendations1. Design 5-V supply to be capable of greater than 200 mA.2. Design 3.3-V supply to be capable of greater than 800 mA.3. Supply to channel I and Q sides must be well matched and isolated from one another. Recommend using
ferrite beads in series to the pin. The I and Q supplies are for IF amplifier (at pin 38 and 23), for RF input (atpin 33 and 29), and for IF path circuitry (at pin 35 and 27).
4. Pins 7 and 16 are supplies for digital circuitry, and they can have extra isolation in this path (TI recommendsusing ferrite bead in series to the pin).
5. Pins 12, 19, and 46 are supplies for the internal synthesizer; designer must take care not to have noisesources that can couple to it nearby.
6. Typically use 0.1-µF capacitors near the pins. Add extra capacitance values at specific frequencies if knowninterfering frequencies in system. See Pin Configuration and Functions for more recommendations oncomponent value recommendations.
10 Layout
10.1 Layout GuidelinesGenerally, there are two major focuses of layout guidelines: high frequency signals and power routing.
10.1.1 High Frequency Trace Routing• Design all traces for matched impedance. The single-ended RF trace must be controlled for 50-Ω impedance,
while the differential OSCIN, LO, and IF traces must be controlled for 100-Ω differential impedance.• Run an uninterrupted ground plane beneath all impedance-controlled traces. No other currents should flow
directly under the controlled impedance traces.• Keep high-frequency traces as short as possible to minimize losses, or potential for cross-coupling.• Controlled impedance can be challenging in materials not designed for RF applications. For example,
standard FR-4 has a wide range of acceptable dielectric constants in practice. Although the constants seen inboards from the same panel or material lot code may match very well, this does not ensure that the constantsmatch between different lots or different dielectric manufacturers. Furthermore, FR-4 has a high loss tangentcompared to many other materials, which can result in much greater attenuation of high frequency signalsacross the same distances. TI recommends the use of materials designed specifically for high-frequency use,such as RO4350B or RO4003C from Rogers Corporation.
• The RF pin is surrounded on three sides by ground pins to assist in the creation of a coplanar waveguidestructure. Design the coplanar waveguide to minimize current flow on the ground traces around the pins.
• The IF outputs are low impedance, and require resistors to set the output impedance.• The LO pins are capacitively coupled as inputs, with internal 50-Ω termination. Use 50-Ω pullup resistors to
VCC_BUF to bias these pins as inputs, if driven through external capacitors. The LO pins require 50-Ω pullupresistors to VCC_BUF as outputs.
• The LO pins are located very close to the Q-channel IF pins, and the LO buffer supply is located betweenthese two ports. Placing a bypass capacitor as close as possible to the LO buffer is recommended for properoperation, but this presents a potential problem: vias to VCC and GND must be routed between thedifferential pairs. Because the high frequency currents in the bypass capacitor and the LO buffer circuit tendto follow the loop with the lowest inductance, and since the VCC via interrupts the path from capacitor groundto IC ground on the plane layer immediately below the top, ground currents tend to travel around this via, inthe path of the LO and IF coupling to the plane layer. To maintain the signal integrity of both the LO and IFdifferential traces, no other currents should be flowing immediately below them on the plane layer. Therefore,the LO bypass capacitor ground via must not connect to the plane layer immediately below the capacitor. TIrecommends connecting through the subsequent layer. See the Layout Example section on how this is done.
Layout Guidelines (continued)10.1.2 Power Trace Routing• Regardless of whether the part is used in internal or external LO mode, all synthesizer VCC and GND pins
must be connected properly. If VCC and GND pins are not connected on the synthesizer, the internal power-up procedure may not execute properly. Noise may also be coupled into the mixer from the synthesizercircuitry if power and ground are not properly connected.
• Place bypass capacitors, whenever possible, to minimize the inductance of the current loop formed by thecapacitor and the IC. Placing the bypass capacitors on the same surface as the IC allows one terminal to beconnected closely to the IC, minimizing this loop. The ground connection can also be made low-inductance byplacing a ground via to a plane layer immediately below. Placing capacitors on the opposite surfacesubstantially limits the effective frequencies they can bypass, since the current must travel through two vias.The loop area formed by placing a capacitor on the opposite surface is almost always larger than the looparea formed by placing a capacitor on the same surface.
• Consider the path that ground currents will take. For optimal performance, supply and bypass capacitorcurrents must not flow underneath high-frequency traces.
• Use as many ground vias as possible to connect the IC pad to the ground plane. This is required for optimalthermal performance.
• Connect ground pins back to the pad. Aside from routing convenience, the inductance through the bond wirestends to be very high, and the inductance through the ground pad tends to be very low.
• Avoid connecting different VCC pins in such a way that the current paths overlap. Overlapping current pathscan inject common-mode noise into the supply pins, degrading performance.
11.1.1 Related DocumentationFor related documentation see the following:
LMX8410LEVM User Guide
11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
11.4 TrademarksE2E is a trademark of Texas Instruments.Narda-MITEQ is a trademark of L3 Narda-MITEQ.Mini-Circuits is a trademark of Mini-Circuits.PPM-Test is a trademark of Pulse Power & Measurement Ltd..All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
LMX8410RGZR ACTIVE VQFN RGZ 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LMX8410
LMX8410RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 LMX8410
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.
VQFN - 1 mm max heightRGZ 48PLASTIC QUADFLAT PACK- NO LEAD7 x 7, 0.5 mm pitch
4224671/A
www.ti.com
PACKAGE OUTLINE
C
SEE TERMINALDETAIL
48X 0.300.18
5.6 0.1
48X 0.50.3
1.00.8
(0.2) TYP
0.050.00
44X 0.5
2X5.5
2X 5.5
B 7.16.9
A
7.16.9
0.300.18
0.50.3
VQFN - 1 mm max heightRGZ0048DPLASTIC QUAD FLATPACK - NO LEAD
4219046/B 11/2019
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
1225
36
13 24
48 37
(OPTIONAL)PIN 1 ID 0.1 C A B
0.05
EXPOSEDTHERMAL PAD
49 SYMM
SYMM
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 1.900
DETAILOPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
10X(1.33)
10X (1.33) 6X (1.22)
0.07 MINALL AROUND
0.07 MAXALL AROUND
48X (0.24)
48X (0.6)
( 0.2) TYPVIA
44X (0.5)
(6.8)
(6.8)
6X(1.22)
( 5.6)
(R0.05)TYP
VQFN - 1 mm max heightRGZ0048DPLASTIC QUAD FLATPACK - NO LEAD
4219046/B 11/2019
SYMM
1
12
13 24
25
36
3748
SYMM
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE:12X
49
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
EXPOSED METALMETAL
SOLDER MASKOPENING
SOLDER MASK DETAILS
NON SOLDER MASKDEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
48X (0.6)
48X (0.24)
44X (0.5)
(6.8)
(6.8)
16X ( 1.13)
(1.33)TYP
(0.665 TYP)
(R0.05) TYP
(1.33) TYP
(0.665)TYP
VQFN - 1 mm max heightRGZ0048DPLASTIC QUAD FLATPACK - NO LEAD
4219046/B 11/2019
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
SYMM
METALTYP
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:15X
SYMM
1
12
13 24
25
36
3748
49
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.
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