LOGIC DESIGN WITH VHDL

What is VHDL ? V HSIC (Very High Speed Integrated Circuit) Hardware Description Language

VHDL is a Design Description LanguageVHDL is a Design Documentation LanguageVHDL is a Simulation Language

It is an IEEE Standard Language (IEEE1076 & 1164)

2Why Use VHDL?Very Fast Time-to-MarketAllows designers to quickly develop designs requiring tens of thousands of logic gates or moreProvides powerful high-level constructs for describing complex logicSupports modular design methodology and multiple levels of hierarchy

One language for design and simulation

Allows creation of device-independent designs that are portable to multiple PLD vendorsAllows user to pick any synthesis tool, vendor, or device

VHDL Design DescriptionsVHDL design descriptions consist of an ENTITY declaration and an ARCHITECTURE body

The ENTITY declaration describes the design I/O

The ARCHITECTURE body describes the content or function of the design

Every architecture needs an entity so it is common to refer to them together as an ENTITY/ARCHITECTURE PAIR

1The EntityA BLACK BOXThe ENTITY describes the I/O of the black boxBLACK_BOXrstd[7:0]clkq[7:0]co

Example Entity declarationENTITY black_box IS PORT (clk, rst:INstd_logic;d:IN std_logic_vector(7 DOWNTO 0);q:OUTstd_logic_vector(7 DOWNTO 0);co:OUT std_logic);END black_box;

What does it all mean ?

2PortsThe Entity (BLACK BOX) has PORTS

PORTS are the points of communicationPORTS are usually the device pins

PORTS have an associated name, mode, and type

3Port ModesA ports MODE indicates the direction that data is transferred:

INData goes into the entity only

OUTData goes out of the entity only (and is not used internally)

INOUTData is bi-directional (goes intoand out of the entity)

BUFFERData that goes out of the entity and is also fed-back internallyEntity

4IEEE 1076 TypesEvery port on the entity has a Type. The type is always checked during an assignment or comparison.BIT - a port of type bit that can only take values of '0' or '1'BIT_VECTOR - a grouping of bits (each can be '0' or '1') ENTITY type_example IS PORT ( a: IN BIT; b: OUT BIT_VECTOR(0 TO 3); -- ascending range c: OUT BIT_VECTOR(3 DOWNTO 0); -- descending rangeEND type_example;

b

INTEGERuseful as index holders for loops, constants, arithmetic functions, or simulation modelingBOOLEANcan take values TRUE or FALSEENUMERATEDhas user defined set of possible values. e.g.:

TYPE traffic_light IS (red, yellow, green);IEEE 1076 Types (contd.)

IEEE 1164A package created to solve the limitations of the BIT typeNine values instead of just two ('0' and '1')Allows increased flexibility in VHDL coding, synthesis, and simulationSTD_LOGIC and STD_LOGIC_VECTOR are used instead of BIT and BIT_VECTOR when a multi-valued logic system is requiredSTD_LOGIC and STD_LOGIC _VECTOR must be used when tri-state logic (Z) is requiredTo be able to use this new type, you need to add 2 lines to your code:LIBRARY ieee;USE ieee.std_logic_1164.ALL;

IEEE-1164 TypesSTD_LOGIC and STD_LOGIC_VECTOR are now the industry standard logic type for digital designAll 9 values are valid in a VHDL simulator, however only:0-- Hard 01-- Hard 1Z-- High ImpedanceL-- Weak 0 (like resistor pull down)H-- Weak 1 (like resistor pull up)--- Dont careare recognized for logic synthesis

Entity Declaration ExampleLIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY black_box IS PORT (clk, rst:INstd_logic;d:IN std_logic_vector(7 DOWNTO 0);q:OUTstd_logic_vector(7 DOWNTO 0);co:OUT std_logic);END black_box;

Exercise #1: The EntityWrite an entity declaration for the following:

Port D is a 12-bit bus, input onlyPort OE and CLK are each input bitsPort AD is a 12-bit bi-directional busPort A is a 12-bit bus, output onlyPort INT is an outputPort AS is an output also used internallymy_designd[11:0]oeclkad[11:0]a[11:0]intas

Exercise #1: SolutionLIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY my_design IS PORT (d:IN std_logic_vector(11 DOWNTO 0);oe, clk:IN std_logic;ad:INOUT std_logic_vector(11 DOWNTO 0);a:OUT std_logic_vector(11 DOWNTO 0);int:OUT std_logic;as:BUFFER std_logic);END my_design;-- In this presentation, VHDL keywords -- are highlighted in bold, CAPITALS.-- However, VHDL is not case sensitive: -- clock, Clock, CLOCK all refer to the-- same signal

3The ArchitectureArchitectures describe what is in the black box (i.e. the function or behavior of entities)Descriptions can be either a combination ofStructural descriptions Instantiations of building blocks (placement of componentsjust like a schematicand their connections)Behavioral descriptions Algorithmic (or high-level) descriptions:IF a = b THEN state

Behavioral Architecture ExampleENTITY black_box IS PORT (a, b:INstd_logic_vector(7 DOWNTO 0);y:OUTstd_logic_vector(7 DOWNTO 0));END black_box;

ARCHITECTURE example OF black_box ISBEGIN y

4SignalsTypically used to represent wires (or nets)Entity Ports are a special type of signalLike ports, they have a name and type (however, there is no mode)Signals are declared inside the architecture before the BEGINFor Example, to create an internal 4 bit bus:

ARCHITECTURE signal_example OF black_box ISSIGNAL count: std_logic_vector (3 DOWNTO 0);BEGIN .. END signal_example;

Combinatorial LogicThere are many ways to describe combinatorial circuits

In the next few slides, we will take a look at some examples of how to describe combinatorial logic

You should refer back to these slides for some ideas when you start writing your first designs

1VHDL Statement Examples (1) Boolean EquationsAll standard Boolean operators are supported in VHDLAND, OR, NOT, XOR, XNOR, NANDFor example, a 4-1 multiplexer is shown below

x

2VHDL Statement Examples (2) WITH-SELECT-WHENAssignment based on a selection signalWHEN clauses must be mutually exclusive (all different)Always use WHEN OTHERS to cover unspecified casesOnly one reference to the signal, only one assignment operator (

VHDL Statement Examples (2) WITH-SELECT-WHENThe same 4-1 multiplexer we saw earlier could also be described as follows:

WITH A SELECT x

VHDL Statement Examples (2) WITH-SELECT-WHENThere can be multiple conditions on each line:

WITH s SELECT x

VHDL Statement Examples (3) WHEN- ELSESignal is assigned a value based on conditionsAny simple expression can be a conditionPriority goes in order of appearanceOnly one reference to the signal, only one assignment operator (

VHDL Statement Examples (3) WHEN-ELSEThe same example 4-1 multiplexer could also be described as follows:

x

VHDL Statement Examples (3) WHEN-ELSEWhat is the difference between WITH-SELECT-WHEN and WHEN-ELSE ?WITH-SELECT-WHEN allows only one control signalWHEN-ELSE supports many different control signals

Example: A priority encoder

j

VHDL StatementsThere are two types of statements, Concurrent and Sequential

Concurrent Statements (means in parallel)Concurrent statements are executed concurrently (at the same time)

The examples we have seen so far are all concurrent statements: Boolean Equations WHEN-ELSE WITH-SELECT-WHEN

The order of concurrent statements is not important

The order of concurrent statementsFor example, suppose we had the following 2 lines of code:

x

2VHDL Statements (cont.)Sequential Statements (means in series)Sometimes we need to model complex functions. In that case, we can use an algorithm or a model to describe the function. This is done with Sequential Statements

With Sequential statements, the ORDER of the statements is important (example later)

Therefore, we use a process to mark the beginning and end of a block of sequential statements

Each completed process is considered to be one big concurrent statement (there can be many processes inside one architecture)

3What is a VHDL Process ?Processes are either awake or asleep (active or inactive)

A process normally has a sensitivity list()When a signal in that sensitivity list changes value, the process wakes up and all of the sequential statements are executedFor example, a process with a clock signal in its sensitivity list will become active on changes of the clock signal

At the end of the process, all the outputs are updated and the process goes back to sleep until the next time a signal changes in the sensitivity list

The Process: An Examplemux: PROCESS (a, b, s)BEGINIF s = '0' THEN x

4Combinatorial Logic using Sequential StatementsWe have already looked at some examples of combinatorial logic using Concurrent Statements

Lets take a look at how to create combinatorial logic with sequential statements...

1Sequential Statement Examples (1) IF-THEN-ELSEFor example, a 4 to 1 mulitplexer could be described as follows:

mux4_1: PROCESS (d0, d1, d2, d3, A)BEGIN IF A = 00 THEN x

How can the order of sequential statements make a difference ?ex1: PROCESS (a, b)BEGIN IF a=1 THEN c

2Sequential Statement Examples (2) CASE-WHENAnother way to describe the same 4 to 1 mux:

mux4_1: PROCESS (d0,d1,d2,d3,A)BEGINCASE A ISWHEN "00" => x x

5A Note about ProcessesSignal AssignmentTake a look at the following piece of code. Which circuit do you think will be synthesized ?

PROCESS (clock)BEGINIF rising_edge(clock) THENb

Signal Assignment in ProcessesInside processes, signals are not updated immediately. Instead, they are scheduled to be updated

The signals are not actually updated until the END PROCESS statement is reached

Therefore, on the previous slide, two registers will be synthesized (c

6VariablesWhen a concurrent signal assignment outside the process cannot be used, the previous problem can be avoided using a variableVariables are like signals, BUT they can only be used inside a PROCESS. They cannot be used to communicate information between processesVariables can be of any valid VHDL data typeThe value assigned to a variable is available immediatelyAssignment of variables is done using a colon (:), like this:c := a AND b;

Using Variables vs. SignalsSolution using a variable within a process:c

PROCESS (clock)VARIABLE b : std_logic ;BEGIN IF rising_edge(clock) THEN b := a ; -- this is immediatec

Native Operators (IEEE-1076) Logical - defined for type BIT, BIT_VECTOR, BOOLEANAND, NANDOR, NORXOR, XNORNOT

Relational - defined for types BIT, BIT_VECTOR, INTEGER= (equal to)/=(not equal to)=(greater than or equal to)

Native Operators (continued)Arithmetic - defined for type INTEGER+(addition), * (multiplication)-(subtraction)

Concatenation - defined for STRING& A STRING is any sequence of charactersstd_logic_vector is an example of a STRINGNote: None of these operators were defined to support std_logic or std_logic_vector types because in IEEE-1076, std_logic did not exist yet. How can we fix this problem ?

2Overloaded OperatorsIn VHDL, any native operator can be overloaded (means re-defined) to accept any other VHDL type. This is very useful. For example:

SIGNAL counter: std_logic_vector(15 DOWNTO 0);counter

Exercise #2: Architecture Declaration of a ComparatorThe entity declaration is as follows:LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY compare IS PORT (a, b: IN std_logic_vector(0 TO 3);aeqb: OUT std_logic);END compare;Write an architecture that causes aeqb to be asserted high only when a is equal to b

Multiple solutions exist. Look back at the 4-1 mux examples

Ex2 Solution: 3 possible solutionsConcurrent statement solution using a conditional assignment:Concurrent statement solution using boolean equations:ARCHITECTURE archcompare OF compare ISBEGINaeqb

3 possible solutions (contd.)Solution using a process with sequential statements:ARCHITECTURE archcompare OF compare ISBEGINcomp: PROCESS (a, b)BEGINIF a = b THENaeqb

3Aggregates and SubscriptsThe aggregate assignment joins signals togetherGood for creating a bus from several single bitsConcatenation operator can be used as wellSame number of array elements on both sidestmp

LIBRARY Ieee;USE Ieee.std_logic_1164.ALL; --

Entity decoder_7seg is port ( indata:in std_logic_vector(3 downto 0); ena:in std_logic; --bit disp:out std_logic_vector(6 downto 0)); --bit_vectorend decoder_7seg;architecture a of decoder_7seg is begin process(indata, ena)begin 4--usestd_logic_...bit

if ena='1' then case indata is -- abcdefgwhen "0000"=>dispdispdispdispdispdispdispdispdispdispdisp

LIBRARY ieee;

ENTITY adder_8bits ISPORT (op1, op2 :in integer range 0 to 255);c:out bit;sum:out integer);END adder_8bits;

ARCHITECTURE a1 OF adder_8bits IS

BEGINsum

LIBRARY ieee;

ENTITY adder_8bits ISPORT (op1, op2 :in integer range 0 to 255;c :out bit; sum :out integer);END adder_8bits;

ARCHITECTURE a2 OF adder_8bits ISBEGINprocess(op1,op2)variable num :integer;beginnum :=op1 + op2;if num >= 255 then num :=num - 255; c

Describing Registers using VHDLWrite a process that is sensitive to a clock edgeExample: a D-type flip-flopENTITY registered IS PORT ( d, clk:IN std_logic;q:OUT std_logic);END registered;ARCHITECTURE archregistered OF registered ISBEGINflipflop: PROCESS (clk)BEGINIF rising_edge(clk) THENq

Describing Registers using Behavioral VHDLThe synthesis compiler knows that a register is to be created for the signal q because:The clock (clk) is in the sensitivity listThe construct rising_edge(clk), appears in the process

There is no else in the if-then statement. This implies that if the rising_edge(clk) condition is not true, then q will hold its current value (this is referred to as implicit memory)

ENTITY regdff ISPORT(d: IN BIT;clk: IN BIT;q: OUT BIT);END regdff;

ARCHITECTURE a OF regdff ISBEGINPROCESS (clk)--BEGINIF (clk'EVENT AND clk = '1') THEN --clk = '1'q

DVHDL-3ENTITY regdff ISPORT(d: IN BIT;clk: IN BIT;q: OUT BIT);END regdff;

ARCHITECTURE a OF regdff ISBEGINPROCESS --WAITBEGINWAIT UNTIL (clk'EVENT AND clk = '1');q

DVHDL-process(clk, d) --D begin if clk= 1 -- then q

2Implicit memoryRemember that inside a process assignments do not occur immediately. Each signal has a current value and may be scheduled for a future value

At the end of the process, if a signal has not been assigned to a new value, then a latch will be synthesized to hold the current value

Advantages:Helps us to create synchronous flip flops

Disadvantages:Can generate unwanted latches in combinatorial logic designs

Implicit memory:Example of incomplete specificationNote: the incomplete specification of the IF...THEN... statement causes a latch to be synthesized to hold the previous state of c when a = 0ARCHITECTURE archincomplete OF incomplete IS BEGINim_mem: PROCESS (a,b)BEGINIF a = '1' THEN c

Implicit memory:Example of complete specificationThe conditional statement is now fully specified, and this causes the process to synthesize to a single gate. There is no implicit memory (latch) synthesizedARCHITECTURE archcomplete OFcomplete IS BEGINno_mem: PROCESS (a, b)BEGINIF a = '1' THEN c

The Rules to Avoid Implicit MemoryTo avoid the generation of unexpected latchesAlways terminate an IF...THEN... statement with an ELSE clauseCover all alternatives in a CASE statementDefine every alternative individually, orTerminate the CASE statement with a WHEN OTHERS... clause. For example:

CASE select ISWHEN "100" => key key key key

3A Registered Process (Template #1)A 4-bit counter with synchronous resetLIBRARY cypress;USE cypress.std_arith.ALL; -- overload the + operatorupcount: PROCESS (clk)BEGINIF rising_edge(clk) THENIF reset = '1' THEN -- synchronous resetcount

A Registered Process (Template #2)A 4-bit counter with asynchronous resetLIBRARY cypress;USE cypress.std_arith.ALL;upcount: PROCESS (clk, rst)BEGINIF rst = '1' THEN count

A Registered Process (Template #3)A 4-bit loadable counter with asynchronous resetLIBRARY cypress; USE cypress.std_arith.ALL;...upcount: PROCESS (clk, rst)BEGINIF rst = '1' THENcount

libraryieee;ENTITY mycounter isport(clk, clear:in bit;c: out bit;qc: out integer range 0 to 15);constant modulus: integer :=10;--end mycounter;architecture a of mycounter is beginPROCESS (clk,clear)VARIABLEcnt: integer range 0 to 16;BEGINIF (clear=0) THEN cnt:= 0; c

Exercise #4Making use of the previous examples, write ONE entity/architecture pair for the following design:DINQREGISTER44QPPEQQCOMPARATOR4COUNTCLOCKLDDATARESET (sync)ENCLDDINQCOUNTERRSTENRENR

Exercise #4: SolutionLIBRARY ieee;USE ieee.std_logic_1164.ALL;LIBRARY cypress;USE cypress.std_arith.ALL; -- overload + for counter ENTITY ex4 IS PORT ( clock, reset, ld, enr: IN std_logic;data: IN std_logic_vector (3 DOWNTO 0);count: BUFFER std_logic_vector (3 DOWNTO 0));END ex4;

ARCHITECTURE archex4 OF ex4 ISSIGNAL peqq: std_logic;SIGNAL regout: std_logic_vector (3 DOWNTO 0);BEGINreg: PROCESS (clock)BEGIN IF rising_edge(clock) THEN IF enr=1 THEN regout

Exercise #4: Solution (contd.)cntr: PROCESS (clock)BEGINIF rising_edge(clock) THENIFreset = '1' THENcount

State MachinesMany implementations are possible, including:

Automatic State Assignmentthe compiler chooses the state encodingoutputs must be decoded from the state registers can be a combinatorial decode can be a registered decode

Specific State Assignment you choose the state encoding outputs may be encoded inside the state registers

library ieee;use ieee.std_logic_1164.all;

entity stmch1 is port(clk, x, rst: in std_logic; y: out std_logic);end stmch1;architecture behave of stmch1 isbegin process (clk, rst) type state_values is (s0, s1, s2); variable state, next_state: state_values; begin if rst = 1 then state := s0; y if x = '1' then next_state := s1; y

library ieee;use ieee.std_logic_1164.all;

entity stmch2 is port(clk, x, rst: in std_logic; y: out std_logic);end stmch2;architecture behave of stmch2 is type state_values is (s0, s1, s2); signal state : state_values;begin process (clk, rst) begin if rst = '1' then state

library ieee;entity stmch5 is port(clk, x, rst: in bit; y: out bit; st:out bit_vector(1 downto 0));end stmch5;architecture behave5 of stmch5 is type state_values is (s0, s1, s2); signal state : state_values; --signalbegin pro1:process (clk, rst) begin----1 if rst = '1' then state

Example: A Traffic Light ControllerLets take a look at an example state machine and see how to describe it using the 3 types of implementations:RESET(asynchronous)REDTIMER1YELLOWGREENTIMER1TIMER2TIMER2TIMER3TIMER3

Example: The Entity DeclarationThe entity declaration remains exactly the same for each implementation.For example:

LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY state_machine IS PORT (clock, reset: IN std_logic;timer1, timer2, timer3: IN std_logic;r, y, g:OUT std_logic);END state_machine;

Example: Solution 1Combinatorial outputs decoded from the state registersARCHITECTURE arch_1 OF state_machine IS

TYPE traffic_states IS (red, yellow, green); -- enumerated typeSIGNAL sm: traffic_states;

BEGIN

fsm: PROCESS (clock, reset) -- the process describes theBEGIN -- state machine onlyIF reset = '1' THEN sm IF timer1=1 THEN sm IF timer2=1' THEN sm

Example: Solution 1 (contd.)WHEN yellow => IF timer3=1' THEN sm sm

(1) Automatic State Assignment: Combinatorial Decode of OutputsOutputs decoded from state bits COMBINATORIALLYcombinatorial output logic is in series with state registersoutputs are a function of the present state onlytime from clock to output (tco) is longInputsNextStateLogicStateRegistersOutputsPresent StateNext Statetco

Example: Solution 2Registered outputs decoded from the state registersARCHITECTURE arch_2 OF state_machine IS

TYPE traffic_states IS (red, yellow, green);SIGNAL sm: traffic_states;

BEGIN

fsm: PROCESS (clock, reset) -- the process describes theBEGIN -- state machine AND the outputsIF reset = '1' THEN sm

Example: Solution 2 (contd.) WHEN green => IF timer2=1' THEN sm

(2) Automatic State Assignment: Registered Decode of OutputsOutputs decoded from state bits using REGISTERSregistered output logic is in parallel with state registersoutputs are a function of the previous state and the inputstco is shorter, but you need more registersOutputsStateRegistersOutputLogicInputsNextStateLogicPresent State

Example: Solution 3Outputs encoded inside the state registersARCHITECTURE arch_3 OF state_machine IS

SIGNAL sm: std_logic_vector(2 DOWNTO 0) ; CONSTANT red: std_logic_vector(2 DOWNTO 0) := 100" ; CONSTANT green: std_logic_vector(2 DOWNTO 0) := "010" ; CONSTANT yellow: std_logic_vector(2 DOWNTO 0) := "001" ;

BEGIN

fsm: PROCESS (clock, reset) -- the process describes theBEGIN -- state machine onlyIF reset = '1' THEN sm IF timer1=1 THEN sm

Example: Solution 3 (contd.)

WHEN green => IF timer2=1' THEN sm

(3) Specific State AssignmentWe encoded the outputs within the state registersNote: All bits of the state encoding were used as outputs

StateMachines: SummaryOutputs decoded from the state machine registerssimplies the design processusing enumerated types allows automatic state assignment during compilation but, performance (speed) may not be optimal

Outputs encoded within the state machine registersmanual state assignment using constantsthe state registers and the outputs are mergedreduces the number of registers but, may require more complex logic

[6.30]

CLK000011002010300141115001601071008000

libraryieee;entity statee is port(clk :in bit;red, yellow, green: out bit); end entity statee;architecture behave of statee issignal q :integer range 0 to 7;begincnt: process(clk)variable cnt: integer range 0 to 7;beginif clk'event and clk='1' then if cnt < 7 then cnt:=cnt+1; else cnt:=0; end if;end if;q red

CLK000011002010300141115001601071008000

Hierarchical (Modular) DesignsA hierarchical design is one which is broken down into many levels, with a top level design bringing all the lower-level components together

This allows very complex designs to be divided down into smaller, more easily managed modules

In the past, this was the major advantage of schematic capture tools

But, VHDL also supports hierarchical designs !!

Hierarchical Design MethodologyAdvantages:

Components (VHDL models) can be created, tested and stored for later use (re-usable code)

Allows the re-use of common building blocks

Allows you to purchase 3rd Party off-the-shelf modules (e.g. UART, PCIbus Interface etc)

Makes the design more readable and easier to understand

Complex design tasks can be split across many designers in a team

VHDL Hierarchy Decomposition In VHDL, hierarchy is composed of:

COMPONENTsentity/architecture pairs which can be instantiated (placed) within other designsPACKAGEsa collection of one or more COMPONENTs and other declarations LIBRARIESa collection of COMPILED design unitse.g. packages, components, entity/architecture pairs etc.

Hierarchy: Schematic Capture vs. VHDLbselmux2to1acsymbolcomponentschematicentity/architecturetop level schematictop level entity/architecturertoplevelqscbmux2to1aseltp

Hierarchy ManagementYour Design (VHDL)LIBRARY ieee;USE ieee.std_logic_1164..LIBRARY cypress;USE cypress.std_arith.allLibrary (Compiled)ieeeLibrary (Compiled)cypressPackages (VHDL)Others (VHDL)std_logictypedefinitionsOthers (VHDL)overloadedoperatorsPackages (VHDL)std_logic_1164std_arith Libraries are used to store re-usable components, type definitions, overloaded operators etc. You add the LIBRARY and USE clauses to your code to get access to them

Package and Component DeclarationsWhen you have created a working entity/architecture pair, you need to add a component declaration to make it a re-usable COMPONENTCOMPONENTS need to be stored in PACKAGES, so you need to write a package declaration to store all your componentsWhen you compile your package with no errors, the components will be stored in the WORK libraryWORK is the default library where everything YOU compile gets stored. Because it is the default library, you do NOT need to add: LIBRARY WORK; -- not required

Package and Component Declarations: An ExampleLIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE mymuxpkg ISCOMPONENT mux2to1 PORT (a, b, sel: IN std_logic; c: OUT std_logic); END COMPONENT;END mymuxpkg;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux2to1 IS PORT (a, b, sel: IN std_logic; c: OUT std_logic);END mux2to1;

ARCHITECTURE archmux2to1 OF mux2to1 ISBEGIN c

Top Level Sheet: ExampleSignals are connected via a PORT MAP that associates signals with the components I/O The port map describes how to wire-up the componentLIBRARY ieee; -- get access to the ieee libraryUSE ieee.std_logic_1164.ALL; -- get access to std_logic_1164 packageENTITY toplevel IS PORT (s: IN std_logic; p, q, r: IN std_logic_vector(2 DOWNTO 0);t: OUT std_logic_vector(2 DOWNTO 0));END toplevel;USE WORK.mymuxpkg.ALL; -- get access to the mymuxpkg packageARCHITECTURE archtoplevel OF toplevel ISSIGNAL i: std_logic_vector(2 DOWNTO 0);BEGINm0: mux2to1 PORT MAP (a=>i(2), b=>r(0), sel=>s, c=>t(0));m1: mux2to1 PORT MAP (c=>t(1), b=>r(1), a=>i(1), sel=>s);i

Exercise #6The same design from ex4. This time, well use a separate entity/architecture for each block and use VHDL hierarchyDINQREGISTER44QPPEQQCOMPARATOR4COUNTCLOCKLOADDATARESET (sync)ENCLDDINQCOUNTERRSTENRENR

Exercise 6 Solution: package.vhdLIBRARY ieee;USE ieee.std_logic_1164.ALL;

PACKAGE ex6_pkg IS

COMPONENT comp4 PORT ( p, q : IN std_logic_vector (3 DOWNTO 0); peqq : OUT std_logic); END COMPONENT;

COMPONENT reg4 PORT ( clk, enr : IN std_logic; din : IN std_logic_vector(3 DOWNTO 0); q : OUT std_logic_vector(3 DOWNTO 0)); END COMPONENT;

COMPONENT count4 PORT( clk, enc, ld, rst : IN std_logic; din : IN std_logic_vector(3 downto 0); q : BUFFER std_logic_vector(3 downto 0)); END COMPONENT;

END ex6_pkg;

Exercise 6 Solution package.vhd (cont)

Exercise 6 SolutionTop Level File: ex6.vhdLIBRARY ieee;USE ieee.std_logic_1164.ALL;

ENTITY ex6 IS PORT ( load, clock, reset, enr : IN std_logic; data : IN std_logic_vector(3 DOWNTO 0); count : BUFFER std_logic_vector(3 DOWNTO 0));END ex6;

USE work.ex6_pkg.ALL; -- get access to your componentsARCHITECTURE ex6_arch OF ex6 IS

SIGNAL regout : std_logic_vector(3 DOWNTO 0); -- internal bus SIGNAL peqq : std_logic; -- internal net SIGNAL not_peqq : std_logic; -- internal net

Exercise 6 SolutionTop Level File: ex6.vhd (cont.)

BEGIN

U1: count4 PORT MAP (din=>data, ld=>load, enc=>not_peqq, clk=>clock, rst=>reset, q=>count);

U2: reg4 PORT MAP (din=>data, enr=>enr, clk=>clock, q=>regout);

U3: comp4 PORT MAP (p=>count, q=>regout, peqq=>peqq); not_peqq

------my hierarchy example 2008.4.28libraryieee;entity ab is port( in1, in2: in bit;y: out bit; re:out integer range 0 to 16);end entity ab;architecture myr of ab iscomponent mycounter -------port(clk, clear:in bit; c: out bit; qc: out integer range 0 to 16);end component;

beginad1: mycounter PORT MAP (clk=>in1, clear=>in2, c=>y, qc=>re);endmyr;-----------------------my counter component--------libraryieee;ENTITY mycounter isport(clk, clear:in bit; c: out bit;qc: out integer range 0 to 16);constant modulus: integer :=10;end mycounter;architecture a of mycounter is beginPROCESS (clk, clear) VARIABLEcnt: integer range 0 to 16; BEGIN IF (clear='0') THEN cnt:= 0;c

Miscellaneous Topics:Tri-State LogicENTITY test_three IS PORT(oe :IN std_logic;data :OUT std_logic_vector(0 to 7));END test_three;ARCHITECTURE archtest_three OF test_three ISBEGINPROCESS (oe)BEGINIF (oe='1') THENdata

Miscellaneous Topics: Bi-directional pinsENTITY ldcnt IS PORT (clk, ld, oe: IN std_logic;count: INOUT std_logic_vector(7 DOWNTO 0));END ldcnt; ARCHITECTURE archldcnt OF ldcnt ISSIGNAL int_count: std_logic_vector(7 DOWNTO 0); BEGIN -- first create an internal signalcnt: PROCESS (clk)BEGINIF rising_edge(clk) THENIF ld='1' THEN int_count

Miscellaneous Topics:Assigning a Dont Care To assign dont cares in VHDL, use a -. Note that X means unknown in VHDL and cannot be used for synthesis Warp uses explicit "dont care" conditions to produce optimal logic equationsIF (a = '1') AND (b = '1') THENy

The pin_numbers attributeGets attached to the entityUsed to map the external signals of an entity to the pins on the target deviceAllows the back-annotation of pin placements after synthesisMust be placed inside the entityENTITY counter IS PORT (clock, reset: IN std_logic;count: OUT std_logic_vector(3 DOWNTO 0));ATTRIBUTE pin_numbers OF counter:ENTITY IS"clock:13 reset:2" &" count(3):3 count(2):4 count(1):5 count(0):6";END counter;

Emphasize that the class will emphasize VHDL and hands-on exercises geared to VHDL design.

Emphasize that this is intended as an introductory class.

Emphasize that we will learn how to use the Warp tools so we can do the exercises.This was basically lifted from Chapter 1 of the book.Emphasize the pairing of entities and architectures. This is the minimum required to synthesize a design.after this foil you can mention that you will now go into detail regarding modes and typesYou may want to elaborate on BUFFER. Mention that its used a lot in counters. Exercise 4 has a good example of this. You may want to draw a picture.

Mention that bold-faced words in all VHDL code shown in this training indicate VHDL reserved words.

You may also want to mention here that VHDL is not case sensitive, e.g. SIGNAL, signal, and sIGNaL all look the same to VHDL.

Actually go through the TO and DOWNTO examples and mention that we used DOWNTO most often because most people are accustomed to looking at busses with the MSB on the left.

Mention that two dashes indicate the start of a comment. The VHDL analyzer/compiler will ignore everything right of the 2 dashes (to the end of the line)

Note how individual bits of a vector are referenced a(0) is read A sub zero and references the zeroth bit in the vector.The basic thing to get out of this slide is that std_logic and std_logic_vector are what you should be using.Warp wont distinguish between 0 and L (or 1 and H) for PLD synthesis.

We take every effort to synthesize code the same way it would simulate. However, not every simulatable construct is synthesizable or representable in hardware. This is where the concept of a synthesizable subset comes in. To address this problem, IEEE is working on defining the synthesizable subset which we will readily adopt.

We could have sat that 'U' is the same as '0' or a '-' and an 'X' is the same as a '-', but we did not because we didn't want to create backward compatibility problems once a standard is adopted.Note the library and use statements required to use the 1164 package.Emphasize that not all foils will show these two statements, but you have to have it to use std_logic and std_logic_vector.

Read Chapter 3 in the VHDL book for more information.Don't let this drag on too long. Just have them scratch the answer on a piece of paper or use notepad or the VHDL editor. We won't synthesize this.

There is a template in ex1.vhd if the students want to use the computer.talk about comments and case insensitivityMore from Chapter 3The NOT operator has higher precedence than any of the other boolean operators. The rest are (and, nand, xor, etc.) are of equal precedence so you just used parentheses where necessary.

That is, AND does not have precedence over OR as in boolean arithmetic.This is essentially a priority encoder. There is an example upcoming.The schematic is shown on page 169 of the book. The equation for j is as folows

j =a * w +/a * b * x +/a * /b * c * y +/a * /b * /c * d * z

so you can see the first condition in the when/else has priority. If a is high, j gets w, no matter what b, c, and d are equal to, but if a is low, then j gets x if b is high, independent of c and d.

You could explicitly use boolean equations if you did not want/need priority, eg.

j