1

SMD152 Digital Hardware Design with VHDL

Responsible for the course:Jonas Thor

Room: A2304Email: thor@sm.luth.se

2

Lecture outline

• What to do today!

• Course introduction» Goal and contents

» Examination

• Basics of combinational logic

3

Today…

• Register for the course - sign list

• From the list I will generate an email alias, smd152_list@sm.luth.se, where I will post various information

• If you do not read email you will miss important information about the course!

• You are encouraged to use the mail alias if you find bugs in labs, have questions etc.

4

Core courses in “datorteknik”

Computer org.and logic design

Digital electronics

Discrete mathematics(Boolean algebra)

Digital hardware Design with VHDL

VLSI design(new course

given this year)

Project in digital synthesis

Computerarchitecture

2nd year 3rd year

SMDxxx“Smaller project

course”

5

Course goals

• Give the student an understanding of functionally complex digital systems

• Give the student a fundamental competence in methods for design and implementation of digital systems

• Familiarize the student with synchronous digital design

6

Lectures

• Lectures focusing on:» Digital design» Implementation technologies» Register Transfer Level (RTL) design with VHDL» Synchronous design» Design methodologies» Programmable logic» etc...

• Lecture plan will be available at

http://www.sm.luth.se/csee/courses/smd/152

7

Course examination

• 5 “point” course» labs and assignments 2 points

» exam 3 points

• Grade determined by results on exam

• Some material covered in lectures is not available in the text books

• Slides will be available on course homepage

8

Teaching...

• There are relatively few lectures and you are supposed to pick up most of the material while working with the labs

• When you have questions you are encouraged to contact me personally or by email.

• Investigate alternate data sources other than me and the textbook

• I plan to put as much material as possible on the course web pages

9

Text books

• Two books sold as a bundle at Bokis – something like 1050 SEK

• Book supply will probably not last

• Suggestion: team up with a lab partner and share books

10

Labs

• Software available on Solaris machines. 30 licenses of NC VHDL, 15 licenses of Synplify and unlimited licenses available for Xilinx. Let me know if you experience any problems with the licenses

• Labs will consist of computer based design problems and various “theoretical” problems (assignments)

• Team up with a friend and to the labs/assignments in pairs

• Hardware will be available at a later date. You will be notified

11

Labs and assignments

• Lab 1 Tutorial, simple VHDL coding TBD

• Lab 2 ALU for MIPS TBD

• Lab 3 RS232 interface TBD

• Lab 4 PS/2 Keyboard TBD

• Lab 5 MIPS TBD

A set of theoretical exercises will be assigned with each lab. Lab work and assignment is due same date

In all labs, except lab 2, the XSB boards will be usedAll deadline are firm i.e. you must have a good reason why a lab is late. Also you must notify me in advance if a lab is late.

Deadline

12

Hardware – XSB-300E board

13

Key competence areas in design of embedded systems

• Digital design – what this course is all about

• Analog design

• Mixed mode design

• Software engineering and hardware/software co-design

• PCB design

14

Abstraction levels – Y-chart

System synthesis

Behavioral synthesis

Logic synthesis

Circuit synthesis

Processors, Memories

Registers, ALUs, MUXs

Gates, flip-flops

Transistors

Structural viewBehavioral view

System Level

RT Level

Logic Level

Geometric Level

Transistor layouts

Cells

Chips

Boards, MCMs

Physical view

15

Design example – a hardware implementation of the GCD algorithm

• Find the Greatest Common Divisor for two unsigned chars (1 byte)

• Algorithm flow chart and corresponding behavioral VHDL code

processvariable A, B, Swap : integer range 0 to 255;

beginA := A_in;B := B_in;if (A /= 0 and B /= 0) then

while (B /= 0) loopwhile (A >= B) loop

A := A-B;end loop;Swap := A; A := B; B := Swap;

end loop;else

A := 0;end if;Y <= A;

end process;

A=0 or B=0

B=0

A>=B

Swap(A, B)

NO

NO

NO

A=A-B

A=0

YES

End

YES

YES

Start GCD

16

Digital design?• How to we get from a high level specification to this

implementation?

If you can learn how to do this we have reached the main goal of this course

D Q

CompareA<B

1

0

D Q1

0

1

00

1

1

0

CompareB=0

1

0A[7:0]

Reset

B[7:0]

Load

Y[7:0]

Done

Clock

17

But... we have to start from the beginning with some

basic theory

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Basics of Combinational Logic

Covers chapter 1 in Lee + some extra material.

• Definition of combinational logic

• Truth tables

• Boolean algebra

• Logic gates and networks

• Synthesis using algebraic manipulation

• Karnaugh maps and minimization

• NAND-NOR networks

• Multilevel logic

• Logic devices

• Timing diagrams and hazards

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Combinational logic - definition

• Combinational means “memory-less”. The outputs of a combinational circuit only depends on its current inputs. Does not contain latches or flip-flops

• Feedback loops are not allowed in combinational logic!

• Very common for students that learn VHDL and logic design to forget these simple rules. When you design a sub-circuit you should know if it is supposed to be combinational or not.

• Sequential circuits to be covered in later lectures

20

Truth tables and logic symbols

0001111011100101110101100000

)´(NOR

)´(NANDXORORAND

yxyxxyyxyxyx

+⋅⊕+⋅

AND OR XOR NAND NOR

“Cheap” to implement in CMOS

& ≥1 =1 & ≥1

21

16 possible logic functions of two variables

1010101010101010111100110011001100011111000011110000101111111100000000001

0 15

21

14

21

13

1

12

21

11

2

10

21

9

21

8

21

7

21

6

2

5

21

4

1

3

21

2

21

1021

=⋅=

+==

+==

⊕=

+=

+=

⊕==

⋅==

⋅=

⋅=

=f

xxf

xxf

xf

xxf

xf

xxf

xxf

xxf

xxf

xf

xxf

xf

xxf

xxf

fxx

Number of possible logic functions of n variables

n22

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Boolean and switching algebra

• Boolean algebra is formal mathematical theory used to represent and manipulate regarding human reasoning (logic)

• Switching algebra is a special case of Boolean algebra can be represented by a sextuple [S, ·, +, ¯ , 0, 1]» S is the set of variables that can take values 0 or 1

» ·, +, ¯ are the logic operations AND, OR and NOT, respectively

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Switching algebra – Axioms

• Switching is based around a set of basic axioms

( ) ( )( ) ( )( ) ( )( ) ( )( ) ( ) 11001'5A001105A

000'4A1114A111'3A0003A

0 then ,1 If'2A1 then ,0 If2A0 then ,1 If'1A1 then ,0 If1A

=+=+=⋅=⋅=+=⋅=+=⋅

=====≠=≠

xxxxxxxx

Axiom Dual Axiom

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Switching algebra - Duality

• The principle of duality states that if each AND is changed to an OR, each OR to an AND, each 1 to 0 and each 0 to 1, the value of the expression remains the same

• For instance

( ) ( )0,1,,,,,1,0,,,,, 11 ⋅+=+⋅ nn xxfxxf KK

00 =⋅x 11=+xIf then holds as well

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Switching algebra – “Simple” theorems

( ) ( )( ) ( )( ) ( )( )( ) ( )( ) ( )( ) ( )( ) ( )( ) ( )( ) ( ) Combining´)()('10T´)()(10T

Absorption Covering,)('9T)(9TveDistributi)()()('8T)()()(8TeAssociativ)()('7T)()(7T

eCommutativ'6T6TComplement0´'5T1´5TInvolution´)´(4T

yIdempotenc'3T3TNull00'2T112TIdentity1'1T01T

xyxyxxyxyxxyxxxyxx

zyxzxyxzyxzxyxzyxzyxzyxzyx

xyyxxyyxxxxx

xxxxxxxx

xxxxxx

=+⋅+=⋅+⋅=+⋅=⋅+

⋅+=+⋅++=⋅+⋅⋅⋅=⋅⋅++=++

⋅=⋅+=+=⋅=+

==⋅=+=⋅=+=⋅=+

Theorem Dual Theorem Common Name

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Proof of Theorems

• To prove a theorem one must only use the fact derivable from the basic axioms and previsously proven theorems

• Some methods are» Perfect induction - show the theorems validity for all possible cases

» Truth table

» Venn diagram

• This has hopefully been covered in previous courses. But you will get some practice in the first assignment...

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Switching algebra – “Complex” theorems

( )( )( )( )( )( )( ) ( )[ ] ( )( ) ( ) ( ) ( )( ) ( ) ( )[ ] ( )[ ]nnn

nnn

nn

xxfxxxfxxxxfxxfxxxfxxxxf

xxxfxxxfyxyxyxyx

zxyxzyzxyxzxyxzyzxyx

yxyxxyxyxx

,,,1,,,0,,,'5T1expansionShannon ,,,0,,,1,,,T15

DeMorgan´s dGeneralize,,0,1,,,,,,1,0,,,,4T1´´)´('3T1

DeMorgan´s´´)´(3T1)´()()()´()('2T1

Consensus)´()()()´()(2T1)´(T11'

Absorption)´(1T1

212121

212121

2121

KKK

KKK

KK

+′⋅+=⋅′+⋅=

+⋅′′′=′⋅+

+=⋅⋅=+

+⋅+=+⋅+⋅+⋅+⋅=⋅+⋅+⋅

⋅=+⋅+=⋅+

Theorem Common Name

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Hardware Implementation of Switching Algebra

• Binary logic values ‘0’ and ‘1’ are (usually) represented as voltage levels

• Positive logic: ‘0’ Low voltage‘1’ High voltage

• Negative logic: ‘0’ High voltage‘1’ Low voltage

• Positive logic is most common and is what be assumed to be used furher on

• The trend is that voltage levels are getting lower - today 5V logic is uncommon

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Noise Margin – How much noise is allowed?• Example: 3.3 V CMOS voltage levels

Logic 1High

Logic 0Low

Unallowed

Logic 1High

Logic 0Low

Unallowed

VIH

InputOutput

VOH

VILVOL

VIH(min)

VIL(max)

VOH(min)

VOL(max)

Output Input

3.3V

2.4V

0.4V

0V

3.3V

2V

0.8V

0V

30

Logic gates

• Logic functions are graphically depicted with gates

• Note that the gate symbol is only illustrates the functionality -the implementation technology is not determined

AND

Inverter

OR

NAND

NOR

XOR

yx ⋅xy

xy

x

xy

xy

xy

yx +

´x

)´( yx ⋅

)´( yx +

´´ yxyxyx ⋅+⋅=⊕

31

NMOS and PMOS transistors “switches”

• Ideal models of MOSFET transistors - switches

NMOS transistor

V G

V D

V S = 0 V

V S = V DD

V D

V G

Closed switch whenV G = V DD

V D = 0 V

Open switch whenV G = 0 V

V D

Open switch whenV G = V DD

V D

V DD

Closed switch whenV G = 0 V

V D = V DD

V DD

PMOS transistor

32

CMOS – Pull-up and Pull-down Networks

• CMOS – Complementary Metal Oxide Semiconductor

• Virtually all large integrated circuits today are based on CMOS technology!

V f

V DD

Pull-down network

Pull-up network

V x 1

V x n

(PUN)

(PDN)

Only one network is “active” at the same time, that is

PDNPUN ff =

PMOS transistors

NMOS transistors

33

CMOS inverter

V f

V DD

V x

onoff

off on

1 0

0 1

f x

T 1

T 2 T 1 T 2

34

CMOS NAND gate

Vf

VDD

onon

onoff

01

0011

01

offoff

onoff

offon

f

offon

1110

offoffonon

Vx1

Vx2

T1 T2

T3

T4

x1 x2 T1 T2 T3 T4

35

CMOS NOR gate

V f

V DD

onon

onoff

0 1

0 0 1 1

0 1

off off

onoff

off on

f

off on

1 0 0 0

off off onon

V x 1

V x 2

T 1

T 2

T 3 T 4

x 1 x 2 T 1 T 2 T 3 T 4

36

CMOS AND gate – six transistors

V f

V DD

V x 1

V x 2

V DD

37

Complex CMOS gates

• PUN and PDN functions are complement functions, that is

• Assume we want to implement the function

• The PUN is given directly by fand the PDN is given by

PDNPUN ff ´=

321 ´´´ xxxf +=

( ) ( )321321´ xxxxxxf +=′′′+′=

V f

V DD

V x 1

V x 2

V x 3

38

Transistors are not ideal switches

• MOS transistors (and others as well) are not ideal switches.

• For instance a transistor has an on-resistance and a parasitic capacitance.

• The R and C will affect the dynamic behavior of the transistors causing delays.

Simple model of parasitic capacitance. Value of C is proportional to the dimensions of the gate

V DD

V x

C

V A

Voltage

time

V x V A

39

Fan-in

• Fan-in is the number of inputs to a gate.

• Impractical to have large fan-in since the speed and noise margin of circuits are affected negatively

• Practically this is solved by cascading several gates with a lower fan-in

V f

V DD

V x 2

V x 1

V x 3

V x k

PUN

40

Fan-out

• Fan-out is the number of other gates a specific gates drive

• The larger the fan-out is the slower the circuit will be, due to the larger load

• Buffering or replicating driving logic will speed up the circuit

x f To inputs of

n other inverters

for n = 1V f

for n =4 V f

V DD

Gnd

Time0

N 1

41

Buffers

• Buffers are use to drive large capacitive loads in order to improve timing. Buffers are built with relatively large transistors

V f

V DD

V x

x f

42

Tri-State Buffers

Equivalent circuit

Truth table

x f

e

A tri-state buffer

0 0 1 1

0 1 0 1

Z Z 0 1

f e x

x f

e = 0

e = 1x f

f x

e

Possible implementation

43

Synthesis using AND, OR and NOT gates

( )

111001110100, 2121 xxfxx

( ) 21212121, xxxxxxxxf ′′+′+=

f

Optimal?Optimal?

1x2x

Eeach occurrence of a variable is called a literal.

In this case we have six literals and three product terms

44

Optimizing using algebraic manipulation

( )

( ) ( )12

221112

21212121

21212121,

xxxxxxxxxxxxxxxx

xxxxxxxxf

′+=

′+′+′+=

′′+′+′+=

′′+′+=

Optimal?Optimal?

f x 2

x 1

In this case we have two literalsand two procuct terms

45

What is an optimal circuit?

• The answer depends on what you are optimizing for. Optimization criteria can be» Area

» Speed

» Power consumption

• Area and speed optimization has been the main objective of synthesis tools, but power optimization is becoming increasingly important

• When using Karnaugh maps we try to find the minimum number of literals – we call this the minimum cover

46

Minterms and maxterms

• Minterm – when the function evaluates to 1

• Maxterm – when the function evaluates to 0

ii Mm

xxxMxxxmxxxMxxxmxxxMxxxmxxxMxxxmxxxMxxxmxxxMxxxmxxxMxxxmxxxMxxxm

xxx

=

++==++==++==++==++==++==++==++==

01270127

01260126

01250125

01240124

01230123

01220122

01210121

01200120

012

111011101001110010100000

MaxtermMinterm

47

Design example with minterms – sum-of-products

11110011010110010110101011000000

012 fxxx

012012012012

7421

xxxxxxxxxxxxmmmmf

+′′+′′+′′=+++=

x2x1x0

f

POS –sum of products

Canonical SOP when all mintermsare included

48

Design example with maxterms – product-of-sums

11110011010110010110101011000000

012 fxxx

POS – product of sums

Canonical POS when all maxtermsare included

( ) ( )

( )( )( )( )012012012012

6530

6530

6530

6530

xxxxxxxxxxxxMMMM

mmmmmmmmff

mmmmf

+′+′′++′′+′+++==

′′′′=

′+++==′′

+++=′

x2x1x0

f

49

Shorthand notation for SOP and POS

( )∑=+++= 7,4,217421 ,mmmmmf

POS – product of sums

SOP – sum of products

( )∏== 6,5,3,06530 MMMMMf

50

Karnaugh maps

• Karnaugh maps may be used to graphically minimize logicfunctions with a limited set of variables

• Rows and columns are Gray coded

0 1 3 2

4 5 7 6

x2

x1x0

0

1

00 01 11 100 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

x3x2

x1x0

00

01

11

10

00 01 11 100 1

3 4

x1

x0

0

1

0 1

x0

x1

x2

x3

x0

x1

51

K-maps• Minterms should be chosen in groups that contain 1, 2, 4, 8, .... Elements

• Select the largest possible groups

01

11

31

21

40

50

70

60

120

130

151

140

81

90

110

101

x3x2

x1x0

00

01

11

10

00 01 11 100 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

x3x2 x1x0

1111000010100001

f

f = x´3x´2 + x´2 x´0 + x3x2 x1x0

x0

x1

x2

x3

52

Understanding Karnaugh maps

• The “key” is the combining property.Find the minterms that only differ inone variable

( ) 0120120120120126,5,4,2,0 xxxxxxxxxxxxxxxmf ′+′+′′+′′+′′′==∑

xyxyx =⋅+⋅ ´

( ) 021102 xxxxxx ′′=′+′′ ( ) 120012 xxxxxx ′=′+′

( ) 021102 xxxxxx ′=′+′

( ) 12012220120202 xxxxxxxxxxxxxxf ′+′=′+′+′=′+′+′′=

Note that we use one minterm twice but this is allowed sincemmm +=

53

Optimizing previous example with a K-map

x 1 x 0

0 0 0 1 1 0 1 1

1 0

0 1

0 0 0 0

0 0 0 1 1 0 1 1

1 1 1 1

1 1

0 1

x 2 f

( )∑= 6,5,4,2,0mf

213 xxxf ′+′=

01

1 3 21

41

51

7 61

x2

x1x0

0

1

00 01 11 10

54

Another example...

• In a 3-variable K-map it is possible to combine cells to produce product terms that corresponds to a single cell, two adjacent cells, a group of four adjacent cells or eight adjacentcells.

• The number of cells are always a power of two.

1202 xxxxf ′+′=

0 1 31

21

41

5 7 61

x2

x1x0

0

1

00 01 11 10

55

Prime implicants

• Implicants – all possible ”circles”

• Prime implicants – implicants that are not a subset of any other implicant

01

1 3 21

4 5 7 6

12 131

151

14

8 91

111

101

x3x2

x1x0

00

01

11

10

00 01 11 10

x0

x1

x2

x3

03012123013013023023023

15131110920

,,,,,,,,,,,,,,

xxxxxxxxxxxxxxxxxxxxxxxmmmmmmm

′′′′′′′′′

03012123023 ,,, xxxxxxxxxxx ′′′′′′

Prime implicantsare marked

56

Essential prime implicants

• Essential prime implicant – a prime implicant that contains a mintermthat is not part of another prime implicant

• Minimum cover

01

1 3 21

4 5 7 6

12 131

151

14

8 91

111

101

x3x2

x1x0

00

01

11

10

00 01 11 10

x0

x1

x2

x3

01203023

12303023 or xxxxxxxxxxxxxxxx′′++′′′

′++′′′

Essential primeimplicants aremarked

03023 , xxxxx ′′′

57

Summary: of Definition of terms

• Literal. Each appearance of a variable, complemented or not is called a literal.

• Implicant is a product term that indicates that a given function is equal to 1. For instance all minterms are implicants.

• Prime implicant. An implicant is called a prime implicant if it cannot be combined into another implicant with fewer variables. It is impossible to delete any variable in a prime implicant and still have a valid implicant.

• Essential prime implicant. A prime implicant that includes a minterm not covered in any other prime implicant is an essential prime implicant.

58

K-maps – finding minimum cover

1. Generate all prime implicants for a given function f.

2. Find the set of essential prime implicants.

3. If the set of essential prime covers all valuation for which f = 1, then this set is the desired cover of f. Otherwise, determine the nonessential prime implicants that should be added to form a complete minimum cost cover.• The choice of non-essential prime implicants to be included is governed

by the cost considerations. This choice is often not obvious and for large circuits there exist many possibilities. Often synthesis tools use heuristic approaches i.e. only a subset of the possibilities are considered but gives a good result most of the time.

59

Example 1 to illustrate terms

x 1 x 0 x 3 x 2 00 01 11 10

00

01

11

10

1 1

1 1

1

1 1

1

1

1

130102301212303 ,,,,, xxxxxxxxxxxxxxx ′′′′′′

6 prime implicants

2 essential prime implicants

0121303 xxxxxxxf ′′++′=

Minimum cover:

Seven literals three product terms

1303 , xxxx′

60

Example 2 to illustrate terms

x 1 x 0 x 3 x 2 00 01 11 10

00

01

11

10

1

1

1

11

1

1

1

01312312312302 ,,,, xxxxxxxxxxxxxx ′′′′

5 prime implicants

4 essential prime implicants

Minimum cover is the four essential prime implicants

61

Five variable K-map

• Lager K-maps are impractical. Instead we rely on CAD tools to do the optimizations.

• The purpose of introducing the K-map here is that it in a simple way illustrate the ideas involved in the minimization process.

x 1 x 0 x 3 x 2 00 01 11 10

1 1

1 1

1 1

00

01

11

10

x 1 x 0 x 3 x 2 00 01 11 10

1

1 1

1 1

1 1

00

01

11

10

x 4 1 = x 4 0 =

013412313 xxxxxxxxxf ′′′+′+′=

62

Minimization of POS forms

• Same procedure as for the SOP forms. But instead group the maxterms

• Invert the literals and OR them together

00

10

30

20

40

51

71

60

121

131

150

141

81

91

111

101

x3x2

x1x0

00

01

11

10

00 01 11 10

( )( )( )01230323 xxxxxxxxf ′+′+′+′++=

63

Incompletely specified functions• In a digital system it is often the case that certain input conditions can

never occur. These conditions are called don’t-care conditions• During minimization the don’t cares can be treated as 1 or 0, whichever is

more useful when trying to find a minimum cost implementation

( ) ( )15,11,7,310,9,8,5,1 Dmf +=∑Shorthand notation

00

11

3-

20

40

51

7-

60

120

130

15-

140

81

91

11-

101

x3x2

x1x0

00

01

11

10

00 01 11 100

01

13

-2

04

05

17

-6

012

013

015

-14

08

19

111

-10

1

x3x2

x1x0

00

01

11

10

00 01 11 10

SOP implementation POS implementation

64

Multiple output circuitsTwo functions f and g individually optimized

0 1 3 2

41

51

71

6

121

131

151

14

8 91

11 10

x3x2

x1x0

00

01

11

10

00 01 11 100 1 3 2

41

5 71

61

121

13 151

141

8 91

11 10

x3x2

x1x0

00

01

11

10

00 01 11 10

0130212 xxxxxxxf ′++′= 01231202 xxxxxxxxg ′′++′=

65

Multiple output circuitsSame two functions f and g optimized by finding common terms

0 1 3 2

41

51

71

6

121

131

151

14

8 91

11 10

x3x2

x1x0

00

01

11

10

00 01 11 100 1 3 2

41

5 71

61

121

13 151

141

8 91

11 10

x3x2

x1x0

00

01

11

10

00 01 11 10

012301212 xxxxxxxxxf ′′++′= 012301202 xxxxxxxxxg ′′++′=

Ver.1 Ver.22-input AND 4 23-input AND 1 14-input AND 1 13-input OR 2 2

66

NAND and NOR logic networks

x y

x

y

x

y

x y

x y

x y

´´)´( yxyx ⋅=+

´´)´( yxyx +=⋅

67

Using NAND gates to implement sum-of-products

CMOS n-input gates

AND: 2n + 2 transistorsOR: 2n + 2 transistorsNAND: 2n transistors NOR: 2n transistors

CMOS NAND and NOR gates arefaster and smaller than CMOS AND and OR gates

68

Using NOR gates to implement products-of-sums

69

Multilevel circuits – factoring example• Y = A D F + A E F + B D F + B E F + C D F + C E

F + G» Reduced sum-of-products form – already simplified

» 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)

» 25 wires (19 literals plus 6 internal wires)

• Y = (A + B + C) (D + E) F + G» Factored form – not written as two-level SOP

» 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate

» 10 wires (7 literals plus 3 internal wires)

70

Multilevel compared to two-level circuits

• The fan-in in of gates are reduced.

• Multilevel synthesis a much more complex than two level synthesis.

• Analysis of multilevel circuits is more difficult.

• Multilevel optimization is a research intensive subject and many optimization algorithms exist. Factoring is only one example...

71

Some combinational devices

• Multiplexer

• Demultiplexer

• Decoder

• Encoder

• Priority encoder

• Look-up table

72

Multiplexers and Demultiplexers

I0I1I2I3

Out

S[1:0]

I311I201I110I000

OutS(0)S(1)

4-1 MUX

S[1:0]

O0O1O2O3

In

000InO0

00In0

O1

0In00

O2

In11001010000

O3S(0)S(1)

1-4 DEMUX

A 2k-1 MUX routes one of the 2k data inputs to the output depending on the binary value of its k selectinputs

A 1-2k DEMUX routes the data input to one of the 2k outputs depending on the binary valueof its k select inputs

73

Decoders and Encoders

I0I1I2I3

O1

4-2 Encoder

O0O1O2O3

I1

0001

O0

0010

O1

0100

O2

111001010000

O3I0I1

2-4 Decoder

I0

One-hot encoding

O2

0100I3

1000I4

1100

O1

100000110001

O0I1I0

One-hot encodingBinaryencoding

Binaryencoding

74

Priority Encoder

I0I1I2I3

O1

4-2 Priority Encoder

O2

01xxI3

1xxxI4

1100

O1

1000001100x1

O0I1I0

One-hot encoding Binaryencoding

In this case I0 has the highest priority

75

Active-high and active-low inputs/outputs

10110100

001

En

1

100

O0

1

010

O1

1

110

O2

011

0101000xx

O30I1

2-4 Decoder

En

O0O1O2O3

I1I0Inputs Outputs

O0O1O2O3En

I1I0

76

MUXes as universal logic devices• A 2k – 1 MUX can implement (k+1) variable expressions

x1 x0

0 0 0 1 1 0 1 1

1 0

0 1

0 0 0 0

0 0 0 1 1 0 1 1

1 1 1 1

1 1

0 1

x2 f x1 x0

0 0 0 1 1 0 1 1

1 0

0 1

1 1

0 1

f, x2=0 f, x2=1

1 x2

0 1

f (x2)

x1 x0

1

01x2 f

77

Look-Up Tables - LUTs

• LUTs are essentially small RAMs• Stores a ”truth-table”• Commonly found in Field Programmable Gate Arrays• A k-input LUT kan implement any function of k variables – how many

functions are there?

f4-LUT

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

x3x2 x1x0

1111000010100001

f

x3x2 x1x0

78

Optimizing for LUTs with K-maps

• Karnaugh’s method is not suited for LUT optimization

010212 xxxxxxf ′+′+′′=

01

11

3 21

4 51

71

61

x2

x1x0

0

1

00 01 11 10

2-LUTx´2x´1

2-LUTx2x´0

2-LUTx1x´0

2-LUT2-LUT

f

79

Optimizing for LUTs with K-maps

• Better...

01011212 xxxxxxxxf ′+′++′′=

01

11

3 21

4 51

71

61

x2

x1x0

0

1

00 01 11 10

2-LUTx2x1

2-LUTx2x0

2-LUTf

1212 xxxx +′′

0101 xxxx ′+′

80

Which is the best implementation?

... assuming you have standard cell gate library4 input LUTs

81

Timing for combinational nets

x 1

x 2

f

A

B

1 0

1 0

1 0

1 0

1 0

x 1

x 2

A

B

f

Time (ns)

Timing diagram

0 1 2 3 4 5 6 7 8

1 ns2 ns

2 ns

82

Hazards cause glitches

Static Hazard Dynamic Hazard

83

Hazard free circuit

add“consensus”

term

84

Do we have to worry about hazards?

• A circuit should be designed so either is true:» Hazards are avoided

» Hazards are tolerated

• We will work with synchronous sequential designs wherehazards are tolerated – given that the timing are met

• Sequential synchronous design to be covered later