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Digital Design with VHDL

Presented by: Amir Masoud Gharehbaghi

Email: amgh@mehr.sharif.edu

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Design Hierarchy

Design Specification & Requirement

Behavioral Design

Register Transfer Level (RTL) Design

Logic Design

Circuit Design

Physical Design

Manufacturing

Circuit Design

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Design Automation (DA)

Automatic doing task in design process:

Transforming one form of design to another

Verifying functionality and timing of design

Generating test sequence for design validation

Documentation

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Hardware Description Languages

(HDLs)Describing Hardware for:

Design & Modeling

Simulation

Synthesis

Testing

Documentation

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VHDL History

Initiated with VHSIC project in 1981 by DoD VHSIC: Very High Speed Integrated Circuits

In 1983 DoD established requirements forVHSIC HDL (VHDL)

In 1987 VHDL became an IEEE standard:

VHDL 1076-1987In 1993 a new version of VHDL released:

VHDL 1076-1993

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VHDL Specifications

Designing in Various Levels of Abstraction: fromBehavioral to Gate Level

Support for Design Hierarchy (Structural Design)Library Support

Support of Generic Design

Timing Control

Concurrent & Sequential Statements

Type Declaration

..

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Components in VHDL

Each Component in VHDL is described as an

ENTITY-ARCHITECTUREpair

ENTITYpart describes the interface ofcomponent

ARCHITECTUREpart describes the functionality

and timing of componentAn ENTITYmay have differentARCHITECTURES,

describing the component at various levels and with

different details of timing and functionality

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ENTITY Declaration

ENTITY entity_name IS

generic clause

port clauseEND ENTITY entity_name ;

ENTITY and3 ISGENERIC (delay: TIME := 5 ns);

PORT (a, b, c : IN BIT; z : OUT BIT);

END and3;

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Ports

Ports are Component Interface Signals

Each Port has: Name Mode

IN : Input signals

OUT : Output Signals

INOUT : Bidirectional Signals

BUFFER : Like OUT from outside the component &INOUT from Inside it

Type

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Standard Types

Standard Package Types:

BIT

BIT_VECTOR BOOLEAN

INTEGER

REAL

TIME

CHARACTER

STRING

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ARCHITECTURE Declaration

ARCHITECTURE arch_name OF entity_name IS

architecture declarative part

BEGINconcurrent statements

END ARCHITECTURE arch_name ;

ARCHITECTURE single_delay OF and3 ISBEGIN

z

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Concurrent Statements

Concurrent Signal Assignment

Component Instantiation Statement

Generate Statement

Process Statement

Block StatementConcurrent Procedure Call Statement

Concurrent Assert Statement

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Concurrent Signal Assignment

Conditional Signal Assignment Statement

Selected Signal Assignment Statement

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Conditional Signal Assignment

target

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Conditional Signal Assignment

Examplesa

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2 Input NAND Gate

ENTITY nand2 IS

PORT (a, b: IN BIT; z: OUT BIT);

END nand2;

ARCHITECTURE no_delay OF nand2 IS

BEGINz

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3 Input NAND Gate

ENTITY nand3 IS

PORT (a, b, c: IN BIT; z: OUT BIT);

END nand3;

ARCHITECTURE no_delay OF nand3 IS

BEGINz

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2:1 MUX

ENTITY Mux2x1 IS

PORT (a0, a1, sel: IN BIT; z: OUT BIT);

END Mux2x1;

ARCHITECTURE conditional OF Mux2x1 IS

BEGINz

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VHDL Operators

Logical AND , NAND , OR , NOR , XOR , XNOR

Relational = , /= , < , , >=

Shift SLL , SRL , SLA , SRA , ROL , ROR

Adding + , - , &

Sign+ , -

Multiplying * , / , MOD , REM

Miscellaneous ABS , **

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Selected Signal Assignment

WITH expression SELECT

target

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2:1 MUX

ARCHITECTURE selected OF Mux2x1 IS

BEGIN

WITH sel SELECT

z

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Component Instantiation Statement

label: instantiated_unit

[ GENERIC MAP (association_list) ]

[ PORT MAP (association_list) ] ;

instantiated_unit ::=

[COMPONENT] component_name

| ENTITY entity_name [ (architecture_name) ]| CONFIGURATION configuration_name

association_list ::= association_element { , association_element }

association_element ::= [ formal_part => ] actual_part

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4:1 MUX (using entity)

ENTITY Mux4x1 IS

PORT (a : IN BIT_VECTOR(3 DOWNTO 0); sel: IN BIT_VECTOR(0 TO 1) ;

z: OUT BIT);

END Mux4x1;

ARCHITECTURE mux2x1_based OF Mux4x1 IS

SIGNAL im0, im1 : BIT;

BEGINm1: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(0), a(1), sel(0), im0);

m2: ENTITY WORK.Mux2x1(conditional) PORT MAP (a(2), a(3), sel(0), im1);

m3: ENTITY WORK.Mux2x1(selected) PORT MAP (im0, im1, sel(1), z);

END mux2x1_based;

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4:1 MUX (using component)

ARCHITECTURE comp_based OF Mux4x1 IS

SIGNAL im0, im1 : BIT;

COMPONENT mux2 PORT (a0, a1, sel: IN BIT; z: OUT BIT);END COMPONENT;

FOR ALL: mux2 USE ENTITY WORK.Mux2x1(conditional);

BEGIN

m1: mux2 PORT MAP (a(0), a(1), sel(0), im0);

m2: mux2 PORT MAP (a(2), a(3), sel(0), im1);

m3: mux2 PORT MAP (a0 =>im0, a1 =>im1, sel =>sel(1), z => z);

END comp_based;

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4:1 MUX (another binding)

ARCHITECTURE another OF Mux4x1 IS

SIGNAL im0, im1 : BIT;

COMPONENT mux2 PORT (a0, a1, sel: IN BIT; z: OUT BIT);

END COMPONENT;

FOR m1, m2: mux2 USE ENTITY WORK.Mux2x1(conditional);

FOR OTHERS: mux2 USE ENTITY WORK.Mux2x1(selected);

BEGINm1: mux2 PORT MAP (a(0), a(1), sel(0), im0);

m2: mux2 PORT MAP (a(2), a(3), sel(0), im1);

m3: mux2 PORT MAP (a0 =>im0, a1 =>im1, sel =>sel(1), z => z);

END another;

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Testing the Mux4x1

ENTITY test_mux4x1 IS END test_mux4x1;ARCHITECTURE test1 OF test_mux4x1 IS

SIGNAL inp: BIT_VECTOR(3 DOWNTO 0);

SIGNAL sel: BIT_VECTOR(1 DOWNTO 0);SIGNAL outp: BIT;

BEGIN

comp: ENTITY Mux4x1(another) PORT MAP (inp, sel, outp);

inp