Low Power 3 Value Logic 9T SRAM Cell Design based on ...

Low Power 3 Value Logic 9T SRAM CellDesign based on CNTFET at 18nm

Technology

S.Tamil Selvan1, Dr. M.Sundararajan2,1Research scholar, 2Dean-Research

1,2Bharath Institute of Higher Education& Research Chennai, Tamil Nadu

[email protected]@gmail.com

December 10, 2018

Abstract

This paper proposes a new design of highly stable andlow power SRAM cell using carbon nanotube FETs (CNT-FETs) at 18nm technology node. As device physical gatelength is reduced to below 65 nm, device non-idealities suchas large parameter variations and exponential increase inleakage current make the I-V characteristics substantiallydifferent from traditional MOSFETs and become a seriousobstacle to scale devices. CNFETs have received widespreadattention as one of the promising successor to MOSFETs.The proposed circuit was simulated in HSPICE using 18nmStanford CNFET model. Analysis of the results shows thatthe proposed CNTFET based 3VL 9T SRAM cell, powerdissipation, and stability substantially improved comparedwith the conventional CMOS 6T SRAM cell by 51% and58% respectively at the expense of 4% write delay increase.Key Words::SRAM, 3 VL, CNTFET, CMOS, low power,highly stable.

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International Journal of Pure and Applied MathematicsVolume 120 No. 6 2018, 101-114ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

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1 INTRODUCTION

For the foreseeable feature, static random access memory (SRAM)will likely remain as the embedded memory technology of choicefor many microprocessors and systems on chips (SoCs) due to thespeed advantage and compatibility with standard logic processes.With the advent of SoC, the design of highly stable and power ef-ficient SRAM structures has become highly desirable. Therefore,it is essential to develop a low power SRAM design technique forthe new device technology such as CNTFET. Carbon NanotubeField Effect Transistor (CNFET) is the most promising technologyto extend or complement the traditional silicon technology due tothe following three reasons: First, the operation principle and thedevice structure are similar to CMOS devices, and the establishedCMOS design infrastructure can be utilised. Second, the CMOSfabrication process can still be utilised. And the most importantreason is that CNFET has the best experimentally demonstrateddevice current carrying capability so far. Several researches havebeen done to estimate the performance of CNFET at a single devicelevel in the presence of process related non-idealities and imperfec-tions at the 18 nm technology node using compact CNFET SPICEmodel [1][2]. In this paper, as a circuit level design of CNTFET,a novel low power and highly stable 3 VL 9T SRAM cell designis proposed and its performance and viability are demonstrated byperforming various simulations. The stability and power consump-tion of the 9T SRAM cell based on CNTFET are compared withthat of the conventional CMOS 6T SRAM cell design to show theviability of the CNTFET based SRAM cell design. The circuitsimulation in this paper uses a 18nm CNFET HSPICE model thatincludes the practical device non-idealities for CNFET [3][4] and the18nm BSIM PTM (predictive technology model) for Si MOSFET[5]. This paper is organised in the following manner: The charac-teristics and physical features of CNTFET Transistor are explainedin section II, section III describes the 3value logic and section IVdescribes, the mechanisms of the read and write operations of theproposed 9T CNTFET SRAM cell and the schemes for deciding thenumber of nanotubes of each. The simulation results are presentedin section IV to compare the performance and viability of the CNT-FET technology with that CMOS technology, and followed by the

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conclusion in Section V.

2 CNTFET TRANSISTOR

Carbon nanotube Field Effect transistors (CNTFETs) utilise semi-conducting single-wall CNTs to assemble electronic devices; CNT-FETs have been shown to have similar properties to MOSFETs. Asingle-wall carbon nanotube (or SWCNT) consists of only one cylin-der, and the simple manufacturing process of this device makes ita very promising alternative to todays MOSFET. An SWCNT canact as either a conductor or a semiconductor depending on the an-gle of the atom arrangement along the tube. This is referred toas the chirality vector and is represented by the integer pair (n,m) [6]. A simple method to determine if a carbon nanotube ismetallic or semiconducting is based on considering the indices (n,m), i.e. the nanotube is metallic if n =m or n-m=3i where i isan integer. Otherwise, the tube is semiconducting. The diameterof the CNT can be calculated from [6] as a function of m and n.Fig. 1 shows the schematic diagram of the CNTFET [6]. Similar tothe silicon device the CNTFET has four terminals, a dielectric filmis wrapped around a portion of the undoped semiconducting nan-otube, and a metal gate surrounds the dielectric. Fig. 2 shows theequivalent circuit model implemented in HSPICE as proposed in [6].Heavily doped CNT segments are placed between the gate and thesource/drain to allow for a low series resistance during the on-state[7]. As the gate potential increases, the device is electrostatic-allyturned on or off via the gate. The current-voltage (I-V) character-istics of the CNTFET are shown in Fig. 3, and they are similarto those of MOSFET. The CNTFET device current is saturatedat higher Vds (drain to source voltage) as channel length increasesas shown in Fig. 3, and the on-current decreases due to energyoptimisation in the axial

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Fig. 1 Schematic diagram of a carbon nanotube transistor(CNTFET): (a) sectional view; (b) top view

Fig. 2 Equivalent circuit model for the intrinsic channel region ofa CNTFET [6]

3 THREE VALUE LOGIC DESIGN

A three-value logic system was first developed by Jan Lukasiewicz,in 1920, in its popular paper O Logice Trojwarkoscioewj, [12], asabstraction of the traditional binary logic. Three-value logic systemhas better characteristic compared to previous binary system suchas increased bit handling capability per unit area, reduced num-ber and complexity of interconnections, as well as reduced number

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of active FETs inside a chip. Hence, in the circuit which designsbase on three-valued logic, circuits will be simpler and more flex-ible also more easy. By using 3VL higher speed and less powerdissipation will be achieved [13] [14]. To obtain 3value logic systemwe need three values, in conventional binary system we have twologics values 0 and 1, these logics represented by 0V and Vdd re-spectively. By supplementing one state between these two logics ofconventional binary system ternary logic system can be achieved.In 3value logic system values represented by 0V, Vdd/2 and Vddwhich denote 0, 1 and 2 respectively. In principle, 3VL can providea means of increasing data processing capability per unit chip area.The serial and serial-parallel arithmetic functions can be carriedout faster if the 3value logic is employed. One of the main merits of3value logic is that it reduces the number of required computationsteps. As each input can have three distinct values, the number ofdigits required in a 3VL family is log32 times less than that requiredin binary logic. It is assumed that 3value logic elements can oper-ate at a speed approaching that of the corresponding binary-logicelements. However, if the 3VL and binary logic gates are used totake advantage of their respective merits, performance could be sig-nificantly improved because 3value logic gates are good candidatefor decoding block since it requires less number of gates while bi-nary logic gates are a good candidate for fast computation modules.Thus, 3value design technique combined with the conventional bi-nary logic gate design technique also provides an excellent speedand power consumption characteristics in memory circuits. Threevalue logic functions are defined as the functions having convincingif a third value is introduced in to the binary logic. Here, 0, 1, and 2denote the 3 logic values to represent true, intermediate, and false,respectively. Any n-variable Z1 ,. . .,Zn 3 value logic function f(Z)is defined as a logic function mapping 0,1,2 n to 0,1,2, where Z =Z1 ,. . .,Zn. The basic operations of 3value logic can be defined asfollows, whereZi,Zj 0,1,2Zi — Zj = maxZi,ZjZi & Zj = minZi,ZjZi = 2 Ziwhere denotes the arithmetic subtraction, the operations—, , and are referred to as the OR, AND, and NOT in 3value

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logic, respectively. The 3 value logic gates are designed accordingto the convention defined in above equation. Here work the set 0,1, 2 is used, where 0 = false, 1= intermediate, and 2 = true. Table1 shows the truth table of all the basic 3Value logic gates. Thechoice of these values leads in a more natural way the adaptationof the ideas from the binary logic

4 PROPOSED 9T CNTFET SRAM CELL

A new 3 VL 9T CNTFET SRAM cell structure is proposed in thispaper to increase SNM and to reduce the power consumption ofthe SRAM cell. A. Write and Read Operations The write and readbits are separated in this new 9T CNTFET SRAM cell. While intraditional 6T CMOS SRAM both bit and bit-bar lines are usedfor writing data, but in this newly proposed 9T CNTFET SRAMcell only Write Bit is used to write both 0 and 1 data, as shownin fig. 4. The writing operation starts by disconnecting the feed-back loop of the two inverters. By setting W bar signal to 0, thefeedback loop is disconnected. The data that is going to be writtenis determined by the Write Bit voltage. If the feedback connectionis disconnected, SRAM cell has just two back-to-back connectedinverters. Write Bit transfers the complementary of the input datato Q2, which drives the other inverter (M1 and M2) to developQ bar. Write Bit have to be pre-charged ”high” before and rightafter each write operation. When writing ”0” data at Q2, negligiblewriting power is consumed because there is no discharging activityat Write Bit. To write 1 data at Q2, the Write Bit have to be dis-charged to ground level just like 6T CMOS SRAM cell. In this case,the dynamic power consumed by the discharging is the same as 6TCMOS SRAM. The write circuit does not discharge for every writeoperation but discharges only when the cell writes 1 data, and theactivity factor of the discharging Write Bit is less than ”1”, whichmakes the proposed 9T CNTFET SRAM cell more power effectiveduring writing operation compared with the conventional CMOSSRAM cell

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Fig. 3 Current-voltage (I-V) characteristics of a ballistic CNTFET

The first step in the read operation is the pre-charging of all theRead Bit lines. During read operation, transistor M7 is turned onby setting W bar signal high and the Read Row (RD) high to turnon M8 and M9. When Q2=”0”, the M6 is turned off making theRead Bit voltage not change from the pre-charged value, whichmeans the cell data Q2 holds 0. On the other hand, if Q2 is 1,the transistors M6, M8 and M9 are turned on. In this case, dueto charge sharing, the Read- Bit voltage will be dropped about100 200mV and this voltage drop is enough to be detected in thesense amplifier.B. CNTFET configurationWhen writing 0, Write Bit is pre-charged high (VDD) and M7 isturned off. The node voltage at Q1 is less than VDD due to thethreshold voltage drop between the gate and source of the transis-tor M5. To compensate this voltage drop, the transistor M3 andM4 must be designed as a low-skew inverter to guarantee that Q2 isat a solid ground level to represent 0 state. A low-skewed inverterhas a weaker PMOS transistor. If the PMOS CNTFET has onlyone tube, the current can be minimised. On the other hand, theoperation of writing 1 is stable because NMOS transistor M5 canpass 0 faithfully. Assume that initially the cell stores 0 at Q2 and1 at Q bar after WL (Word Line) is deactivated and W bar is acti-vated. In this case, the voltage at Q1 is less than VDD due to thethreshold voltage drop across the gate and source of the transistor

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M7. The degraded voltage at Q1 may turn on the transistor M4slightly causing short circuit current through transistors M4 andM3. To overcome this problem, the low skewed inverter (M3 andM4) mentions for writing 0 case is justified again and the Vth ofthe transistor M7 needs to be controlled low to reduce the voltagedifference between Q bar and Q1.

Fig. 4 The proposed 9T CNTFET SRAM Cell structure

a low skewed inverter with transistors M3 and M4, to have a solidground level at Q2. However, by increasing the number of tubes,the M4 and M3 area sizes can be same. That is, if M4 has only onetube and M3 has 2 tubes, then the current ratio M3/M4 can bemore than 2. This means that the inverter transistor sizes M3/M4can be smaller than 2 by controlling the number of tubes. Transis-tor ratio M5/M4 of 1.3, M1/ M4 of 3, and low Vth of the transistorM7 guarantees a stable READ operation when Q bar stores ”0”.However, if the similar approach to M3/M4 sizing is used to opti-mise transistor ratios among M1, M5 and M4, the transistor sizescan be further reduced. If M5 has only one tube, M1 has two tubesand M4 has one tube, the transistor M1 needs to be only 1.5 timeslarger than transistor M4 to satisfy the relationships among M1,M5, and M4.

5 SIMULATION RESULTS

using bulk CMOS and CNTFET transistors respectively. HSPICEsimulations are performed at 18nm technology node using the Stan-ford CNTFET model and the Predictive Technology Model ( PTM)to compare the performance of the 3VL 9T CNTFET and 6T

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CMOS SRAM cells.A. Simulation SetupThe following technology parameters are used for simulation of3VL 9T SRAM cell using CNTFET Technology: Lch (physicalchannel length) = 18.0nm, Lss (the length of the doped CNTdrain-side/sourceside extension region) = 18.0nm, Efi (Fermi levelof the doped S/D tube) = 0.6 eV, Tox (The thickness of high-ktop gate dielectric material) = 4.0nm, (n1, n2) (chirality of tube)= (19,0), pitch = 10nm, Vfbn and Vfbp (Flatband voltage forn-CNTFET and p-CNTFET) = 0.0eV and 0.0eV, physical gatelength = 18.0nm, Lgeff (the mean free path in intrinsic CNT chan-nel region due to non-ideal elastic scattering) = source/drain ex-tension region) = 18.0nm, the mean free path in p+/n+ dopedCNT = 15.0nm, the work function of Source/Drain metal contact= 4.6eV, and CNT work function = 4.5eV. The minimum transis-tor sizes used for CMOS and CNTFET technologies are W=48nmand L = 18nm for bulk CMOS, and L=18nm and the number oftubes =1 for CNTFET. A Power supply of 0.9 V is used [8]. Table1 shows the summarised results to compare the proposed 3VL 9TCNTFET SRAM characteristics with the conventional CMOS 6TSRAM cell. B. Dynamic Power Consumption The newly proposed3VL 9T CNTFET SRAM cell achieves 51% writing power savingwhile maintaining the cell performance, read/write delay, and sta-bility of the conventional cell. The power saving comes from the factthat the cell keeps Write Bit ”high” instead of discharging whenit writes ”0”, which reduces the activity factor of the Write Bit.

TABLE I SUMMARISED SIMULATION RESULTS

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Fig. 5 The Dynamic Power Consumption with VDD variation

While conventional 6T CMOS SRAM always discharges one of thebit lines to write a data into the cell, the proposed 9T CNTFETSRAM discharges the Write Bit only when it writes 1. As theprobability of writing 0 gets higher, the power dissipation due tothe bit line discharging is reduced comparing to the conventionalcase. Fig. 5 shows the dynamic power consumption of the CNT-FET 9T SRAM cell for different VDD. As shown in the Fig. 5, thepower saving of the 9T CNTFET SRAM cell becomes greater as VDD increases since the dynamic power difference between the 6TCMOS SRAM and the proposed 9T CNTFET SRAM cell increasesexponentially as VDD increases.C. Leakage Power Consumptionthe leakage power of the 6T CMOS SRAM cell and 3VL9T CNT-FET SRAM cell. In the 3VL9T CNTFET SRAM cell, the bit lineleakage is significantly reduced by adding a NMOS transistor (M9),because of the socalled stack effect between M8 and M9. The re-duced bit-line leakage makes it possible to have more SRAM cellson a bit-line for high-density SRAM designs. 9T CNTFET SRAMcell, the bit-line leakage is significantly reduced by adding a NMOStransistor (M9), because of the so-called stack effect between M8and M9. The reduced bit-line leakage makes it possible to havemore SRAM cells on a bit-line for high-density SRAM designs.D. Static Noise MarginStatic Noise Margin (SNM) is the standard metric to measure thestability in SRAM bit-cells. The SNM of SRAM cell is defined asthe minimum DC noise voltage necessary to flip the state of thecell. The voltage transfer curves (VTCs) of the back-to-back in-verters in a bit-cell are used to measure SNM. Separating the Read

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and Write bit offers wider SNM during read operation as shownin Fig. 7. When reading the stored data, only Read Bit affectsinverter1 (M1/M2) output voltage. Consequently, this fact makesthe cell hard to flip. Table 1 shows 9T CNTFET SRAM cell hasthe highest SNM because of the relatively higher Vth and lowerleakage current than CMOS based SRAM cells.E. Write and Read DelayFor write operation, the write delay is defined as the time from the50% activation of the WL to the time when Q bar becomes 90% ofits full swing. The write delay is approximately equal to the prop-agation delay of the inverter2 (M3/M4) and inverter1 (M1/M2).Because the inverter1 is only driving the diffusion capacitor of M7,it is desirable to reduce the input capacitance of the inverter1 asmuch as possible to reduce the load capacitance on inverter2. Theproposed 3VL 9T CNTFET SRAM cell is slightly slower than 6TSRAM in writing operation because of this reason. The read timedepends on the READ paths transistors sizes. The proposed 3VL9T CNTFET SRAM cell READ delay is almost same as the con-ventional 6T CMOS SRAM cell since the transistor sizes are verysimilar. The READ access time at the cell level is determined bythe time taken for the bit-lines to develop a potential difference ofat least 100mV.

6 CONCLUSION

This paper has investigated the use of MOSFET-like CNTFET inplace of the conventional CMOS in the design of SRAM cell. Thisnew 9T CNTFET SRAM cell is compared with CMOS based 6TSRAM cell. This new 3VL 9T CNTFET SRAM cell cuts off thefeedback connection between the two back-to-back inverters in theSRAM cell when data is written and separates the write and readport with 9 transistors. Compared to 6T SRAM structure, the pro-posed 3VL 9T CNTFET SRAM saves power up to 5158% higherSNM during read operation at the minimal cost of 4% delay in-crease. These Simulation results show that the CNTFET based9T SRAM cell design achieves improvements in stability and powerconsumption, especially at a low power supply.

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References

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