LOW POWER VLSI DEGISN

•PHYSICS OF POWER DISSIPATION IN CMOS DEVICES

•LOW POWER ARITHMETIC COMPONENTS

Presented by:NAVEEN TOKASM.Tech-ECE1st Sem

Physics of power dissipation in CMOS devices

Power dissipation is defined as the measure of rate at which the energy is dissipated or lost from an electrical system. When an electric current works on a conductor , the internal energy of that conductor increases causing its temperature to rise above the surrounding temperature. This causes energy to dissipate away from the conductor into the surrounding through the process of heat transfer.

Need to estimate power dissipation:The below factors should be considered for estimating power dissipation

Performance Reliability Packaging Cost Portability

Where does power go in CMOS

The various types of power dissipations are:

Dynamic power dissipation Short circuit power dissipation Leakage current

MIS Structure

Energy Bands in an unbiased MIS diode

In this we have sandwiched a layer of thickness d of insulating material between a metal plate and the semi-conductor. Here we have assumed the semiconductor to be of P-type

In an ideal MIS diode, the insulator has an infinite resistance and does not have either the mobile charge carriers or charge centers.

The Fermi levels in the metal line up with the Fermi level in the semiconductor.

The level in the metal itself is same throughout.

This is called the Flat-Band condition

Energy Bands when the negative voltage is applied

When the voltage V is negative, the holes in the P-Type semiconductor are attracted to and accumulate at the semi-conductor surface in contact with the insulator.

This is called as Accumulation.

In the absence of the current flow, the carriers in the semi-conductor are in the state of equilibrium and the Fermi level appears as a straight line.

The intrinsic Fermi level has a higher value at the surface than at a point deep in the substrate and the energy levels Ec , Ev and Ei bend upward near the surface.

The Fermi Level Ef in the semiconductor is now -qV below the Fermi level in the metal gate.

Energy Bands when a small positive voltage is applied

When the applied voltage V is positive but small, the holes in the P-Type semiconductor are repelled away from the surface and leave negatively charged acceptor ions behind.

A depletion region, extending from the surface into the semiconductor is created .

This is the depletion condition. Besides repelling the holes, the positive

voltage on the gate attracts electrons in the semiconductor to the surface.

The surface is said to have begun to get inverted form original P-Type to N-Type.

While V is small , the concentration of holes is still larger than the concentration of electrons.

This is the weak inversion condition. The bands at this stage bend

downward near the suface.

Energy bands in strong inversion

If the applied voltage is increased sufficiently, the bands bend far enough that level Ei at the surface crosses over to the other side of level Ef.

It is brought about by the tendency of carriers to occupy states with the lowest total energy.

The kinetic energy of the electrons is zero when they occupy a state at the bottom edge of the conduction band.

In the present condition of inversion level Ei bends to be closer to level Ec.

The electron density at the surface is still smaller than the hole density deep inside the semiconductor.

When V is increased to the extent that the electron density at the surface ‘ns’ becomes greater than the hole density in the bulk, onset of strong inversion is said to take place.

Low Power Arithmetic components

Minimizing the power consumption of circuits is important for a wide variety of applications because of the increasing levels of integration and the desire for portability. Since performance is often limited by the arithmetic components speed, it is also important to maximize the speed.

The compromise between these two conflicting demands of low power dissipation and high speed can be accomplished by selecting the optimum circuit architecture.

An important attribute of arithmetic circuits for most applications is maximizing speed (for general purpose applications) or throughput (for signal processing applications).

For a growing number of applications, minimizing the power consumption is also of great importance.

The most direct way to reduce the power is to use CMOS circuits, which generally dissipate less power.

For CMOS, the use of adders with minimum power consumption is attractive to increase battery life to avoid local areas of high power dissipation.

There are four factors which influence the power dissipation of CMOS circuits:

Technology Circuit design style Architecture Algorithm

Circuit Design Style There are a number of CMOS circuit

design styles, both static and dynamic in nature.

The full Adder is the basis for almost every arithmetic unit, therefore any investigation into the suitability of circuit design style for use in arithmetic units must focus on the design of full adder.

Static CMOS Full Adder

The above figure shows a full adder designed using static complementary MOS logic employing both P and N type logic.

The P- Logic tree(upper half of the circuit) allows the output to be charged high, while the N-tree (lower half of the circuit) allows the output to be discharged to ground.

Both the complemented and un-complemented inputs are required and both the ‘sum’ and ‘carry’ and the ‘complemented sum and carry’ are produced.

The sum and carry functions are computed independently of each other.

Full Adders constructed using NO RAce dynamic CMOS logic(NORA) employ alternating stages of P and N type logic to form carry and sum outputs.

NO Race dynamic CMOS logic (NORA) Full Adder

NO Race dynamic CMOS logic (NORA) Full Adder

The P-Type stage that forms the carry output is dynamically pre-charged high while the N-Type transistor that computes the sum output is dynamically pre-discharged low.

This pre-charging and pre-discharging process requires a two-phase complimentary clock.

NORA logic is unique because it doesn’t require complemented inputs and doesn’t compute both complemented and un-complemented outputs.

Cascode Voltage Switch Logic (CVSL) Full Adder

Cascode Voltage Switch logic (CVSL) Full Adder

Cascode Voltage Switch Logic (CVSL) is a dynamic logic family. It requires a two-phase clock.

The complement of the clock signal is not necessary unlike NORA.

In CVSL Full Adder circuit , the outputs and their complements are all pre-charged high while the clock is low.

The complementary cascoded differential N-Type transistor trees pull either the output or its complement low.

The sum and carry are computed independently of each other.

Differential Cascoded Voltage Switch logic(DCVSL) full Adder

Differential Cascode voltage switch logic full adder

The DCVSL is formed by replacing the P-type transistor in CVSL with a cross coupled pair of P transistor yields a static version of that logic.

When the output at one side gets pulled low, then the opposite P transistor will be turned on and the output on that side will be pulled high.

CMOS Non Threshold Logic (CNTL) full Adder

CMOS non threshold logic full adder

CMOS non threshold logic employs the same binary decision trees and cross coupled P transistors as DCVS but an extra N-Type transistors are added.

Two N-Type transistors are placed in between the cross coupled P transistors and the output in order to lower the voltage level of the high output .

Another two N transistors are placed between the N Transistors trees and ground in order to raise the voltage level of the low output.

Enable/Disable CMOS Differential Logic (ECDL) Full Adder

Enable/Disable CMOS Differential Logic (ECDL) Full Adder

ECDL is an extension to the DCVS Full Adder.

ECDL uses a completion signal, DONE, to pre-discharge the outputs of each stage.

The DONE input signal goes low when the previous stage has finished its completion.

Enhancement source Coupled Logic is another variation on the DCVS full adder.

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