Low-Power VLSI rev1 - Yonsei Universitytera.yonsei.ac.kr/class/2013_1/lecture/Topic 11 Low-Power...

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Low-Power VLSI

Seong-Ook Jung

2013. 5. 27.

[email protected]

VLSI SYSTEM LAB, YONSEI University

School of Electrical & Electronic Engineering

2 YONSEI Univ. School of EEE

Contents

1. Introduction

2. Power classification & Power – performance relationship

3. Low power design1. Architecture and algorithm level

2. Circuit level

3. Device level

4. NTV operation

4. Summary

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Introduction


Technology Scaling

Technology Scaling : Moore’s law The number of transistors that can be placed on an integrated circuit

has doubled approximately every 18 months

[1] http://en.wikipedia.org

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Development Trend

Scaling (More Moore) More devices are integrated in a

chip

New scaling road mapNot only ‘geometrical scaling’ for

2D device, but also ‘equivalent scaling’ for 3D device

Beyond bulk CMOSFinFET, SOI…

Functional Diversification (More than Moore) Several functions are merged in

a chip

[2] ITRS (International Technology Roadmap for Semiconductors) 2011


SoC Performance

SoC Performance : Exponentially Increases!! Thanks to both device technology and design methodology


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SoC Power Consumption Problem

SoC Power Consumption : ‘Also’ Severely Increases After 15 years, about x10 power is required…



Process Variation Problem

Process Variation : Result of Scaling Global variation and local variation

Global variation Comes from fabrication, lot, wafer processes

Different process corner (NMOS-PMOS : SS/SF/TT/FS/FF)

Local variation Truly random variation between device with identical layout

[3] Synopsis, 2005 [4] http://cnx.org

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Process Variation Problem

Performance Variation due to Process Variation Frequency difference ≈ 30%

Leakage current difference ≈ x20

⇒ Process variation should be considered in SoC design

[5] A. Devgan, “Leakage Issues in IC Design: Part 3”, IBM


Effect of the Process Variation

Limitation for Low Voltage / Low Power Operation ID∝W/L*(VDD-VTH)α

VTH variation ⇒ ID variation ⇒ Performance Variation !!

Need more design margin due to process variation ⇒ VDD ↑

Yield Limitation Process variation ⇒ failure probability ↑ ⇒ Yield ↓

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Importance of Low Power VLSI Design

Low power VLSI design !!!

Process variation tolerant design



State-of-the-arts Low Power VLSI in Commercialized Product

[6] http://www.techinsights.com

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SPEC of State-of-the-arts Low Power VLSI

HKMG & DVFS?

In this class, we will study about a variety of low power design techniques

[1] http://en.wikipedia.org/

Power Classification & Power – Performance Relationship

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Power Consumption of CMOS Circuits

Ptotal = Pdynamic + Pleakage

Psw + Psc

Power Classification

=


Switching Power : Psw

Psw is due to the charge and discharge (output transition) of the capacitors driven by the circuit according to input transition.

Psw = CLVDD2f

I=CLdV/dt=CL∆Vf

Psw=IVDD=CL∆V VDDf

In digital circuit, ∆V=VDD

Psw=IVDD=CLVDD2f

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Short Circuit Power : Psc

Psc is caused by the simultaneous conductance of PMOS and NMOS during input and output transitions.

Psc = (β/12)(VDD-2VTH)3 (t3-t1)

When VTN < VIN < VDD – |VTP|

VIN = VTN @ t1VIN = VDD – |VTP| @ t3


Leakage Power : Psub, Pgate & Pjunc

Psub Ideal MOSFET : Isub = 0 In short channel MOSFET, Isub

exists when |VGS|<|VTH| Psub∝ Exp[(VGS-VTH)/mvT ] VDD

Pgate Ideal MOSFET : Igate = 0 In short channel MOSFET, Igate

exists because of thin TOX

Pgate∝WL (VGS/TOX)2 VDD

Pjunc Reverse PN junction leakage Pjunc∝ Exp[VD/vT -1] VDD

[7] K.M.Cao, “BSIM4 Gate Leakage Model Including Source-Drain Partition”, IEDM, 2000[8] http://www.altera.com/

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Power Vs. Performance

Case.1 : VDD ↓ All power consumption ↓ However… Delay ∝ CLVDD/ID∝

CLVDD/(VDD-VTH)α

Thus, VDD ↓ Delay ↑ Performance loss

Case.2 : VTH ↑ Psc ↓ and especially, Psub ↓ However… Delay ∝ CLVDD/ID∝

CLVDD/(VDD-VTH)α

Thus, VTH ↑ Delay ↑ Performance loss

Case.3 : f ↓ Psw ↓ However… Throughput ∝ f Performance loss

Power consumption equation Psw = CLVDD

2f

Psc = (β/12) (VDD-2VTH)3 (t3-t1)

Psub∝ Exp[(VGS-VTH)/mvT ] VDD

Pgate∝WL (VGS/TOX)2 VDD

Pjunc∝ Exp[VD/vT -1] VDD


Tradeoff w.r.t VTH

Tradeoff between power and performance Low power design :

Power reduction without performance degradation

[9] S. Mutoh, “Review of low-voltage CMOS LSI technology as a standard in the 21st century”, 1998

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Low Power Design - Architecture and Algorithm Levels


Parallelism

[10] A.P. Chandrakasan, “Minimizing power consumption in digital CMOS circuits”, Proc. of IEEE, 1995

Lower VDD and frequency are used at the expense of area penalty

By adopting parallelism…Power ~ x 0.36

Area ~ x 3.4

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Pipeline

[10] A.P. Chandrakasan, “Minimizing power consumption in digital CMOS circuits”, Proc. of IEEE, 1995

By inserting additional pipeline latch, logic depth of critical path is reduced and thus logic can be operated with slower rate

By adopting pipeline…Power ~ x 0.39

Area ~ x 1.3

Low Power Design- Circuit Level

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Critical Path

Critical Path : The Worst Case Delay Path Determines SoC’s maximum performance

# of critical path << # of non-critical path

Fast non-critical path is just wasteful…By increasing non-critical path’s delay, we may achieve power

reduction because of tradeoff relation between power & performance


Dual VDD

Basic Idea VDDL

Logic gates off the critical path

VDDH

Logic gate on the critical path

Reduce power without degrading the performance

Shaded : VDDL

Non-shaded: VDDH

[11] K. Usami, “Automated low-power technique exploiting multiple supply voltages applied to a mediaprocessor”, JSSC, 1998

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Dual VTH

High-VTH

Assigned to transistors in noncritical path.

Leakage saving in both standby and active modes

Low-VTH

Assigned to transistors in critical path

Maintained performance

[12] J. T. Kao, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits”, JSSC, 2000


MTCMOS

MTCMOS : Multiple Threshold voltage CMOSBasic Circuit Scheme

Two different VTH

High-VTH (0.5~0.6V) / Low-VTH (0.2~0.3V) Two operating mode

Active / Standby

Operation Active mode

SL=1 / SL=0 VDDVVDD / VGNDVVGND

Low-VTH operating frequency

Standby mode SL=0 / SL=1 VDDV & VGNDV = floating High-VTH leakage

[13] Anis, M, “Dynamic and leakage power reduction in MTCMOS circuits”, Proc. of IEEE, 2002

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DVFS : Basic Concept

Basic Concept Pdynamic = CVDD

2f

VDD and frequency scaling simultaneously

VDD scalingA best way to get low Pdynamic because Pdynamic∝VDD

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Frequency scalingOperating frequency = throughput

All tasks do not require maximum throughput

By controlling the frequency, SoC improves energy efficiency

[14] G. Dhiman, “Analysis of Dynamic Voltage Scaling for System Level Energy Management”, hotpower, 2008


SONY Microprocessor

[15] M.Nakai, “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor”, JSSC, 2005

DVFS Block

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DVFS

DVFS Block Diagram

Closed loop system DVC : VDD control circuit DFC : Frequency control circuit


Delay Synthesizer Structure

Composed not only a simple transistor delay factor, but also wire delay and rise/fall delayGate delay component : one of nominal gate length and another of long

gate lengthRC delay component : wires from each of the four metal layers and its

total length is 14mm

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Delay Synthesizer Effect


Operation (DVC+DFC)

Operation Procedure

Low → High : The main logic clock frequency is changed after the DVC confirms the voltage has increased enough

High → Low : Both the DVC reference clock and the system clock are changed simultaneously

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Performance Enhancement

Low Power Design- Device Level

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High-K & Metal Gate

High-K & Metal Gate SiO2 -> High-K material

Thick oxide can be usedwithout performance degradation

Gate leakage is substantiallydecreased

Low power & High performance !!

Poly gate -> Metal gatePoly gate is not suitable to high-k

material High switching voltage is required

Metal gate solves the problem of poly gate

Low power !!

[16] http://www.automationnotebook.com


FinFET

Characteristics Vertical structure

FinFET effective width= fin thickness + 2×fin height

ScalingAs scaling goes on, variation

of planar MOSFET get worse. VDD scaling is impossible.

However, FinFET’s VTH variation can be reduced. Fully depleted device Superior short channel control

Undoped body No random dopant fluctuation

VDD scaling is possible ⇒ low power !!

[17] T. Chiarella, "Migrating from Planar to FinFET for Further CMOS Scaling: SOI or Bulk?”, ESSDERC, 2009,

3D FinFET

Fin

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Low Power Design- Near-Threshold Voltage (NTV) Operation


Low Voltage Operation

Low Voltage Operation Near- and sub-VTH digital circuit design has been

focused on low power consumption.

Sub-VTH Operation Sub-VTH operation is suitable only for specific

applications which do not consider performance.

Near-VTH Operation Near-VTH operation is suitable for applications

which use the DVFS, such as AP in cell phone.

Balanced trade-off between power and performance

R. G. Dreslinski, Proc. IEEE, 2010

[18] R. G. Dreslinski, "Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits”, Proc. of IEEE, 2010

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NTV Application

Samsung and Intel’s Products

Samsung : ARM Cortex-A7 processor Intel : IA-32 processor


Samsung’s NTV

Samsung mentioned the NTV operation in Samsung’s press release on Dec. 19. 2012. Samsung Electronics Co., Ltd. announced that it reached another milestone in

the development of 14nm FinFET process technology with the successful tape-out of multiple development vehicles in collaboration with its key design and IP partners.

As part of its 14nm FinFET development process, Samsung, and its ecosystem partners – ARM, Cadence, Mentor and Synopsys – taped out multiple test chips ranging from a full ARM® Cortex™-A7 processor implementation to a SRAM-based chip capable of operation near threshold voltage levels as well as an array of analog IP.

Samsung used Synopsys tools optimized for FinFET devices to implement additional IP on this vehicle, including low power SRAMs intended to operate with the power supply close to threshold voltage levels. The move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges including modeling. The multi-year collaboration between Samsung and Synopsys has delivered foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices.

[19] http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=12461

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Intel’s NTV Intel presented 3 papers applying the NTV operation in ISSCC 2012.

[20] “Intel Labs at ISSCC 2012”, Intel Corporation, 2012


Issues of NTV operation

Performance Variation In near-VTH region, the dependencies of driving current on VTH, VDD, and

temperature approach exponential, which significantly increases the performance variation.

[18] R. G. Dreslinski, "Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits”, Proc. of IEEE, 2010

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Summary


Summary

State-of-the-arts VLSI Low power & process variation tolerant design

P = Psw + Psc + Psub + Pgate + Pjunc

Pdynamic Pstatic

Power and performance : Trade-off Low power design

Architecture and algorithm level : parallelism, pipe line Circuit level

Long channel Stacked Dual VDD

Dual VTH

MTCMOS DVFS

Device level : FinFET, HKMG NTV operation

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