M-RAMM-RAM

Ashutosh RanjanAshutosh Ranjan Roll No - 010Roll No - 010

Memory CategoryMemory Category

Volatile Memory ComparisonVolatile Memory Comparison

SRAM Cell

• Larger cell lower density, higher cost/bit • Read non-destructive • No refresh required • Simple read faster access

• DRAM Cell

• Smaller cell higher density, lower cost/bit • Needs periodic refresh, and refresh after read • Complex read longer access time

word line

bit line bit line

word line

bit line

The primary difference between different memory types is the bit cell.

Limitation of Flash MemoryLimitation of Flash Memory

The main weakness of flash memory is the number of times that data can be written to it. Data can be read from flash as many times as desired, but after a certain number of "write" operations, it will fail. Most flash devices are designed for about 100,000 - 1,000,000 write operations (or "write cycles").

The erase command takes much longer than the write process; and, for manufacturing reasons, flash memory chips are not made with the ability to erase individual bits or bytes. Only large sections of memory (usually 512 bytes or more) can be erased at a time.

MRAM IntroductionMRAM Introduction

• It is a non-volatile, random access memory technology that is designed to initially replace flash memory and, potentially, DRAM memory.

• MRAM uses magnetic, thin film elements on a silicon substrate that can be built on the same chip with the logic circuits.

The MRAM product, called MR2A16A .

MRAM - The “Universal” Memory

• MRAM is a revolutionary, non-volatile memory chip with potential to replace all other forms of semiconductor memories

• Allows single memory solution for multiple memory options within one chip - enabling faster, lower power, less expensive solutions for next-generation wireless and portable products

• MRAM offers solution to technology shortcomings such as slow computer or cell phone startup, data loss, long waits for data to load and short battery life

Information flux.Information flux.

Information

Ou

tsid

e

w

ord

Input

Output

Information

transmission

Information

Processing

Information

storage

DRAM, MRAM Magnetic (HDD)

Optical (CD, DVD)

MRAM AdvantagesMRAM AdvantagesData Retention 10 years

Symmetrical Read/Write25-35ns for 4Mb at 0.18um technology node

Endurance (>1016)Data stored by magnetic polarization

Integrated with Existing CMOS Baseline

Compatible with Embedded Designs

4Mb Memory Device sampled

Nonvolatile

Fast

Unlimited Cycles

Viable

History and History and development... development...

M-RAM – quick view.Magnetoresistivity. GMR effect - 1980th.

TMR effect – 1995 year.

M-RAM based on:

• 1989 - IBM scientists made a string of key discoveries about the "giant magnetoresistive effect" in thin-film structures.

• 2000 - IBM and Infineon established a joint MRAM development program.

• 2003 - A 128 kbit MRAM chip was introduced

• 2004 -Renesas Technology Develops High-Speed, High-Reliability MRAM Technology.

• 2005 - Renesas Technology and Grandis to Collaborate on Development of 65 nm MRAM Employing Spin Torque Transfer.

Behavior of a ferromagnet in a magnetic

field

H

MsH

Hysteresis

Memory !!

H

M

Ms

H

M

Linear response

Sensor !!

N S

S N

N S

N

S

Magnetic LEGO and Magnetoresistance

Stack of ferromagnetic thin layersseparated by non-magnetic layers

Resistance can be usedto determine the magneticstate of stack

FM

FM

Normal metal(Cu, Au)

Insulator(Al2O3)

VVVV

Giant magnetoresistance (GMR)

Resistance dependson magnetic fieldRAP >> RP

spin-valve

multilayer

granular system

Ferromagnetic thin films (Co, NiFe) separated by thin non-magnetic metal spacers(Cu, Au)

Two current model of GMR

Parallel stateLow resistance

Anti-parallel stateHigh resistance

Co Cu Co

x

xSpin-down

Spin-up

RMaj

RMaj

Rmin

Rmin

Spin-down

Spin-up

xx

Co Cu Co

Spin-down

Spin-up

RMaj RMaj

Rmin Rmin

Spin-down

Spin-up

GMR = (-1)2

4 = Rmin/RMajGMR =

(-1)2

4 = Rmin/RMaj

Tunnel magnetoresistance (TMR)

Ultrathin insulatorAl2O3 ~ 1.0 nm

Ferromagnet 1

Ferromagnet 2

AFM

State-of-the-art:

TMR of up to 70% at 300 K

Large effects at RT first observed by Moodera et al. PRL 74, 3273 (1995)

Storage and states of a Storage and states of a bit. bit.

Storage state:

DRAM: charge of capacitor. Flash, EEPROM: charge on floating gate. FeRAM: charge of a ferroelectric capacitor.

TM

R [

%]

Field [Oe]

MRAM: charge and spin.

„1”

„0”

Soft ferromagnetInsulator

Hard ferromagnet

Magnetic Random Access Memory (MRAM)

Cross point architecture

Magnetic memory element

High resistance

Low resistance

topping

crust

integration

Si circuitry

Integration of MRAM (pizza style)

Writing a bit in MRAM

Send current through metal word and bit lines.

This creates a local magnetic field to switch a memory cell at the cross point

Reading a bit in MRAM

- Send current through element- Measure its resistance (high or low)

But many parallel current paths diode or transistor needed

Reading a bit in MRAM

- Send current through a single element- Measure its resistance (high or low)

Select one element inarray using isolationtransistor

p.s. Resistancematching needed !

Information is stored as magnetic polarization, not charge

The state of the bit is detected as a change in resistance

How MRAM WorksHow MRAM Works

Magnetic layer 1 (free layer)

Magnetic layer 2 (fixed layer)

Tunnel barrier

Magnetic vectors are parallel – low resistance. “0”

Magnetic vectors are anti-parallel – high resistance. “1”

S

S N

N N

S N

S

• MRAM normally functions by constructing minuscule magnetic fields at intersections in a grid of nanoscopic power rails. When current attempts to travel through a power rail which is opposing the polarization of one of the magnetic field bits, its current flow is mitigated and the bit value stored by the field is detected by this weakened current flow.

MRAM CellMRAM Cell

• Magnetoresistive random access memory (MRAM) uses the magnetic tunnel junction (MTJ) to store information

• MRAM cell composed of a diode and an MTJ stack

• MTJ stack consists of two ferromagnetic layers separated by a thin dielectric barrier

• Polarization of one layer fixed, other used for information storage

Bit Line

Diode

MTJ Stack

Word Line

PtCo/FeNi/FeAl2O

3

Co/FeNi/FeMn/FePtW

Read/Write Current

1 T-1 MTJ MRAM memory cell operation - read

Isolation Transistor“ON”

Read Mode

ISense

To read an MRAM bit, current is passed through the bit and the resistance of the bit is sensed.

1 T-1 MTJ MRAM memory cell operation - write

Free LayerTunnel Barrier

Fixed Layer

Easy Axis Field

Hard Axis Field

Isolation Transistor“OFF”

“Write Mode”

IEasy

IHard

To write an MRAM bit, current is passed through the programming lines generating magnetic fields.

The sum of the magnetic field from both lines is needed to program the bit.

No moving parts.

Other MRAM cell architectures.Other MRAM cell architectures.

Twin cell arrays:

Circuit is faster than the 1T1TMR implementation. Less atractive on a cell density and cost basis.Diode cell:

SOI diodes allow the integration of a memory with most circuits without sacrificing silicon wafer surface area. SOI diodes suitable for this aplication haven’t been developed yet.

Transistorless array:

Large reduce in cell area. Complex circuity required to read bit state, slow read.

4Mb Memory Cell4Mb Memory Cell

M5-BLVia1-4M1-3

N+P-

Layer Name

N+ N+

M4-DL MVia BE TVia TETJ

N+ N+N+ N+

M1

M3

M2

M4-DL

V1

V2

V3

V4MVia

BE

TETJ TVia

M5-BL

Group SelectPass Xtor Pass XtorThk Oxide Xtor

i

i

Program path for Writing information

Sense Path for bit cell reading

MRAM 32Kb MRAM 32Kb memory segment.memory segment.

Bit line 31

Digit line

Digit lineWord line

Bit line 0

Word line

MRAM Reference Circuit

Bit Line

Rmax Rmin

Word Line common source

Word Line

Rmax Rmin

Rref = 1/2 * (Rmin + Rmax) Reference Cell

Reference Cell uses Parallel/Serial combination of MTJ’s in two memory states to generate “mid resistance” reference between those two states

ImplementationImplementationof 1-MTJ / 1-transistor of 1-MTJ / 1-transistor

cell.cell.

Word

line

NiFe (free layer)

CoFe (fixed layer)Ru

CoFe (pinned layer)

Al2O3 (tunneling barrier)

SA

F

cladclad HwI

H 2wI

Hunclad

2

Toggle Bit TechnologyToggle Bit Technology

Full MTJ Stack for MRAM

Full MTJ Stack for MRAM

Low resistance contact Top electrode

Switches between two magnetic states in applied field. Free Stores information.

AlOx Tunnel barrier. Affects resistance and MR ratio.

Fixed Synthetic Antiferromagnet (SAF). AF coupling through Ru Ru layer makes the structure stable in applied magnetic fields.

Relative thickness of Fixed and Pinned used to center loop. Pinned

AF pinning layer Pins the bottom magnetic layers.

Template Seeds growth, determines crystal structure Seed

Base electrode Low resistance contact

Bit Line

DL Program Line

BL Program Line

Free Tri-Layer

Tunnel Barrier

Pinning Layer

Bit Line

Program Line 1

Program Line 2

Free Tri-Layer

Tunnel Barrier

Pinned Ferromagnetic

Pinning Layer

Ferromagnetic layerCoupling LayerFerromagnetic layer

Toggle MRAM Bit CellToggle MRAM Bit Cell

Elements of Toggle BitElements of Toggle Bit

• Balanced SAF free-layer

• Bit oriented 45º to lines

• Unipolar currents

• Overlapping pulse sequence

• Pre-read / decision write

WriteLine 1(H1)

WriteLine 2(H2)

HardAxis

EasyAxis

HardAxisHardAxisHardAxis

EasyAxisEasyAxisEasyAxis

Write Line 2

Write Line 1

HardAxisHardAxisHardAxis

EasyAxisEasyAxisEasyAxis

Write Line 2

Write Line 1

HardAxisHardAxisHardAxis

EasyAxisEasyAxisEasyAxis

Write Line 2

HardAxisHardAxisHardAxis

EasyAxisEasyAxisEasyAxis

Write Line 2

HardAxisHardAxisHardAxis

EasyAxisEasyAxisEasyAxis

Write Line 2

Write Line 1

Write Line 1

Write Line 2

t0 t1 t2 t3 t4

Off

On

Off

On

H 1

I 1

H 2

I 2

H 1

I 1

H 2

I 2

Write Line 1

Write Line 1

Toggle MRAM Switching SequenceToggle MRAM Switching Sequence

MCU

SRAM

BatteryControl Chip

CE

• Problems• System design complexity• Board space and weight• Battery life• Manufacturing complexity• Environmental concerns

MRAM• Solutions• Single chip solution• Simple, low cost system

design• Manufacturing

simplification• No battery• Unlimited life• Smaller profile • Higher performance• Environmentally friendly

“Built-in-house” Components

MCUSRAM

Battery

• Problems• Cost• Manufacturing complexity• Battery life• Low performance• Environmental concerns

“Off-the-shelf” components

Addr/Data Bus

Sample Application – Battery Backed Sample Application – Battery Backed SRAM ReplacementSRAM Replacement

Addr/Data Bus

Addr/Data Bus MCU

Target Application – Battery Target Application – Battery Backed SRAM ReplacementBacked SRAM Replacement

•Primary Usage– Data Logging– Parameter Storage– System Status– Storage Buffers

• Battery Contact Failure

• Out-of-Tolerance Voltage Spikes

• Limited Life

Manufacturing Complexity

More Parts & Labor & Board Space & WeightSystem Design

Complexity

MR2A16A Application SpacesMR2A16A Application Spaces►Target Application Spaces

– Data Streaming• RAID systems and

servers• POS terminals• Data-acquisition

systems• Data logging• Buffers• Routers / switches• Printers / copiers

– System Configuration• Black-box applications• Gaming• System status

►Currently not targeting high density, space-constrained applications

– Portable digital audio players– Jump drives– Digital camera data storage

MRAM parameters

Major limitations of MRAM:

• Although MRAM has many advantages over virtually every existing memory type, it is still in its infancy. Many had hoped MRAM would usher in the age of instant-on computers able to replace the computer main memory and hard drives, but, due mainly to its cost, these hopes remain a dream.

• At $25 per 0.5 MB, MRAM has no chance of competing with existing RAM selling for $25 per 256 MB, not to mention Flash, which sells for $25 per 1 GB.

• The only place where MRAM might be widely utilized is in specialized markets, for example, as a Battery-Backed SRAM replacement. Only when it breaks its current high price per MB ratio will MRAM's unique qualities find widespread usage. 

Roadmap to future Roadmap to future storage technologies.storage technologies.

RRAM with CMR

Bio – MRAM,Bio – MRAM,vision for tomorrow?vision for tomorrow?

MRAM array

Biomolecule labeled by magnetic

markers

MRAM Roadmap ?

4 Motorola tunnelMRAM demo’s

Honeywell GMR-MRAMlimited performance

0.256

Conclusion

• Non Volatile

• No need to refresh

• (potentially) High density

• Non destructive read

• Read speed = write speed; < 50ns

• Unlimited R/W endurance

• Soft error immunity

Thank you