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Pulse and Digit al Circuit s Lab MAN U AL ONLY FOR REFERENCE

1Pulse and Digit al Circuit s Lab MAN U AL ONLY FOR REFERENCE

Experi ment No:1

LINEAR WAVE SHAPING

AIM : a) To observe the response of RC Low pass circuit for a square wave input fordifferent time constants

i) RC>>T ii) RC = T iii) RC

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i = resulting current

Applying Kirchoffs Voltage Law to RC low pass circuit (fig.1).

???T

oi dt i

C iRV .

1

Multiplying throughout by C, we get

???T

oi dt iiRC CV .

As RC >> T , the term ?T

o

dt i. may be neglected

? iRC CV i ?

Integrating with respect to T on both sides, we get

? ??T T

i dt i RC dt CV 0 0

..

? ??T t

i dt V RC dt i

C 0 0.

1.

1

??T

dt iC

V 0

0 .1

? ??t

i dt V RC V

00 .

1

The output voltage is proportional to the integral of the input voltage.

EXPECTED GRAPH:

V i

t

t

t

RC>T

(0.9)V 0 (0.1)V 0

V0

t r

RC=T

V0

0
http://www.uandistar.org/http://www.uandistar.org/

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b) High Pass Circuit.The Capacitor in series arm and resistor in the shunt arm, the resulting circuit is calledHigh pass circuit

Figure: 2. RC High Pass Circuit.

The higher frequency components in the input signal appears at the output with lessattenuation than the lower frequency components because the reactance of the capacitordecreases with increase in frequency. This circuit works as a differential circuit. A circuit inwhich the output voltage is proportional to the derivative of the input voltage is known as

differential circuit. The condition for differential circuit is RC value must be much smaller thenthe time period of the input wave (RC

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Therefore iV dt d

RC V ?0 . iV dt d

V ?0

EXPECTED GRAPHS:

DESIGN:

1. Choose T = 1msec.2. Select C = 0.01 ? F.3. For RC = T; select R.4. For RC >> T; select R.5. For RC T, the Low pass circuit works as an integrator.

PROCEDURE:

1. Connect the circuit as shown in the figure1 &2.2. Connect the function generator at the input terminals and CRO at the output

terminals of the circuit.3. Apply a square wave signal of frequency 1KHz at the input. (T = 1 msec.)4. Observe the output waveform of the circuit for different time constants.5. Calculate the rise time for low pass filter and tilt for high pass filter and compare

with the theoretical values.6. For low pass filter select rise time (t r ) = 2.2 RC (theoretical). The rise time is

defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its finalvalue.

7. % tilt = ( T/2RC ) ? 100 ( theoretical)% tilt = [ ( V 1 V 1? ) / ( V / 2 ) ] ? 100 ( practical)

V i

t

t

t

RC=T

RCTV1

t

V0

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QUESTIONS:1. What is meant by linear wave shaping?2. Derive the expression for the generalized single time constant transient of a series RC circuit?3. Derive the expression for the Rise time and % of tilt?

CONCLUSION:Low pass filter:

Conclusions can be made on theoretical and practical values of rise time and outputwaveforms of the Linear wave shaping circuits are identical or not when compared withthe theoretical wave forms.

High pass filter:Conclusions can be made on theoretical and practical values of % tilt and outputwaveforms of the Linear wave shaping circuits are identical or not when compared withthe theoretical wave forms.

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Experiment No:2

NON LINEAR WAVE SHAPING - CLIPPERS

AIM : To study the clipping circuits for different reference voltages andto verify the responses.

Components Required:1. Resistors - 1K ? 2. IN4007 Diode 2No.

Apparatus Required : 1. Bread board.2. CRO (1Hz- 20MHz)3. Function Generator(1Hz-1MHz)4. Power supply(0-30V)5. Connecting wires.

THEORY:

The non-linear semiconductor diode in combination with resistor can function as clippercircuit. Energy storage circuit components are not required in the basic process of clipping.

These circuits will select part of an arbitrary waveform which lies above or below some particular reference voltage level and that selected part of the waveform is used for transmission.So they are referred as voltage limiters, current limiters, amplitude selectors or slicers.

There are three different types of clipping circuits.1) Positive Clipping circuit.2) Negative Clipping.3) Positive and Negative Clipping ( slicer ).

In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative portion of sinusoidal signal is obtained in the output of reference voltage is added, instead ofcomplete positive cycle that portion of the positive cycle which is above the reference voltagevalue is clipped.

In negative clipping circuit instead of positive portion of sinusoidal signal, negative portion is clipped.

In slicer both positive and negative portions of the sinusoidal signal are clipped.

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VR + V ?

I. Positive Clipping

Figure:1

Figure: 2(a). Input waveform Figure: 2(b)Output waveform.

V i is a input sinusoidal signal as shown in the figure 2(a) . For positive portion of the

sinusoidal the diode IN4007 gets forward biased. The output voltages in the voltage across thediode under forward biased which is cut-in-voltage of the diode. Therefore the positive portionabove the cut-in-voltage is clipped or not observed in the output (V 0 ) as shown in figure 2(b).

II. Positive Clipping with Positive Reference Voltage

Figure:3.

Figure:4(a). Input waveform Figure:4(b). Output waveform.

The input sinusoidal signal ( V i ) in figure 4(a) can make the diode to conduct when itsinstantaneous value is greater than V R. Up to that voltage ( V R ) the diode is open circuited and theoutput voltage is same as the input voltage. After that voltage ( V R) the output voltage is V R plusthe cut-in-voltage ( V ? ) of the diode as shown in figure 4(b).

IN 4007

1 KO

VR

V i V 0

Vi

t V?

V0

t

Vi

t

V0

t

IN 4007

1 KO

V 0 V i

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III. Positive Clipping with Negative Reference Voltage

Figure: 5.

Figure:6(a). Input waveform Figure:6(b) Output waveform.

In this circuit the diode conducts the output voltage is same as input voltage. The diodeconducts at a voltage less by V R from cut-in-voltage called as V ? . For voltage less than V ?, thediode is open circuited and output is same as input voltage.

IV Negative Clipping Circuit

Figure:7.

Figure:8 (a). Input waveform Figure:8 (b). Output waveform.

V ? -V R

IN 4007

1 KO

VR

V i V 0

IN 4007

1 KO

V i V 0

Vi

t

V0

t

Vi

t

-V ?

V0

t

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V V 0

For this portion of the input sinusoidal signal (Vi ), the diode gets reverse biased and it is open.Then the output voltage is same as input voltage. For the negative portion of the signal the diodegets forward biased and the output voltage is the cut-in-voltage ( -V ? ) of the diode. Then theinput sinusoidal variation is not seen in the output. Therefore the negative portion of the inputsinusoidal signal (Vi ) is clipped in the output signal ( V 0 ).

V. Negative Clipping with Negative Reference Voltage

Figure:9

Figure:10(a). Input waveform. Figure:10(b) Output waveform.In this circuit, the diode gets forward biased for the input sinusoidal voltage is less than

( V R). For input voltage greater than ( V R), the diode is non-conducting and it is open. Then theoutput voltage is same as input voltage.

VI. Negative Clipping with Positive Reference Voltage

Figure:11.

IN 4007

1 KO

VR

V i V 0

IN 4007

1 KO

VR

Vi

t

-V R -V ?

V0

t

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Figure:12(a) Input waveform Figure:12(b) Output waveform.

For input sinusoidal signal voltage less than V R, the diode is shorted and the outputvoltage is fixed ar V R. For input sinusoidal voltage greater than V R the diode is reverse biasedand open circuited. Then the output voltage is same as input voltage.

VII. Slicer

V i V 0

Figure:13.

Figure:14(a). Input waveform Figure14(b). Output waveform.

DESIGN:1. For positive clipping at V volts reference select V R = V.2. For negative clipping at V volts reference select V R = V.3. For clipping at two independent levels at V 1&V 2 reference voltages select

VR1 = V 1, V R2 = V 2 and V R2 = V R1 .

IN 4007

1 KO

VR1

IN 4007

VR2

Vi

tVR -V ?

V0

t

Vi

t V ?+V R

V ?-V R

V0

t

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PROCEDURE:1. Connect the circuit as shown in the figure 1.2. Connect the function generator at the input terminals and CRO at the output

terminals of the circuit.3. Apply a sine wave signal of frequency 1KHz, Amplitude greater than the reference

voltage at the input and observe the output waveforms of the circuits.4. Repeat the procedure for figure 3, 5, 7, 9, 11 and 13.

QUESTIONS:1. What is a clipper? Describe (i) Positive clipper (ii) Biased clipper (iii) Combination

clipper.2. Discuss the differences between shunt and series clipper.

CONCLUSION:

Conclusion can be made on theoretical and practical values of cut in voltage of diode and

also made on theoretical and practical output wave forms for different reference voltages

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Experiment No:3

NON LINEAR WAVE SHAPING CLAMPERS

AIM : To study the clampling circuits for different reference voltages andto verify the responses.

Components Required:

1. Resistors - 1k ? 2. IN4007 Diode3. Capacitor -10 ? F

Apparatus Required:

1. Bread board2. Function generator (1Hz 1Mz)3. CRO (1Hz- 20MHz)

4. Power supply (0-30V)5. Connecting Wires.

THEORY:

Clamping CircuitA clamping cir cuit i s one that takes an i nput waveform and pr ovides an output that i s

a f aith fu l repli ca of i ts shape but has one edge tightl y clamped to the zero voltage referencepoint.

There are various types of Clamping circuits, which are mentioned below:

1. Positive Clamping Circuit.2. Negative Clamping Circuit.

3. Positive Clamping with positive reference voltage.

4. Negative Clamping with positive reference voltage.

5. Positive Clamping with negative reference voltage.

6. Negative Clamping with negative reference voltage.

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Negative Clamping Circuit

Figure:1The input signal is a sinusoidal which begins at t=0. The capacitor C is charged at t = 0 .

The waveform across the diode at various instant is studied.During the first quarter cycle the input signal rises from zero to the maximum value V m.

The diode being ideal, no forward voltage may appear across it. During this first quarter cyclethe capacitor voltage V A = V i. The voltage across C rises sinusoidally, the capacitor is charged

through the series combination of the signal source and the diode. Throughout this first quartercycle the output V 0 has remained zero. At the end of this quarter cycle there exists across thecapacitor a voltage V A = V m.

After the first quarter cycle, the peak has been passed and the input signal begins to fall,the voltage V A across the capacitor is no longer able to follow the input voltage. For in order todo so, it would be required that the capacitor discharge, and because of the diode, such adischarge is not possible. The capacitor remains charged to the voltage V A = V m, and, after thefirst quarter cycle the output is V 0 = V i V m. During succeeding cycles the positive excursion ofthe signal just barely reaches zero. The diode need never again conduct, and the positiveextremity of the signal has been clamped to zero. The average value of the signal is V m.

Positive Clamping Circuit:

Figure:2

It is also called as negative peak clamper, because this circuit clamps at the negative peaks of a signal.

Let the input signal be V i = V m sin ? t. When V i goes negative, diode gets forward biasedand conducts. The capacitor charges to voltage V m, with polarity as shown. Under steady statecondition, the positive clamping circuit is given as,

V i V 0

VA

C

D

+ -

+

-

V i V 0

V m

C

D

+ -

+

-

+

-

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mi V V V ??0

)(0 mi V V V ???

Eq.1

During the negative half cycle of V i, the diode conducts and C charges to V m volts, i.e.,the negative peak value. The capacitor cannot discharge since the diode cannot conduct in the

reverse direction. Thus the capacitor acts as a battery of V m volts and the output voltage is given by equation.1 above. It is seen for figure 2, that the negative peaks of the input signal areclamped to zero level. Peak-to-peak amplitude of output voltage 2V m, which is the same as thatof the input signal.

Negative Clamping with Positive Reference Voltage

Figure:2

Since V R is in series with the output of negative clamping circuit, now the average value of theoutput becomes (-V m + V R ).

Similarly, the average ofi) Negative clamping with negative reference voltage is (-V m + V R ).

ii) Positive clamping is + V m.iii) Positive clamping with positive reference voltage is V m + V R.iv) Positive clamping with negative reference voltage is V m - V R.

Clamping Circuit Theorem:

It states that for any input waveform the ratio of the areas under the output voltage curvein forward direction to that in the reverse direction is equal to the ratio ( R f / R) .

R

R

A

A f

r

f ? .

Where A f = area of the output wave in forward direction. Ar = area of the output wave in reverse direction. Rf and R are forward and reverse resistances of the diode.

V i V 0

C

D

V R

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I. Negative Clamping

Figure:3

Figure:4 (a).Input waveform Figure:4 (b) Output waveform.

II. Negative Clamping with Positive Reference Voltage.

Figure:5

IN 4007

1 KOV i V 0

10 ? F

C

D R

IN 4007

1 KO

V i V 0

10 ? F

C

D

R

V R

t

V i V R

t

V 0

V i V m

-V m

V 0

t

-2V m

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III. Negative Clamping with Negative Reference Voltage.

Figure:7


IV. Positive Clamping.

figure:9

IN 4007

1 KOV i V 0

10 ? F

C

D R

tt

V 0 V i

-V R

IN 4007

1 KO

V i V 0

10 ? F

C

D

R

V R

V 0

t

V i

t

2V m

V m

-V m

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IN 4007

1 KO

V i V 0

10 ? F

C

D

R

V R

V. Positive Clamping with Negative Reference Voltage.

Figure: 11


VI. Positive Clamping with Positive reference Voltage.

Figure: 13


IN 4007

1 KO

V i V 0

10 ? F

C

D

R

V R

t

V i

V R t

V 0

t

V i

t

V 0 -V R

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PROCEDURE: 1. Connect the circuit as shown in the figure 3.2. Connect the function generator at the input terminals and CRO at the output

terminals of the circuit.3. Apply a sine wave greater than the reference voltage, and signal of frequency 1kHz at

the input and observe the output waveforms of the circuits in CRO.4. Repeat the above procedure for the different circuit diagram as shown inf figure 5, 7,

9, 11 and 13.

QUESTIONS:1. Explain the operation of a clamping circuit for a square wave input.2. Differentiate the clippers with clampers.3. Give the applications of clampers.

CONCLUSION:

Conclusion can be made on theoretical and practical values of cutin voltages of diodeand also conclude on theoretical and practical output wave forms for different referencevoltages

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C

B

E

QR B

IB

R L

IC

VBB IE VCC

Experi ment No:4

TRANSISTOR AS A SWITCH

AIM : To design and observe the performance of a transistor as a switch.

Components Required:1. Resistors2. LED3. 2N2369 Transistor

Apparatus Required :

1. Bread board2. Function generator 1Hz- 1MHz 1No.3. CRO 1Hz -20MHz 1No.4. Power supply 0-30V 1No.

THEORY:

Figure:1 Figure:2

Figure:3

Fig.1. Transistor as a switch. Fig.2 Pin configuration of transistor 2N2369.Fig.3 Output characteristics with load line(d.c)

The transistor Q can be used as a switch to connect and disconnect the load R L from thesource V CC . When a transistor is saturated , it is like a closed switch from the collector to theemitter. When a transistor is cut-off, it is like an open switch.

I

L

CC RV

IB > I B sat

IB = I B(sat)

IB =0Cut-off

Saturation

VC VCE0

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L

CE CC C R

V V I

??

CC CE V V ? Cut-off and Saturation : The point at which the load line intersects the I B = 0 curve is knownas cut-off. At this point, base current is zero and collector current is negligible small i.e., onlyleakage current I CEO exists. At cut-off, the emitter diode comes out of forward bias and normaltransistor action is lost.

V CE(sat) V CC

The intersection of the loadline and the I B = I B(sat) is called saturation. At this point basecurrent is I B(sat) and the collector current is maximum. At saturation, the collector diode comesout of reverse bias, and normal transistor action is again lost.

L

CC sat C R

V I ?)(

In figure:3 I B(sat) represents the amount of base current that just produces saturation. If base current is less than I B(sat) , the transistor operates in the active region somewhere betweensaturation and cut-off. If base current is greater than I B(sat) , the collector current approximately

equalsC

CC

RV

. The transistor appears like a closed switch.

B B BE BB R I V V ??

B

BE BB B R

V V I

?? .

If base current ( I B) is zero, the transistor operates at the lower end of the loadline and the

transistor appears like an open switch.CIRCUIT DIAGRAM:

Pin Configuration 2N2369 Figure 4.

DESIGN :

2N2369

VCC +12V

R C

R B IB

IC

1KO

LED0 or 5 V

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QUESTIONS:

1. Discuss the advantages of an electronic switch over a mechanical or electromechanical switch.

2. What is a switching circuit?3. Explain the terms collector leakage current and saturation collector current.

CONCLUSION:

Conclusions can made on what are the conditions required to operate the transistor as aswitch and also made on junction voltages of the transistor when it is ON and OFFalso conclude what happens if we apply high voltage to the transistor.

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Experi ment No:5

STUDY OF LOGIC GATES

AIM : To study the various logic gates by using discrete components.

Component Required :

1. Resistors - 1k ? -1, 10 k ? -22. IN4007 Diodes 2 no3. Transistor 2N2369

Apparatus Required:

1. Power supply 0-30V2. Bread board 3. Connecting wires 4. Multimeter

THEORY: TRUTH TABLE

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

AND GATE:

The AND gate as a high output when all the inputs are high the figure 1 showsone way to build the AND gate by using diodes.Case 1: When both A and B are low then the diodes are in the saturation region then the supply

from V CC will flow to the diodes then the output is low.Case 2: When A is low and B is high then diode D 1 will be in the saturation region and D 2 will

be in the Cut-off region, then the supply from V CC will flow through diode D 1 then theoutput will be low.

Case 3: When A is high, B is low the diode D 1 will be in the Cut-off region and diode D 2 will bein saturation region then the supply from V CC will flow through the diode D 2, thereforethe output will be low.

Case 4: When both the A and B are high then the two diodes will be in Cut-off region thereforethe supply from V CC will flow through V out then V out is high.

A

BY=A.B

SYMBOL

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OR GATE:

TRUTH TABLE

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

An OR gate has two or more inputs but only one output signal. It is called OR gate because the output voltage is high if any or all the inputs are high.

The figure 2 shows one way to build OR gate (two inputs) by using diodes.Case 1: When A and B are low then the two diodes D 1 and D 2 are in Cut-off region. Then the

V out is low.Case 2: When A is low and B is high then the diode D 1 is in Cut-off region and diode D 2 is in

saturation region, then the V out is high.Case 3: When A is high and B is low then the diode D 2 is in saturation region and diode D 1 is inCut-off region, then the V out is high.

Case 4: When both A and B are high the diodes D 1 and D 2 are in saturation region then theoutput V out is high.

NOR GATE:TRUTH TABLE

Symbol NOR gate is referred to a NOT OR gate because the output is B AY ?? . Read this as Y

= NOT A OR B or Y = compliment of the A OR B. the circuit is in an OR gate followed by a NO gate OR inverter. The only to get high output is to have both inputs low.

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY = A + B

SYMBOL

A

B

Y = A + B B AY ??

A

B B AY ??

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A

B

Y = A.B B AY .?

A

B B AY .?

NAND GATE:

TRUTH TABLE

Symbol

NAND gate is referred to as NOT AND GATE because the output is B AY .? read this as Y = NOT A AND B or Y = Compliment of A AND B. By this gate the output is low when all theinputs are high.

NOT GATE:

TRUTH TABLEA Y

0 1

1 0

The Inverter or NOT gate is with only one input and only one output. It is called inverter because the output is always opposite to the input.

The figure5 shows the one way to build inverter circuit by using transistor (CE mode)when the Vin is low then the transistor will be in the Cut-off region. Then the supply from VCC

will flow to Vout. Then the Vout is high. When Vin is high then the transistor is in the saturationregion then the supply from VCC will flow through the transistor to the ground, then the Vout islow.

CIRCUIT DIAGRAM :

Figure 1 Figure 2

A B Y

0 0 1

0 1 11 0 1

1 1 0

A Y= A

S mbol

D1 IN4007

D2 IN4007

10KO

YA

B

OR GATE

D1 IN4007

D2 IN4007

10KO

YA

B

AND GATEVcc+5v

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Figure 3

Figure 4

Figure 5

D IN4007

D2 IN4007

10KOY

A

B

VCC +5V

NAND GATE

1KO

10KO

2N2369

Vcc+5v

1KOY

2N2369A NOT GATE

10KO

D1 IN4007

D2 IN4007

10KO

Y

A

B

NOR GATE

1KO

10KO

2N2369

Vcc+5v

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PROCEDURE:1. Connect the circuit as shown in figure 12. Apply 0v to logic 0 and 5V to logic 1 using power supply.3. Verify the truth tables of various gates for different conditions of inputs.4. Repeat the steps 1&2 for figures 2, 3, 4 & 5.

TRUTH TABLES

AND GATE OR GATE NAND GATE NOR GATE NOT GATEA B Y A B Y A B Y A B Y A Y0011

0101

0011

0101

0011

0101

0011

0101

0

1

QUESTIONS:

1. Realize AND, OR, NOT gates using NAND & NOR gates2. Why NAND & NOR gates are called universal gates.

CONCLUSION:

Conclusions can be made on theoretical and practical values of the truth tables for thegiven logic gates

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Q

Q

S /RFLIP-FLOP

S

R

Experiment No:6

STUDY OF FLIP-FLOPS

AIM: To verify the truth table of SR latch, J-K flip-flop,J-K master Slave flip- flop, T flip-flop and D flip-flop.

Components Required:

1. IC 74LS002. IC 74LS103. IC 74LS04.

4. Digital Trainer Kit.THEORY :

RS F L OP-FL OP: Consider the logic Symbol for RS flip-flop shown in Fig. Notice that the RS flip-flop has

two inputs, labeled S and R. The two outputs are labeled Q and Q . Note that the outputs arealways opposite, or complementary in the flip-flops.

Fig. shows the timing diagram for an RS flip-flop. Notice that the output Q goes highwhenever R goes low; and the output Q goes LOW whenever S goes LOW. The logic levels (0,1) are on the left side of the wave forms. The output Q holds, whenever the both inputs arehigh.

Fig. Logic symbol for RS FLIP-FLOP

CLOCKED RS FL I P-FL OP (RST FL I P-FL OP):

We know that the flip-flops are synchronous bistable devices. The term synchronousindicates that the output changes its state only at a specified point on a triggering input called theclock; i.e. changes in the output occur in synchronization with the clock.By adding gates to the inputs of the basic circuit, the flip-flop can be made to respond to inputlevels during the occurrence of a clock pulse. Note that the clock signal is a square wave signaland the signal prevents the flip-flops from changing the states until the right time occurs. Theclocked RS flip-flop using NAND gates are shown in Fig.

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Q

Truth Table

JK FLI P-FL OP:

The JK flip-flop has the features of all other flip-flops, and hence it can also beconsidered as Universal flip-flop. This JK flip-flop is a refinement of the RS flip-flop.

The indeterminate state (when R=S=1) of the RS type is defined in the JK type. In that conditionthe state of the output is changed; i.e. the complement of the previous state is available. In otherwords, if the previous state of the output Q is 0; it becomes 1; and vice versa. This can be writtenas nQQn ?? 1 .

The logic diagram of a clocked JK flip-flop is shown in Fig. Inputs J and K behave likeinputs S and R to set and reset the flip-flop. Note that in a JK flip-flop, the letter j is for set andthe letter K is for reset.

Fig. shows the logic symbol for JK flip-flop and its truth table is shown in the Fig. Note that theRS flip-flop is converted into JK flip-flop by making Q J S ?? and

Q K R ?

Logic Symbol

Inputs Outputs

CLK J K Q0

0001

0

0110

0

1010

No Change

( HOLD)

11

01

10

01

10

1 1 1 Toggle

QJ

K

CLK

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J K M ASTER-SL AVE FL I P-FL OP:

In the operation of a JK flip-flop, it is very difficult to satisfy the requirements, whichshould be fulfilled to avoid the racing condition, when both the data inputs are at High. The

practical approach to overcome this problem is to use Master-slave JK flip-flop. The Logicdiagram of a master-slave JK flip-flop is shown in Fig. which contains two clocked flop-flops.

One flip-flop serves as a MASTER and the other as a SLAVE; and overall circuit is known asMaster-Slave flip-flop. Whenever the clock is HIGH, the master is active. According to thestate of the data inputs, The output of the master is set or reset. At this stage, the slave is inactiveand its output remains in the previous state. Whenever the input clock is LOW, then the masteris inactive and the slave is active. Note that final output of the master-slave flip-flop is the outputof the slave flip-flop. Hence the final output of the master-slave flip-flop is available at the endof a clock pulse.

T (TOGGLE) FLIP-FLOP:

The single input version of the JK flip-flop is T (toggle) flip-flop and it is obtained

from a JK flip-flop if both inputs are tied together. The name T comes from the ability of theflip-flop to toggle or change the state. Generally T flip-flop ICs are not available. It can berealized using JK, SR, or D flip-flop.

Fig 1. shows the logic diagram of a clocked T flip-flop; which has only one inputreferred to as T-input.

Truth table

CLK I/P(T) O/P(Q)

0101

0011

Qn No change No change

Toggle

CLK

Q

Q

TT

CL

Fig 1.Logic

MASTER FLIP-FLOP

SLAVE

FLIP-FLOP CLK

J

K

LOGIC DIAGRAM OF MASTER-SLAVE J-K FLIP-FLOP

Q Q

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DATA

Clk

CIRCUIT DIAGRAMS:

S R Flip Flop

J - K Flip Flop

T Flip flop D Flip flip

1

2

4

5

Q

Q

S

R

Clk

SR Latch12

13

10

9

11

8

3

6

J Q

K Q

S Q

R Q

DATA

Clk

S

R L a t c

h

3

5

4

910

11

6

8

Q

Q

J

K

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Experiment No:7SAMPLING GATES

AIM: To observe the output of the Unidirectional diode gate for different Control InputVoltages

APPARATUS: 1. Resistors 1k ? -22. Capacitor - 10 ? F3. 1N4007 Diode4. Bread board5. CRO (1Hz-20MHz)6. Function generator (1Hz-1MHz)- 2

THEORY :Unidirectional Diode Gates:

At point A receives both the signal V s and the control input V c we observe here thatwhile the input signal V s is capacitively connected to A, the control input V c is directly coupled.The net signal at point A can be determined by employing superposition theorem .A carefulinspection indicates that the input signal V s is passing through a high pass filter and the controlinput V c is passing through a low pass filter to reach point A

It can be seen that the input to the sampling gates has a low duty cycle pulse train. Thewidth of the control pulse is large compared to input pulse width .The diode in the samplingcircuit is less reverse biased when the control input rises to its higher voltage level V 2.However the diode is forward biased only during the narrow input signal Vs reaches point A.The input pulse that lies with in the duration of the control pulse is transmitted through thediode as output .The effect of the level V 2 on the output of the gate waveform can be seen infig 2 .In fig 2.a we have V 2 = -5V and for a 10V input pulse; a 5V pulse appears as output.

Operation in this manner is advantageous when the bottom line of the input signal has a noisesignal surrounding it This would enable us to choose a noise threshold appears at the output.When used in this manner , the circuit is referred to as a threshold gate .In fig 2-b V 2 = 0 andthe entire input pulse is transmitted to the output , whereas in fig 2-c V 2 is positive and thesignal appears super imposed on a 5V pedestal

We have to remind the reader that the waveforms shown above are unrealistic as they donot take the effects of the high pass filter and the low pass filter mentioned at the beginning ofthis section .We are quite aware of the fact that R 1C1 networks constitutes an integrator to thecontrol input V c .As a consequence , the control input at A would be rising exponentially andexponentially falling at a similar rate .The rates and fall are controlled by the time constant R 1C1

The above discussion makes it clear that this form of a sampling gate is not particularlysuitable for selecting a portion of a continuous waveform .However when the input signal is ashort pulse whose duration is clearly smaller than the width of the control input , the

performance of the gate is acceptable .

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Fig.1 Unidirectional Diode Gate

Fig .2 Effect of control voltage on the output waveform

CIRCUIT DIAGRAM

Unidirectional Diode Gate

Signalin ut

controlin ut

R 1 R L V0

C1

Signalinput

controlin ut

R 1 R L V0

C1

Signalinput

Output Output

Output

Pedestal

Gatinginput

5V

0V

-5V

-15V

-V2

-V1

- V2

-V2

10V15V

a) Output waveform when V 2 is negative

b) Output waveform when V 2 is zero

c) Output waveform when V 2 is positive

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Procedure:1. Connect the circuit as shown in the circuit diagram.2. Connect the signal generator at the signal input with a frequency of 10KHz , 10Vp-p . 3. Connect the another signal generator at the control input with a frequency of 1KHz ,

-10Vp-p . 4. Vary the control input voltage and observe the output for different control input voltages

say 0V, -5V & -10V

MODEL GRAPH:

Questions:

1. What is sampling gate?2. Sketch the simple diode Unidirectional sampling gates that functions as a coincidence

gate3. Write some applications of sampling gate?4. Write short notes on four diode bi- directional diode sampling gate?

Signalin ut

Output OutputOutput

Pedestal

Gatinginput

5V

0V

-5V

-15V

-V 2

-V1

-V2

-V2

10V15V

a) Output waveformwhen V 2 is negative

b) Output waveformwhen V 2 is zero

c) Output waveformwhen V 2 is positive

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Experiment No:8

ASTABLE MULTIVIBRATOR

AIM : a) To design an Astable Multivibrator to generate clock pulse for a given frequency and obtain the wave forms and test its performance.

COMPONENTS REQUIRED:1. Resistors2. Capacitors 0.1 ? f 2 No.s3. Transistors 2N2369 2 No.s

APPARATUS :1. CRO 1Hz-20MHz 1No.2. Power supply 0-30V 1 No3. Bread board4. Connecting wires

THEORY: An Astable mu lti vibrator has two quasi-stable states, and it keeps on switchi ng between

these two states, by itself , No external tri ggeri ng signal is needed. Th e astable mul tivi bratorcannot r emain in defi ni tely i n any of these two states. The two ampli fi ers of an astablemul tivibrator are regeneratively cross-coupled by capacitor.

Principle:A collector-coupled astable multivibrator using n-p-n transistor in figure 1. The working

of an astable multivibrator can be studied with respect to the figure1.

Figure:1Let it be assumed that the multivibrator is already in action and is oscillating i.e.,

switching between the two states. Let it be further assumed that at the instant considered, Q 2 isON and Q 1 is OFF .

i) Since Q 2 is ON, capacitor C 2 charges through resistor R C1 . The voltage across C 2 is V CC .

RC 1 RC 2 R 2 R 1

C 2 C 1

2N23692N2369

VCC 12V

Q 1 Q 2

A B

C D

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ii) Capacitor C 1discharges through resistor R 1, the voltage across C 1 when it is about to startdischarging is V CC .(Capacitor C 1 gets charged to V CC when Q 1 is ON).

As capacitor C 1 discharges more and more, the potential of point A becomes more andmore positive (or less and less negative), and eventually V A becomes equal to V ? , the cut involtage of Q 1. For V A > V ?, transistor Q 1 starts conducting. When Q 1 is ON Q 2 becomes OFF.

Similar operations repeat when Q 1 becomes ON and Q 2 becomes OFF.

Thus with Q 1 ON and Q 2 OFF, capacitor C 1 charges through resistor R C2 and capacitorC2 discharges through resistor R 2. As capacitor C 2 discharges more and more , it is seen that the

potential of point B becomes less and less negative (or more and more positive), and eventuallyVB becomes equal to V ?, the cut in voltage of Q 2. when V B > V ?, transistor Q 2 starts conducting.When Q 2 becomes On, Q 1 becomes OFF.

It is thus seen that the circuit keeps on switching continuously between the two quasi-stable states and once in operation, no external triggering is needed. Square wave voltage aregenerated at the collector terminals of Q 1 and Q 2 i.e., at points C and D.

DESIGN:

IC max = 5 mA ; V CC = 12 V; V CE (SAT) = 0.2V

R C = (V CC - V CE(SAT) ) / I C MAX

Let C = 0.1 ? f and R= 10K ?

T = 0.69 (R 1C1+R 2C2) = 0.69(2RC) ( R 1=R 2 ; C 1=C 2)

=TON+T OFF

PROCEDURE:

1. Connect the circuit as shown in figure 1.2. Observe the waveforms at V BE1 , VBE2 , V CE1 , V CE2 and find frequency.3. Vary C from 0.01 to 0.001 ? F and measure the frequency at each step.4. Keep the DC- AC control of the Oscilloscope in DC mode.

?

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EXPECTED WAVEFORMS:

Q 1 OFF, Q 2 ON Q 1 OFF, Q 2 ON

Q 1 ON, Q 2 OFF Q 1 ON, Q 2 OFF

Figure 2

OBSERVATIONS:T ON (Theoritical) = 0.69RC = T OFF (Theoritical) = 0.69RC =

T(T ON + T OFF ) (Theoritical) = 1.38 RC =

T ON (practical) = T OFF (practical) = T(T ON + T OFF ) (practical) =

QUESTIONS :

1. What is a switching circuit?2. Justify that the Astable Multivibrator is a two stage RC coupled Amplifier using

negative feedback. How does it generate square wave.3. What is the difference between a switching transistor and an ordinary transistor?4. What is the effect of slew rate on the working of an Op-amp Multivibrator?

CONCLUSION:Conclusion can be made on time period of the output waveforms of the Astablemultivibrator theoretically and practically and output waveforms of the multi vibrator areidentical or not when compared with the theoretical wave forms.

VC 1 t

VC 2 t

VB 1 t

VB 2 t

VCE (SAT )

VCE (SAT )

VCC

V??

V??

VCC

I.R ?C

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Experiment No:9

MONOSTABLE MULTIVIBRATOR

AIM : To design a monostable multivibrator to generate clock pulse for a given frequency and obtain the waveforms and test its performance

Components Required:1. Resistors2. Capacitors.3. Transistors 2N2369 2 No.s

Apparatus Required:1. CRO 1Hz-20MHz 1 No.2. Power supply 0-30V 1 No.3. Bread board4. Connecting wires

CIRCUIT DIAGRAM:

Figure-1

THEORY :A monostable multivibrator has only one stable state, the other state being quasi-

stable. Normally the multivibrator is in the stable state, and when an external triggering pulse isapplied, it switches from the stable to the quasi-stable state. It remains in the quasi-stable statefro a short duration, but automatically reverts i.e. switches back to its original stable state,without any triggering pulse.

RC 1 RC 2 R=10KO

R 1

C=0.1 ? F

2N23692N2369

VCC = 6V

-V BB -1.5V

R 2

Q 1 Q 2

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Principle of operationA collector-coupled Monostable multivibrator of the two transistors Q 1 and Q 2, Q 1 is

normally OFF and Q 2 is Normally ON. Resistor R 1 and R 2 are connected to the normally OFFtransistor, and the capacitor C is connected to the normally ON transistor.

It is seen from the circuit of the monostable multivibrator that, under normal conditions,the supply voltage V

CC provides enough base drive to the transistor Q

2 through resistor R, with

the result that Q 2 goes into saturation. With Q 2 ON, Q 1 goes OFF, as already studied in thecontext of binary operation.

With Q 2 ON and Q 1 OFF, the capacitor finds a charging path. The voltage across thecapacitor is V CC with polarity. It is obvious that in the stable state of the multivibrator, Q 2 is ONand Q 1 is OFF.

If the negative triggering pulse is applied to the collector of Q 1, it is transmitted to the base of Q 2 through the capacitor, and hence makes the base of Q 2 negative. Immediately Q 2 goesOFF and Q 1 becomes ON. However, this is only a quasi-stable state as is obvious form thefollowing observation.

With Q 1 ON and Q 2 OFF, the capacitor C finds a discharging path. As the capacitordischarges, it is seen that the potential at the base of the transistor Q 2 becomes less and less

negative, and after a time, we have V B = V ?, the cut-in-voltage of Q 2.As soon as V B crosses the level of V ?, Q 2 starts conducting and gets saturated.

When Q 2 becomes ON, Q 1 becomes OFF. Thus the original stable state of the multivibrator isrestored.

[ In quasi-stable state: Q 1 is ON and Q 2 is OFF] The interval during which the quasi-stable state of the multivibrator persists i.e., Q 2

remains OFF is dependent upon the rate at which the capacitor C discharges. This duration of thequasi-stable state is termed as delay time or pulse width or gate time. It is denoted as T. Thewave forms of the voltage at base of the transistor Q 2 and C (Collector of Q 1)

DESIGN:VCE = 5.56v, V CC = 6v, V CE(sat) = 0.3v, V BE(sat) , = 0.7v, I C = 6mA,V F = -0.3vRc = (V CC V CE(sat) )/IC.

C

C sat BE

C

CC CE R R

RV

R R RV

V ?

??

?

1

)(

1

1

Find the values of R 1 and R 2Theoretical gate width T with Q 1 in saturation = 0.69RC

PROCEDURE:1. Connect the circuit as shown in figure.2. With the help of a triggering circuit and using the condition T (trig) >

T(Quasi) a pulse waveform is generated.3. The output of the triggering circuit is connected to the base of the off

transistor.4. The Off transistor goes into ON state.5. Observe the waveforms at V BE1 , VBE2 , V CE1 , V CE26. Keep the DC- AC control of the Oscilloscope in DC mode.7. Compare the theoretical and practical gate widths.

21

2)(

21

1

R R

RV

R R RV

V sat CE BB F ??

?

??

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VC 2

t

VB 2 t

VC 1 t

VB 1 t

I.R ?C

EXPECTED WAVEFORMS:Q 2 OFF, Q 1 ON Q 1 OFF, Q 2 ON

Q 2 ON, Q 1 OFF

Figure 2

OBSERVATIONS:

T ON (Theoritical) = 0.69RC =

T ON (practical) =

QUESTIONS:

1. Explain the operation of collector coupled Monostable Multivibrator?2. Derive the expression for the gate width of a transistor Monostable Multivibrator?3. Give the application of a Monostable Multivibrator.

CONCLUSION:Conclusion can be made on time gate width T of the monostable multivibratortheoretically and practically and output waveforms of the multi vibrator are identical ornot when compared with the theoretical wave forms.

V CC

VCE (SAT)

VCE (SAT)

V ??

V ??

VCC

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Experiment No:10

BISTABLE MULTIVIBRATOR

AIM: To design a fixed bias Bistable Multivibrator and to measure the stable statevoltages before and after triggering.

COMPONENTS REQUIRED:1. Resistors2. Transistors 2N2369 1 No.

APPARATUS: 1. Bread board2. Power supply 0-30V 1 No.3. CRO 1Hz-20MHz 1 No.4. Connecting wires5. Digital Multimeter

THEORY:

A bistable multivibrator has two stable output states. It can remain indefinitely in anyone of the two stable states, and it can be induced to make an abrupt transition to the other stablestate by means of suitable external excitation. It would remain indefinitely in this stable state,until it is again induced to switch into the original stable state by external triggering.

Bistable multivibrators are also termed as Binarys or Flip-flops . A binary is sometimesreferred to as Eccles-Jordan Circuit .

RC 1 RC 2 R 1

Q 2

+V CC

Q 1

R 2 R 2

R 1

-VBB

A B

C D

I I 2

Figure 1

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Principle of Operation of bistable multivibrator.

Consider the circuit as shown in the figure.1. The transistor Q 1 and Q 2 are n-p-ntransistors. They are coupled to each other as shown in figure 1. It is evident that the output ofeach transistor is coupled to the input of the other transistor. Since the transistors are identical,there quiescent currents would be the same, unless the loop gain is greater than unity. When I 1 increases slightly, the voltage drop across the collector resistance RC1 increases. Since V CC isfixed, the voltage of point C decreases. This has the effect of decreasing the base current of Q

2.

This, in turn, decreases the collector current of Q2 viz. I 2 decreases, the voltage drop I 2 RC2 decreases. Hence the voltage of point D increases.

Due to increase of V D, the base current of Q1 increases. This increases the collectorcurrent of Q1 viz I 1. Thus I 1 further increases. I 1 RC1 drop further increases, V C further decreases,the base current of Q2 further decreases, with the result that I 2 further decreases. Thus it caneasily seen that if the collector current I 1 increases even marginally, I 2 would go on progressivelydecreasing and as a result, I 1 would progressively increase. Eventually I 2 would become

practically zero, cutting off the transistor Q2, at the same time transistor Q1 would conductheavily with the result that it would be driven into saturation. Thus Q2 becomes OFF and Q1

becomes ON. It can similarly be shown that if I 2 increases even marginally similar sequence ofoperation would result and ultimately Q2 would be ON and Q1 OFF. Thus when Q1 is ON, Q2 is

OFF and when Q1 is OFF Q2 is ON.

CIRCUIT DIAGRAM:

Figure: 2

RC 12.2KO

RC 22.2KO

R 1 15KO

2N23692N2369

V CC 12V

-V BB = -1.5V

R 1 15KO

R 2

1 0 0 K O

R 2

1 0 0 K O

Q 1 Q 2

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PROCEDURE:

1. Connect the circuit as shown in figure 2.2. Observe the waveforms at V BE1 , V BE2 , V CE1 , V CE2 using CRO & multimeter 3. Observe the voltages at V C1 and V C2 . 4. If V

C1= V

CE(Sat) and V

C2=V

CC(Approximately) then Q1 is ON and Q2 is OFF

Otherwise V C1= V CC (Approximately) and V C2= V CE(Sat) ) then Q1 isOFF and Q2isON.

5. Observe which transistor is in ON state and which transistor is in OFF state. andobserve the voltages V C1 , V C2, V B1, and V B2.

6. Apply ve triggering at the base of the ON transistor and observe the voltages V C1 ,VC2 , V B1 , and V B2.

EXPECTED WAVEFORMS:

OBSERVATIONS:

Before Triggering : When Q1 is ON and Q2 is OFF

After Triggering: When Q1 isOFF and Q2 isON.

QUESTIONS:1. What is Multivibrator? Explain the principle on which it works? Why is it called a

binary?2. Explain the role of commutating capacitors in a Bistable Multivibrator?3. Give the Application of a Binary.

VBE1 VBE2 VCE1 VCE2 Stable state Voltages

VBE1 VBE2 VCE1 VCE2 Stable state Voltages

t

V o

l t a g e

VC1

VC2

Before Triggering

t

V o

l t a g e

VC1

VC2

After Triggering

0 0

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CONCLUSION:Conclusion can be made on which transistor is ON and which transistor isOFF before triggering and after triggering.

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THEORY:

The most important application of Schmitt Trigger circuit are amplitude comparator andsquaring circuit are amplitude comparator and squaring circuit. The circuit is used to obtain asquare waveform from any arbitrary input waveform. The loop gain is to be less than unity.

If Q2 is conducting there will be voltage drop across R Z which will elevate the emitter ofQ

1. Consequently if V is small enough in voltage, Q

1 will be cut-off with Q

1 conducting, the

circuit amplifies and since the gain is positive, the output to rise, V 2 continues to fall and Z 2 continues to rise. Therefore a value of V will be reached where Q2 is turned OFF. At the pointthe output no longer responds to the input.

Here the input signal is arbitrary except that it has large enough excursion to carry input beyond the limits of hysteresis range, V H = (V 1 V 2 ).

The output is a square wave whose amplitude is independent of the amplitude of theinput waveform.DESIGN: Given UTP=5V,LTP=3V

IC2 = 5mA(Rc 2 + R E) = V CC / IC2U.T.P = V E2 = 5VVE2 = (R E ? VCC ) / (Rc 2+R E)I2 = 0.1 ? IC2 L.T.P = V E1 = 3VR 2 = E R2i / I 2 = V E1 / I 2 = L.T.P / I 2 Rc1 = {(R E? VCC) / V E1} R EIB2 = I C2 / hfe(min)(VCC - V E2) / (R 1+R c1))) = (V E2/R 2)+I B2 R B = (h fe? R E) / 10Find R 1, R 2, R E, Rc 1and Rc 2 from the above equations

PROCEDURE:

1. Connect the circuit as shown in figure 1 with designed values.2. Apply V CC of 12V and an input frequency of 1KHz with an amplitude more than the

designed UTP.3. Now note down the output wave forms4. Observe that the output comes to ON state when input exceeds UTP and it comes to OFF

state when input comes below LTP5. Observe the waveforms at V C1 , V C2 , V B2 and V E and plot graphs.6. Keep the DC- AC control of the Oscilloscope in DC mode.

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Experiment No: 12

UJT RELAXATION OSCILLATOR

AIM : To obtain a saw tooth waveform using UJT and test its performance as anoscillator

APPARATUS :

1. Resistors 47k ? , 100 ? 2. Capacitor - 0.1 ? F3. 2n2646 UJT4. Bread board5. Power supply (0-30V)6. CRO(1Hz-20MHz)

THOERY :

A Unijunction transistor (UJT), as the very implies, has only one p-n junction, unlike a BJT which has two p-n junctions.

The equivalent circuit of the UJT is as shown in figure 1.

R B1 is the resistance between base B1 and the emitter, and it is basically a variableresistance, its value being dependent upon the emitter current I E .

R B2 is the resistance between base B2 and the emitter, and the value is fixed.Consider the circuit as shown in figure 1.Let I E = 0 . Due to the applied voltage V BB a current I results as shown.

VBB

V1 VE

IE

R B2

R B1

+

-Figure:1

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V P = V ? + ? V BB

??

???

??

?? 0,when

21

1 E

B B

B I R R

R?

We have V 1 = iR B1.

But21 B B

BB

R RV i ?

?

? 121

1 B B B

BB R R R

V V ??

?

????

?

??

BB B B

B V R R

R???

????

?

??

21

1

The ratio ???

????

?

?21

1

B B

B

R R R

is termed as the in tri nsic stand

off ratio and it is denoted as?

. ? BBV V ??1 .

Form the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltageV E = V ? + V 1, where V ? is the cutin voltage of the diode.

This value of the emitter voltage which makes the diode conduct is termed as peakvoltage , and it is denoted as V P .

We have V E = V ? + V 1,or since V 1 = ? V BB.

It is obvious that if V E < V P , the UJT is OFF, andif V E < V P , the UJT is ON.

Figure 3. shows the emitter characteristics of a UJT (plot of V E vs I E )

Figure 3.

R B2

R B1

VBB

V1 i

Figure 2.

0 I P I V I

V

V

V

Peak Point

Valle Point

Negativeresistance

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R B2

R B1

R

C Vs

-

V or V BB

B2

B1

E

The main application of UJT is in switching circuits wherein rapid discharging ofcapacitor is very essential.

Having understood the basic of UJT, we shall next study the working of UJT relaxationoscillator.

Worki ng of UJT r elaxation oscill ator (OR UJT sweep circui t)

Figure:4

The UJT sweep circuit shown in the figure 4 consists of a UJT, a capacitor and a resistorarranged as shown.

We studied that a UJT is OFF as long as V E < V P , the peak voltage. Hence initially whenthe UJT is OFF, the capacitor C charges through the resistance R from the supply voltage V .

Let V S = capacitor voltage.It is seen that when the capacitor voltage V S rises to the value V P the UJT readily

conducts. When the UJT becomes ON, the capacitor discharges and its voltage falls. When thevoltage falls to the valley point V V , the UJT becomes OFF and the capacitor charges again to V P .

This cycle of charging and discharging of the capacitor C repeats, and as a result, a sawtooth wave form of voltage across C is generated.

CIRCUIT DIAGRAM :

1. Emitter 2. Base1 3. Base2 Figure:5

V CC =12VR 1

C

B2

B1

E47k ?

0.1 ? F

R 2 100 ?

2N2646

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Experiment No:13

BOOT STRAP SWEEP CIRCUIT

AIM: To design a bootstrap sweep circui and test its performan .

Components Required:1. Resistors 100k ? , 5.6k ? , 10 k ? 2. Capacitors 0.1 ? F, 10 ? F, 100 ? F3. IN4007 Diode4. 2N2369 Transistors 2

Apparatus Required:1. Bread board2. Power supply(0V-30V)3. CRO(1Hz-20MHz)4. Signal generator(1Hz-1MHZ)5. Connecting Wires.

CIRCUIT DIAGRAM

Figure

DESIGN:

RC

T V V g CC S

??

?? ?)/1()/(

/)( R Rh

V V C T

B fe

CC S R ?

??

Sweep time = T S = RC

-V BB =-10V

10F

VCC = 12V

100F

0.1F

100K ? 5.6K ?

10K ?

IN4007

2N2369

V 0 V i

2N2369

1

Q 2

Functiongenerator

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Q1UESTIONS:1. Describe the operation a single transistor Boot strap time base voltage waveform generator

making use of its related circuit diagrams?2. Explain the principle of working of Boot strap circuit?

Conclusion:Conclusions can be made on swee4p time Ts and retrace time T R and sweep voltage Vs of thesweep waveform theoretically and practically and also made on if the output waveform of theBootstrap are identical with the theoretical wave forms or not.

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Experiment No:14

SYNCHRONIZATION OF A UJT RELAXATION OSCILLATOR

AIM : To obtain synchronization and f requency division of a UJ T r elaxation oscill ator byapplying negative pulse at base 2 of UJT and pl ot the wavefor ms

APPARATUS :

1. Resistors 47k ? , 100 ? , 330 ? 2. Capacitor - 0.1 ? F, 10 ? F3. 2n2646 UJT4. Bread board5. Power supply 0-30V6. CRO (1Hz-20MHz)7. Function generator (1Hz-1MHz)

THOERY

A Unijunction transistor (UJT), as the very implies, has only one p-n junction, unlike a BJT which has two p-n junctions.

The equivalent circuit of the UJT is as shown in figure 1.

R B1 is the resistance between base B1 and the emitter, and it is basically a variable resistance, itsvalue being dependent upon the emitter current I E .

R B2 is the resistance between base B2 and the emitter, and the value is fixed.Consider the circuit as shown in figure 1.Let I E = 0 . Due to the applied voltage V BB a current I results as shown.

VBB

V1 VE

IE

R B2

R B1

+

-Figure:1

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V P = V ? + ? V BB

??

???

? ??

? 0,when21

1 E

B B

B I R R

R?

We have V 1 = iR B1.

But21 B B

BB

R RV i ?

?

? 121

1 B B B

BB R R R

V V ??

?

????

?

??

BB B B

B V R R

R???

????

?

??

21

1

The ratio ???

????

?

?21

1

B B

B

R R R

is termed as the in tri nsic stand

off ratio and it is denoted as ? .?

BBV V ??

1 .

Form the equivalent circuit, it is evident that the diode cannot conduct unless the emitter voltageV E = V ? + V 1, where V ? is the cutin voltage of the diode.

This value of the emitter voltage which makes the diode conduct is termed as peakvoltage , and it is denoted as V P .

We have V E = V ? + V 1,or since V 1 = ? V BB.

It is obvious that if V E < V P , the UJT is OFF, andif V E < V P , the UJT is ON.

Figure 3. shows the emitter characteristics of a UJT (plot of V E vs I E )

Figure 3.

R B2

R B1

VBB

V1

i

Figure 2.

0 I P I V I

V

V

V

Peak Point

Valle Point

Negativeresistance

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The main application of UJT is in switching circuits wherein rapid discharging of capacitor isvery essential.

Having understood the basic of UJT, we shall next study the working of UJT relaxationoscillator.

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R B2

R B1

R

C Vs

+

-

V or V BB

B2

B1

E

Worki ng of UJ T r elaxation oscil lator (OR UJT sweep circuit)

Figure:4

The UJT sweep circuit shown in the figure 4 consists of a UJT, a capacitor and a resistorarranged as shown.

We studied that a UJT is OFF as long as V E < V P , the peak voltage. Hence initially when

the UJT is OFF, the capacitor C charges through the resistance R from the supply voltage V .

Let V S = capacitor voltage.It is seen that when the capacitor voltage V S rises to the value V P the UJT readily

conducts. When the UJT becomes ON, the capacitor discharges and its voltage falls. When thevoltage falls to the valley point V V , the UJT becomes OFF and the capacitor charges again to V P .

This cycle of charging and discharging of the capacitor C repeats, and as a result, a sawtooth wave form of voltage across C is generated.

Synchronization and frequency division of UJT:The synchronization principle of UJT is shown in fig (a)

Synchronization to an external signal is possible because this signal may be introduced at thesync terminal in such a a manner as to change the peak voltage V p .Thus in the UJT a negative

pulse applied at B2 as shown in fig (b) will lower V p ,whereas in the SCS , the thyristor and thethyraton a positive pulse applied at the gate , the base , or the grid will serve the same purposeThe situation which results when synchronizing pulses are applied shown in fig c.The effect ofthe sync pulse is to lower for the duration of the pulse , the peak or break down voltage asindicated .A pulse train of regular space is shown starting at an arbitrary time t = 0

The first several pulses have no influence on the sweep generator , which continues to rununsynchronized .Eventually however the exact moment at which the negative resistance devicegoes ON is determined by the instant of occurrence of a pulse as is also each succeeding

beginning of the ON interval .From the point on the sweep generator runs synchronously withthe pulses

In order that synchronization may result , it is necessary that each pulse shall occur at a timewhen it may serve to terminate the cycle prematurely .This requirement mean that the interval

between pulses , T p must be less than the natural period, T o, of the sweep generator .in fig (d)thecase in which T p>T o .Here synchronization of each cycle does not occur . The pulses do serve toestablish that four sweep cycles shall occur during the course of 3 pulse periods, butsynchronization of this type is normally of no value .Even if the requirement T p

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synchronization cannot result unless the pulse amplitude is at least large enough to bridge thegap between the quiescent breakdown voltage V c. In fig (e) have the case T p is less than T o asrequired but the pulses amplitude is too small and again synchronization does not result

a) A sweep generator

1. Emitter 2. Base1 3. Base2

Fig (b)

c)an initially unsynchronized generator falls into synchronization shortly after the application ofsynchronizing pulses

Vc o/p

R 1

B2

B1

E47k ?

0.1 ? F

R 2 100 ?

2N2646

330 ?

10 ? F

VBB =12v

ViFunctiongenerator

Vi S VcC+

-

+

-

R

VYY

VC TP

t=T

Vv , valley or maintaining voltage

To

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d) illustrating that for synchronization to result ,Tp must less than To;

e) illustrating failure of synchronization due to inadequate amplitude of sync pulses

2 1 2 1 2 1 2

f) frequency division by a factor of 2 in a sweep generator

CIRCUIT DIAGRAM

Vc o/p

R 1

B2

B1

E47k ?

0.1 ? F

R 2 100 ?

2N2646

330?

10 ? F

VBB =12v

ViFunctiongenerator

TP

To

TP

To

Tp

Tp

Ts

To

V

V

Vs

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PROCEDURE:1. Connect the circuit as shown in circuit diagram2. Note down the voltage V

s and time period T

o across the capacitor c without

giving external sync pulses3. Now apply external negative sync pulses to the Base2 of UJT4. Now adjust the amplitude and time period T p in such a way T p

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Experiment No:15

STUDY OF LOGIC GATES USING INTEGRATED CIRCUITS

AIM : To study the various logic gates by using digital integrated circuits

COMPONENTS:1. IC 74LS00,2. IC 74LS02,3. IC 74LS04,4. IC 74LS08,5. IC 74LS10,6. IC 74LS32,7. IC 74LS86.8. Digital IC trainer kit. 9. Patch cards

THEORY:

The logical operations involved in Boolean algebra are OR, AND, NOT. Theseoperations are involved in the design of digital systems. These functions are performed by anelectronic circuit known as gate, such as OR gate, AND gate and NOT gate. These logic gatesare the basic building blocks of digital systems.

NOT gate:

A NOT gate has only one input and one output. It performs a basic logic function calledinversion or complementation. In this logic function, when a High level is applied to this gateas input, a low level will appear on its output. When a low level is applied to its input, a High

level will appear on its output. Thus in the logic function, the output of this gate is thecomplement of the input.

AND gate:

AND gate performs logical multiplication. The operation of this gate is such that theoutput is high only when all the inputs are high. When any of the inputs are low, the output islow. The AND gate is composed of two or more inputs and a single output. Fig shows the logicsymbol for a AND gate with two inputs A and B, and the output Y.

A

BY=A.B

SYMBOL

A Y= A

Symbol

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A

B

Y = A.B B AY .?

A

B B AY .?

OR gate:

An OR gate has two or more inputs and one output. The operation of OR gate is suchthat a High on the output is produced when any of the inputs are High. The output is low onlywhen all of the inputs are low. Fig. shows the logic symbol for an OR gate with two inputs Aand B and the output Y.

NAND gate :

The term NAND is a contraction of NOT-AND and implies an AND function with aninverted (NOT) output. The operation of this gate can be analyzed, using an equivalent circuitshown in fig. Which has an AND gate followed by an inverter (NOT). If the inputs are A and B,

then the output of AND gate is A.B and complement of this is B A B A ??.

SymbolNOR gate:

The term NOR is a contraction of NOT-OR and implies an OR function with an inverted(NOT) output. The operation of this gate can be analyzed using an equivalent circuit, shown inFig. Which has an OR gate followed by an inverter (NOT). If the inputs are A and B, then theoutput of OR gate is A + B, and complement of this is

NAND and NOR gates are very popular logic gates because they have a Universalfunction, i.e., they can be used to construct an AND gate, an OR gate, a NOT gate or anycombination of these functions. Hence NAND and NOR gates are known as Universal gates.

A

1Y = A + B

SYMBOL

A

B

Y = A + B B AY ??

A

B B AY ??

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SymbolExclu sive-OR gate:

Exclusive-OR operation is not a basic operation. It can be performed by using either basic gates or Universal gates. Exclusive-OR gate, abbreviated as XOR or EX-OR. The outputexpression for the circuit is . B A B AY ?? Fig. shows a standard symbol for EX-OR gate, Notice

that the output is High only when the two inputs must be different to get a High output.

SymbolPIN CONFIGURATIONS:

NAND GATE IC NOR GATE IC

NOT GATE IC AND GATE IC

3-INPUT NAND GATE IC OR GATE IC

B B AY ??

A

VCC

Gnd

74LS02

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS32

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS00

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS08

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS86

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS04

814 13 12

73 4 5 6

11 10 9

1 2

VCC

Gnd

74LS10

814 13 12

73 4 5 6

11 10 9

1 2
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EX-OR GATE IC

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Tabular forms:

AND Gate OR Gate NAND Gate NOR Gate EX-OR GateA B Y A B Y A B Y A B Y A B Y001

1

010

1

001

1

010

1

001

1

010

1

001

1

010

1

001

1

010

1

3 Input NAND gate NOT Gate

Digital circuit can be classified into two types. These are combinational and sequentiallogic circuits. The logic circuits, in which their outputs at any instant of time may depend uponthe inputs present at that time, are known as combinational logic circuits. The combinationallogic circuit which includes memory elements in its feed back path is known as sequential logiccircuits. The outputs in a sequential circuit are a function not only of inputs but also of the

present state of the memory elements. Flip-Flops are the basic building blocks for the sequentiallogic circuits.

The basic digital memory circuit is known as Flip-flop. It has two stable states which areknown as the 1 state and the 0 state. It can be obtained by using NAND or NOR gates.

PROCEDURE:

1. Place the IC on the bread board in the Digital Trainer Kit.2. Connect the VCC and Ground to pin number 14 and & 7 respectively.3. Verify the truth table by giving the inputs and observing the output for each gate in

the given IC

QUESTIONS:1. What are the Universal gates?2. Design an AND gate using NAND gates?3 D i OR t i NOR t ?

A B C Y A Y00001111

00110011

01010101

01
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