May 8, 2001 2

Peripheral Design Options For USB 2.0

Solutions

Peripheral Design Options For USB 2.0

SolutionsDave ThompsonDave Thompson

Manager of High Speed I/O DevelopmentManager of High Speed I/O Development

Agere Systems,Agere Systems,

davethompson@agere.comdavethompson@agere.com

May 8, 2001 3

Concept to Production with USB 2.0Concept to Production with USB 2.0

Product Prototyping PhaseProduct Prototyping Phase– Get something to work!Get something to work!– Advanced prototyping optionsAdvanced prototyping options– What are the best ways to optimize?What are the best ways to optimize?

Four options will be presentedFour options will be presented

Mass Production PhaseMass Production Phase– Lowest possible overall cost structureLowest possible overall cost structure

There May Be Two “Minimums”There May Be Two “Minimums”

May 8, 2001 4

Product Prototyping PhaseProduct Prototyping Phase

Important ElementsImportant Elements– Trusted Modular ComponentsTrusted Modular Components

USB 2.0 transceiver daughter cardUSB 2.0 transceiver daughter card PCI USB2.0 host adapter cardsPCI USB2.0 host adapter cards

– Analysis toolsAnalysis tools USB 2.0 bus protocol analyzerUSB 2.0 bus protocol analyzer Logic analyzer/traffic generatorsLogic analyzer/traffic generators

– Trusted hosts and peripheralsTrusted hosts and peripherals Multiple lab setups is desirableMultiple lab setups is desirable

– Software SupportSoftware Support Drivers; Apps; debug toolsDrivers; Apps; debug tools

May 8, 2001 5

USB2.0 Prototyping In ActionUSB2.0 Prototyping In Action

Agere USB2 Transceiver Daughter CardAgere USB2 Transceiver Daughter Card

May 8, 2001 6

Advanced USB 2.0 Prototyping OptionsAdvanced USB 2.0 Prototyping Options

USB 2.0 Transceiver MacrocellUSB 2.0 Transceiver Macrocell– Integrating analog circuits avoids issues laterIntegrating analog circuits avoids issues later– Demonstrated success at 480Mb/s signal ratesDemonstrated success at 480Mb/s signal rates

Metal programmable/Rapid turn chipsMetal programmable/Rapid turn chips– Standard digital logic options are easyStandard digital logic options are easy– NEW!--Could include integrated transceiversNEW!--Could include integrated transceivers

Board platforms for peripheral productsBoard platforms for peripheral products– Transceiver and processor basedTransceiver and processor based

Board level platforms for host productsBoard level platforms for host products– PCI based single chips or FPGA’sPCI based single chips or FPGA’s

May 8, 2001 7

UTMI Transceiver MacrocellUTMI Transceiver Macrocell

USB 2.0 (UTMI)http://developer.intel.com/technology/usb/spec.htmUSB 2.0 (UTMI)http://developer.intel.com/technology/usb/spec.htm Broad Industry support, discrete versions availableBroad Industry support, discrete versions available

ControlControlControlControlControlControl

D-D-

D+D+

DLLDLLDLLDLL

FSFSInterfaceInterface

HSHSInterfaceInterface

Shared LogicShared LogicShared LogicShared Logic

ParallelParallelInterfaceInterfaceParallelParallel

InterfaceInterfaceDLLDLLDLLDLL

muxmux

BitBitUnstufferUnstuffer

BitBitUnstufferUnstuffer DeseralizerDeseralizerDeseralizerDeseralizer RX HoldingRX Holding

RegRegRX HoldingRX Holding

RegReg

BitBitStufferStuffer

BitBitStufferStuffer SeralizerSeralizerSeralizerSeralizer TX HoldingTX Holding

RegRegTX HoldingTX Holding

RegReg

ToToSIESIE

DataData

ToToUSBUSB

May 8, 2001 8

John Hyde’s Typical ImplementationJohn Hyde’s Typical Implementation

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine

DeviceDeviceSpecificSpecific

LogicLogic

DeviceDeviceSpecificSpecific

LogicLogic

Endpoint Logic

Endpoint Logic

…SIE

Control Logic

USB 2.0USB 2.0Endpoint Logic

Device Device HardwareHardware

USB 2.0 USB 2.0 TransceiverTransceiver

USB 2.0 USB 2.0 TransceiverTransceiver

This is a minimal I/O DeviceThis is a minimal I/O Device Many Implementation OptionsMany Implementation Options Discrete versions availableDiscrete versions available

May 8, 2001 9

Option 1Option 1

Building USB 2.0 DevicesBuilding USB 2.0 Devices

Use a discrete UTMI transceiverUse a discrete UTMI transceiver– Has good TTM characteristicsHas good TTM characteristics– Concentrate on product functionConcentrate on product function

USB 2.0USB 2.0USB 2.0 USB 2.0 TransceiverTransceiver

USB 2.0 USB 2.0 TransceiverTransceiver

ControlControl

Data InData In

Data OutData Out

To BusTo BusDeviceDeviceSpecificSpecific

LogicLogic

DeviceDeviceSpecificSpecific

LogicLogicDevice

HardwareDevice

Hardware

UTMIInterface

UTMIInterface

May 8, 2001 10

Discrete UTMI TransceiverDiscrete UTMI Transceiver

Has to be a parallel interface on function sideHas to be a parallel interface on function side 8-bit parallel interface difficult to connect to8-bit parallel interface difficult to connect to

– Has to run at 60MHzHas to run at 60MHz– Hard to do with FPGAsHard to do with FPGAs– Pay attention to TxReady, Rx Valid & ValidHPay attention to TxReady, Rx Valid & ValidH

16-bit parallel interface severely pin constrained16-bit parallel interface severely pin constrained– Package cost dwarfs silicon costPackage cost dwarfs silicon cost– Easy to connect to (runs at 30MHz)Easy to connect to (runs at 30MHz)

Add functionality to increase silicon valueAdd functionality to increase silicon value– SIE, DMA, … but that limits scopeSIE, DMA, … but that limits scope

May 8, 2001 11

Discrete UTMI TransceiverDiscrete UTMI Transceiver

May 8, 2001 12

Option 2Option 2

Building USB2 DevicesBuilding USB2 Devices

Use a generic device controllerUse a generic device controller– Has good TTM characteristicsHas good TTM characteristics– Interfaces to product function with general purpose Interfaces to product function with general purpose

bus interfacebus interface– Quickly enables existing product to USB 2.0Quickly enables existing product to USB 2.0

US2820US2820Device Device cntrlrcntrlr

ProductProductFunctionFunction

USBUSBDevice Hardware

Device Hardware

General Purpose uP Interface

General Purpose uP Interface

May 8, 2001 13

Option 3Option 3

Building USB2 DevicesBuilding USB2 Devices

Use an Enhanced Device ControllerUse an Enhanced Device Controller– Flexibility with integrated uPFlexibility with integrated uP– Lower cost for high volume productLower cost for high volume product

USB2 Enhanced Device ControllerUSB2 Enhanced Device ControllerUSB2 Enhanced Device ControllerUSB2 Enhanced Device Controller

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface Engine

Microprocessor Microprocessor + Memory + + Memory +

DMA EnginesDMA Engines

Microprocessor Microprocessor + Memory + + Memory +

DMA EnginesDMA Engines

Endpoint Logic

Endpoint Logic

…SIE

Control Logic

USB 2.0Endpoint Logic

Device Hardware

USB 2.0 USB 2.0 TransceiverTransceiverUSB 2.0 USB 2.0

TransceiverTransceiver

May 8, 2001 14

Option 4Option 4

Building USB2 DevicesBuilding USB2 Devices

Full ASIC designFull ASIC design– Longer design/qualification timesLonger design/qualification times– Lowest cost for high volume productLowest cost for high volume product

ASICASICASICASIC

Serial Interface EngineSerial Interface EngineSerial Interface EngineSerial Interface EngineDeviceDevice

SpecificSpecificLogic Logic

+uP+memory+D+uP+memory+DMA EnginesMA Engines

DeviceDeviceSpecificSpecific

Logic Logic +uP+memory+D+uP+memory+D

MA EnginesMA EnginesEndpoint Logic

Endpoint Logic

…SIE

Control Logic

USB 2.0Endpoint Logic

Device Hardware

USB 2.0 USB 2.0 TransceiverTransceiverUSB 2.0 USB 2.0

TransceiverTransceiver

May 8, 2001 15

Decision Points for Mass ProductionDecision Points for Mass Production

When to use Integrated ASIC/ASSPWhen to use Integrated ASIC/ASSP– Minimum board part count is importantMinimum board part count is important– Familiar with ASIC/ASSP design flowsFamiliar with ASIC/ASSP design flows– Function can be added to existing ASIC/ASSPFunction can be added to existing ASIC/ASSP

When to use Standalone TransceiverWhen to use Standalone Transceiver– If integration risk is high--not so in USB 2.0If integration risk is high--not so in USB 2.0– Gives added debug points of observationGives added debug points of observation– Volume may not justify integrated solutionVolume may not justify integrated solution