Microtronix ViClaro IV-GX Video Host Board · 2018-11-28 · CYCLONE IV-GX FPGA The ViClaro IV Host...

4056 Meadowbrood Drive, Unit 126 London, ON, Canada N6L 1E3 www.microtronix.com

Microtronix ViClaro IV-GX

Video Host Board

USER MANUAL

REVISION 1.0

Page 2 of 40

This user guide provides basic information about using the Microtronix ViClaro

IV-GX Video Host Board. The following table shows the document revision

history.

Date Rev Description

Jan. 2013 1.0 Initial Release

E-MAIL

Sales Information: [email protected]

Support Information: [email protected]

WEBSITE

Software updates to the ViClaro IV-GX Video Host Board and supporting

Microtronix IP Cores are listed on the download page of our website and made

available via an email request form. Some product upgrades are only available

to customers who have purchased the ViClaro III kit.

The upload site is for sending files to Technical Support.

General Website: http://www.microtronix.com

Downloads Page: http://www.microtronix.com/downloads/

FTP Upload Site: http://microtronix.leapfile.com

PHONE NUMBERS

General: (001) 519-690-0091

Fax: (001) 519-690-0092

Document

Revision History

How to Contact

Microtronix

Path/Filename A path/filename

[SOPC Builder]$ <cmd> A command that should be run from within the Cygwin Environment.

Code Sample code.

Indicates that there is no break between the current line and the next line.

Typographic

Conventions

ViClaro IV-GX Video Host Board User Manual

Page 3 of 40

Table of Contents

Document Revision History ...........................................................................................................................2

How to Contact Microtronix ...........................................................................................................................2

E-mail .........................................................................................................................................................2

Website ......................................................................................................................................................2

Phone Numbers .........................................................................................................................................2

Typographic Conventions ..............................................................................................................................2

Introduction ....................................................................................................................................................5

Kit Contents ...................................................................................................................................................5

Microtronix HSMC Daughter Cards ...............................................................................................................5

Quad Link LVDS Interface HSMC Daughter Card .....................................................................................6

Camera Link Receiver HSMC Daughter Card ...........................................................................................6

Camera Link Transmitter HSMC Daughter Card .......................................................................................7

Gig-Ethernet - HDMI 1.3 Transmitter HSMC Daughter Card ....................................................................7

HDMI v1.1 Receiver / Transmitter HSMC Daughter Card .........................................................................8

HDMI v1.4 Transmitter HSMC Daughter Card ..........................................................................................8

HDMI v1.4 Receiver HSMC Daughter Card ..............................................................................................9

ViClaro IV-GX Overview ............................................................................................................................. 10

Power Supply .......................................................................................................................................... 10

Power Consumption ............................................................................................................................ 10

Power ON/OFF Switch ........................................................................................................................ 11

Cyclone IV-GX Device Configuration ...................................................................................................... 11

ViClaro IV-GX Clocking ........................................................................................................................... 11

Clock Oscillator Circuitry ..................................................................................................................... 11

HSMC Clock Connections ...................................................................................................................... 12

ViClaro IV-GX Host Board Components .................................................................................................... 12

Cyclone IV-GX FPGA ............................................................................................................................. 12

Config Done LED .................................................................................................................................... 12

HSMC Presence LEDs ........................................................................................................................... 12

User LEDs ............................................................................................................................................... 13

User Push Button Switches .................................................................................................................... 13

JTAG Select DIP Switch ......................................................................................................................... 13

miniSD Card Interface ............................................................................................................................. 13


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DDR2 SDRAM ........................................................................................................................................ 14

Connector J1, HSMC1 ............................................................................................................................ 16

Connector J2, HSMC2 ............................................................................................................................ 19

Connector J3, HSMC3 ............................................................................................................................ 21

ViClaro IV-GX Software Installation ........................................................................................................... 25

Running Video Reference Designs ............................................................................................................ 25

Configure USB-Blaster ............................................................................................................................ 25

Overview of Reference Designs ................................................................................................................. 25

Microtronix IP Cores ............................................................................................................................... 26

Description of Reference Design ................................................................................................................ 26

SD-HD Dynamic Scaler Reference Design ............................................................................................ 26

SD-HD Dynamic Scaler Circuit Descriptions....................................................................................... 27

HDMI v1.1 Hardware Configuration .................................................................................................... 28

HDMI v1.4 Hardware Configuration .................................................................................................... 28

Quad Video Display Reference Design .................................................................................................. 28

Quad Video Display Circuit Descriptions ............................................................................................ 29

Hardware Configuration ...................................................................................................................... 30

720p Text Overlay OSD Reference Design ............................................................................................ 31

720p Text Overlay Circuit Descriptions ............................................................................................... 32


HDMI 1.4 1080p Transmitter Reference Design..................................................................................... 33


HD-SDI Pass-Through Design ................................................................................................................ 34


Configuring HD EDID for Correct Refresh Rate ......................................................................................... 36

Loading ViClaro IV-GX Reference Designs ............................................................................................... 37

Importing Software ..................................................................................................................................... 38

Appendix A: Loading Designs into the FPGA............................................................................................. 39

Appendix B: Loading Designs into On-Board Flash ................................................................................... 40

Converting a SOF File to a JIC for the Flash Device .......................................................................... 40

Programming the Flash Device ........................................................................................................... 40


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The Microtronix ViClaro IV-GX Video Host Board is an open architecture

FPGA development board targeted at the development of consumer video

display and imaging systems.

The key features of the kit include:

Altera Cyclone IV-GX FPGA (EP4CGX110DF31C7N)

256 Mbyte of 64-bit wide DDR2 SDRAM (consisting of 4

MT47H32M16HR-25E IT:G memory devices)

3 High Speed Mezzanine Connectors (HSMC)

On-board USB-Blaster circuit

miniSD Memory Card slot

2 TI CDCE925 VXCO Clock Synthesizers

10 status LEDs (four general I/O)

Switches: 4 momentary and one 4-position DIP

50MHz & 27MHz oscillators

Power ON/OFF switch

The Microtronix ViClaro IV-GX Video Host Board includes the following

hardware components:

ViClaro IV-GX Video Host Board (PN: 6282-00-00)

USB A-B cable

100-240 VAC - 12VDC 7A Power Adapter (PN: 589-PS-1270A)

Microtronix ViClaro IV-GX Video Host Board – Installation CD

The following Microtronix HSMC Daughter Cards are available for purchase

through our website:

Quad Link LVDS Interface, PN: 6253-01-01

Gig-Ethernet / HDMI 1.3 Transmitter, PN: 6266-01-01

HDMI 1.1 Receiver / Transmitter, PN: 6256-00-00

Camera Link Receiver, PN: 6283-01-01

Camera Link Transmitter, PN: 6287-01-01

HDMI 1.4 Transmitter, PN: 6290-01-01

HDMI 1.4 Receiver, PN: 6291-01-01

Introduction

Kit Contents

Microtronix HSMC

Daughter Cards

http://www.microtronix.com/hsmc-daughtercard-solutions/quad-link-lvds-interface-hsmc-daughtercard

http://www.microtronix.com/hsmc-daughtercard-solutions/quad-link-lvds-interface-hsmc-daughtercard

http://www.microtronix.com/hsmc-daughtercard-solutions/gigabit-ethernet-phy-hdmi-transmitter-hsmc-daughtercard

http://www.microtronix.com/hsmc-daughtercard-solutions/hdmi-receiver-transmitter-hsmc-daughtercard-1

http://www.microtronix.com/hsmc-daughtercard-solutions/camera-link-receiver-hsmc-daughter-card

http://www.microtronix.com/hsmc-daughtercard-solutions/camera-link-transmitter-hsmc-daughter-card

http://www.microtronix.com/hsmc-daughtercard-solutions/hdmi-1-4-transmitter-hsmc-daughter-card

http://www.microtronix.com/hsmc-daughtercard-solutions/hdmi-1-4-receiver-hsmc-daughter-card


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QUAD LINK LVDS INTERFACE HSMC DAUGHTER CARD

The Microtronix Quad Link LVDS Interface HSMC Daughter Card (PN: 6253-

01-01) targeted at the development of HD video systems incorporating LVDS

interfaces. A picture of the Quad Link LVDS Interface HSMC Daughter Card

is shown in Figure 1 below.

Figure 1: Quad Link LVDS Interface Daughter Card

CAMERA LINK RECEIVER HSMC DAUGHTER CARD

The Microtronix Camera Link Receiver HSMC Daughter Card (PN: 6283-01-

01) is shown in Figure 2 below. It provides two Camera Link MDR-26 female

connectors (3M – 14B26-SZLB-X00-OLC). The card supports Power over

Camera Link (PoCL).

Figure 2: Camera Link Receiver HSMC Daughter Card


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CAMERA LINK TRANSMITTER HSMC DAUGHTER CARD

The Microtronix Camera Link Transmitter HSMC Daughter Card (PN: 6287-

01-01) is shown in Figure 2 below. It provides two Camera Link MDR-26

female connectors (3M – 14B26-SZLB-X00-OLC). The card supports

configuration to indicate Power over Camera Link (PoCL).

Figure 3: Camera Link Transmitter HSMC Daughter Card

GIG-ETHERNET - HDMI 1.3 TRANSMITTER HSMC DAUGHTER CARD

The Microtronix Gig-Ethernet – HDMI 1.3 Transmitter HSMC Daughter Card

(PN: 6266-01-01) provides a triple-speed Ethernet port and a HDMI v1.3 output

video port. The card is shown in Figure 4 below.

Figure 4: Gigabit Ethernet and HDMI 1.3 Transmitter Board


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HDMI V1.1 RECEIVER / TRANSMITTER HSMC DAUGHTER CARD

The Microtronix HDMI v1.1 Transmitter HSMC Daughter Card

(PN: 6256-01-01) provide one HDMI Receiver and one HDM Transmitter

interface using a single HSMC expansion connector. The card is shown in

Figure 5 below.

Figure 5: HDMI v1.1 Receiver / Transmitter Board

HDMI V1.4 TRANSMITTER HSMC DAUGHTER CARD

The Microtronix HDMI 1.4 Transmitter HSMC Daughter Card uses the Analog

Device ADV7511KSTZ-P high-performance HDMI v1.4 Transmitter to support

HDTV formats up to 1080p at 60 Hz. It is shown in Figure 6 below.

Figure 6: HDMI 1.4 Transmitter HSMC Daughter Card


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HDMI V1.4 RECEIVER HSMC DAUGHTER CARD

The Microtronix HDMI 1.4 Transmitter HSMC Daughter Card uses the Analog

Device ADV7612BSWZ-P high-performance HDMI v1.4 Receiver to support

HDTV formats up to 1080p at 60 Hz. It is shown in Figure 7 below.

Figure 7: HDMI 1.4 Receiver HSMC Daughter Card


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A picture of the ViClaro IV-GX Video Host board is shown in Figure 1 below.

Figure 8: ViClaro IV-GX Video Host Board

POWER SUPPLY

The board is powered from a 2.5mm power jack input using an external

120/240VDC power adapter rated at +12VDC 7 amps. The jack is polarity

insensitive. On-board DC-DC power convertors and linear regulators are used

to the required voltages.

One LTM4618 power converter module is used to generate 3.3V. Switching

convertors are used to generate 1.2V and 1.8V power. A low noise LDO

micropower regulator is used to generate 2.5V.

Power Consumption

The ViClaro IV-GX board draws approximately 1.25 A at 12 VDC. However,

power consumption varies greatly according to the frequency of operation,

ViClaro IV-GX

Overview


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amount of logic incorporated into the FPGA device and the HSMC Daughter

cards installed on the board.

Power ON/OFF Switch

Slide switch SW2 is used to switch the board on and off by powering the DC-

DC convertors ON and OFF. LED9 is a green LED which indicates the present

of 3.3VDC.

CYCLONE IV-GX DEVICE CONFIGURATION

The Cyclone IV-GX device can be configured in JTAG stand-alone mode or

passive serial mode. At power-up, the Cyclone IV-GX device loads the

configuration from the on-board (EPCS128) serial flash. If the configuration is

successful, the orange CONF_DONE LED illuminates.

For instructions on programming the FPGA via JTAG, see Appendix A. The

serial flash can be programmed using JTAG in-system programming. See

Appendix B.

VICLARO IV-GX CLOCKING

Clock Oscillator Circuitry

The board has a 27 MHz and a 50 MHz crystal oscillator. Figure 9 shows the

clocking circuitry.

Figure 9: 27 MHz & 50 MHz Clock Oscillator Circuitry


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HSMC CLOCK CONNECTIONS

The board has a 27 MHz and a 50 MHz crystal oscillator. Figure 10 below

shows the HSMC – FPGA clock connections.

Figure 10: HSMC Connector – FPGA Clock Connections

CYCLONE IV-GX FPGA

The ViClaro IV Host board is fitted with an Cyclone IV-GX EP4CGX110 device

in a 780-pin Fine Line BGA package with speed grade -7. See Appendices A

and B for instructions on programming the FPGA.

For more information on Cyclone IV-GX devices, refer to the Altera Cyclone IV

Device Handbook.

CONFIG DONE LED

There is one orange Config Done LED (LED7) which is used to indicate a

successful load (programming) of the FPGA device.

HSMC PRESENCE LEDS

Each HSMC connector has a presence LED which is active when a HSMC

daughter card is installed on the HSMC connector. These are associated with

ViClaro IV-GX Host Board

Components


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each connector as follows: HSMC1 – LED4, HSMC2 – LED5 and HSMC3 –

LED5 .

USER LEDS

There are four user general purpose red LEDs labeled LED0-LED3 driven by

the Cyclone IV-GX device. The LEDs are located in bank 3. The I/O standard

for these pins should be set to 1.8V.

Table 1: Cyclone IV-GX – Red LED pin assignments

LED Signal Name Pin Number

LED0 LED0 AE10

LED1 LED1 AF10

LED2 LED2 AE9

LED3 LED3 AJ12

USER PUSH BUTTON SWITCHES

There are four general-purpose momentary push button switches driving inputs

on the Cyclone IV-GX device. The push buttons are labeled PB0-PB3 allocated

in bank 3. The I/O standard for these pins should be set to 1.8V.

Table 2: Cyclone IV-GX – Push button switch pin assignments

Switch Signal Name Pin Number

PB0 SWITCH0 AK12

PB1 SWITCH1 AD10

PB2 SWITCH2 AF7

PB3 SWITCH3 AF9

JTAG SELECT DIP SWITCH

There is one four position DIP Switch labeled SW1, used to enable (select) the

JTAG chain to each of the three HSMC connectors. DIP switch position 1-3

enable HSMC connector 1 through 3 respectively.

MINISD CARD INTERFACE

The board supports one miniSD Card Slot interface located on the bottom of

the card. A MAX13030 level translator is used to interface the 3.3V SD Card

signals to the 1.8V level required by the FPGA. The SD Card signals are

located in bank 3. The I/O standard for these pins should be set to 1.8V.


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Table 3: Cyclone III – miniSD interface pin assignments

miniSD Card Signal Pin Number

SD_CLK AE5

SD_CMD AE4

SD_DAT0 AH3

SD_DAT1 AH4

SD_DAT2 AG4

SD_DAT3 AF4

SD_SW0 AH5

SD_SW1 AG3

DDR2 SDRAM

The ViClaro IV-GX board has four Micron DDR2 SDRAM devices (Micron

MT47H32M16HR-25E IT:G) with a total capacity of 256MB (32M x 64). The

memory devices are connected to banks 3 and 4 of the Cyclone IV-GX device

and use the SSTL-18 I/O-standard. The two banks are powered with the 1.8V

power supply. The board is designed for matched length traces across all DDR2

signals. All unused I/O-pins in the banks are connected to ground.

There are two clock outputs from the FPGA to the four devices. The lower 32

bits (U5, U4) use CLK0/CLK#0 and the upper 32 bits (U2, U1) use

CLK1/CLK#1.

The DDR2 SDRAM has been performance tested at 167 MHz (333 MT/s) using

the Microtronix Streaming and Avalon SDRAM Memory Controller IP cores.

Table 4: Cyclone IV-GX – DDR2 SDRAM key pin assignments

Signal Name Pin Number Signal Name Pin Number

CKE AA16 A3 AF16

WEn AB16 A4 AK21

CSn AF18 A5 AK20

CASn AE17 A6 AJ22

RASn AF21 A7 AJ19

ODT AG17 A8 AK22

BA0 AD16 A9 AJ21

BA1 AE20 A10 AE16

A0 AG18 A11 AH21

A1 AG16 A12 AK19

A2 AH17


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Table 5: Cyclone IV-GX – DDR2 SDRAM key pin assignments

Signal Name

Pin Number

Signal Name

Pin Number

Signal Name

Pin Number

Signal Name

Pin Number

DQ0 AK5 DQ16 AA15 DQ32 AH25 DQ48 AG28

DQ1 AH2 DQ17 AK8 DQ33 AG23 DQ49 Y21

DQ2 AG5 DQ18 AK14 DQ34 AK23 DQ50 AH27

DQ3 AJ4 DQ19 AK11 DQ35 Y19 DQ51 AE24

DQ4 AJ3 DQ20 AE14 DQ36 AA20 DQ52 Y20

DQ5 AH6 DQ21 AH16 DQ37 AJ24 DQ53 AG25

DQ6 AF3 DQ22 AJ7 DQ38 AE21 DQ54 AA21

DQ7 AK4 DQ23 AH15 DQ39 AK26 DQ55 AD24

DQ8 AH11 DQ24 AE18 DQ40 AG24 DQ56 AG26

DQ9 AG9 DQ25 AK15 DQ41 AH22 DQ57 AK27

DQ10 AH12 DQ26 AH18 DQ42 AH23 DQ58 AK25

DQ11 AH8 DQ27 AH19 DQ43 AF22 DQ59 AH26

DQ12 AG10 DQ28 AK18 DQ44 AE22 DQ60 AJ25

DQ13 AE13 DQ29 AJ18 DQ45 AH24 DQ61 AH28

DQ14 AE12 DQ30 AJ15 DQ46 AG22 DQ62 AJ28

DQ15 AJ10 DQ31 AK17 DQ47 AE23 DQ63 AG27

DQS0 AD9 DSQ2 AF15 DQS4 AD22 DQS6 AB22

DQS1 AH13 DQS3 AA17 DQS5 AK24 DQS7 AK29

DM0 AE3 DM2 AB13 DM4 AE19 DM6 AJ27

DM1 AJ6 DM3 Y17 DM5 AD23 DM7 AK28

CLK0 AG7 CLK1 AG20

CLKn0 AH7 CLKn1 AH20

Notes:

1) The Microtronix SDRAM Memory Controller IP cores use source synchronous DQS clocking to capture data from the DDR2 memory devices and therefore does not require the use of dedicated DQ pins for the data. While the IO banks used for DDR2 memory only provided 48 bits of DQ pins, the Microtronix core can support a full 64-bit memory interface by using non-dedicated IO for the DQ signals.

2) The Altera memory controller requires DQ signals to be on DQ pins and is therefore limited to a 32-bit memory interface on the ViClaro IV-GX board. To accommodate this core, the low 8-bits of each chip are all connected to the dedicated DQ pins and used to provide a 32-bit interface.


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CONNECTOR J1, HSMC1

HSMC1 (J1) connector is located on the left (beside the push button switches).

This connector interface supports single-ended signaling only.

In its default configuration, HSMC1 provides: 80 single ended I/Os and 4

transceiver channels. In addition one dedicated clock input and clock output

connected to PLL2.

The HSMC1 interface pins are located in banks 7 and 8. This bank is powered

at 2.5 volts. HSMC1_TX(p/n)[0..3] and HSMC1_RX(p/n)[0..3] pins are located

in bank QL0.

Table 6: J1, HSMC1 Connector Pin Assignments

Cyclone IV Pin #

Signal Name HSMC1 Pin #

HSMC1 Pin #

Signal Name Cyclone IV

Pin #

NC 1 2 NC

NC 3 4 NC

NC 5 6 NC

NC 7 8 NC

NC 9 10 NC

NC 11 12 NC

NC 13 14 NC

NC 15 16 NC

AB4 HSMC1_TXp3 17 18 HSMC1_RXp3 AC2

AB3 HSMC1_TXn3 19 20 HSMC1_RXn3 AC1

Y4 HSMC1_TXp2 21 22 HSMC1_RXp2 AA2

Y3 HSMC1_TXn2 23 24 HSMC1_RXn2 AA1

V4 HSMC1_TXp1 25 26 HSMC1_RXp1 W1

V3 HSMC1_TXn1 27 28 HSMC1_RXn1 W2

T4 HSMC1_TXp0 29 30 HSMC1_RXp0 U2

T3 HSMC1_TXn0 31 32 HSMC1_RXn0 U1

J9 HSMC1_SDA 33 34 HSMC1_SCL H9

‡ HSMC1_TCK 35 36 HSMC1_TMS ‡

* HSMC1_TDO 37 38 HSMC1_TDI *

G6 HSMC1_CLKOUT0 39 40 HSMC1_CLKIN0 L11

F17 HSMC1_D0 41 42 HSMC1_D1 G14

F16 HSMC1_D2 43 44 HSMC1_D3 G15

3.3V 45 46 12V

E15 HSMC1_D4 47 48 HSMC1_D5 G12


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D14 HSMC1_D6 49 50 HSMC1_D7 G13

3.3V 51 52 12V

D13 HSMC1_D8 53 54 HSMC1_D9 G10

D12 HSMC1_D10 55 56 HSMC1_D11 F11

3.3V 57 58 12V

D11 HSMC1_D12 59 60 HSMC1_D13 F8

E10 HSMC1_D14 61 62 HSMC1_D15 F9

3.3V 63 64 12V

E9 HSMC1_D16 65 66 HSMC1_D17 F6

D8 HSMC1_D18 67 68 HSMC1_D19 G7

3.3V 69 70 12V

E7 HSMC1_D20 71 72 HSMC1_D21 F4

E6 HSMC1_D22 73 74 HSMC1_D23 F5

3.3V 75 76 12V

D5 HSMC1_D24 77 78 HSMC1_D25 F10

E4 HSMC1_D26 79 80 HSMC1_D27 F7

3.3V 81 82 12V

E3 HSMC1_D28 83 84 HSMC1_D29 C2

D3 HSMC1_D30 85 86 HSMC1_D31 D4

3.3V 87 88 12V

D1 HSMC1_D32 89 90 HSMC1_D33 C4

E16 HSMC1_D34 91 92 HSMC1_D35 C3

3.3V 93 94 12V

D16 HSMC1_D36 95 96 HSMC1_D37 D6

C16 HSMC1_D38 97 98 HSMC1_D39 C5

3.3V 99 100 12v

A4 HSMC1_D40 101 102 HSMC1_D41 C7

A5 HSMC1_D42 103 104 HSMC1_D43 D7

3.3V 105 106 12V

A6 HSMC1_D44 107 108 HSMC1_D45 D10

A7 HSMC1_D46 109 110 HSMC1_D47 D9

3.3V 111 112 12V

A8 HSMC1_D48 113 114 HSMC1_D49 C12

A9 HSMC1_D50 115 116 HSMC1_D51 C11

3.3V 117 118 12V

A10 HSMC1_D52 119 120 HSMC1_D53 C14


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A11 HSMC1_D54 121 122 HSMC1_D55 F14

3.3V 123 124 12V

A12 HSMC1_D56 125 126 HSMC1_D57 C15

A13 HSMC1_D58 127 128 HSMC1_D59 D15

3.3V 129 130 12V

A14 HSMC1_D60 131 132 HSMC1_D61 E13

B16 HSMC1_D62 133 134 HSMC1_D63 F15

3.3V 135 136 12V

A16 HSMC1_D64 137 138 HSMC1_D65 E12

D17 HSMC1_D66 139 140 HSMC1_D67 F12

3.3V 141 142 12V

A17 HSMC1_D68 143 144 HSMC1_D69 E13

C17 HSMC1_D70 145 146 HSMC1_D71 C6

3.3V 147 148 12V

C9 HSMC1_D72 149 150 HSMC1_D73 B6

B9 HSMC1_D74 151 152 HSMC1_D75 B7

3.3V 153 154 12V

B10 HSMC1_D76 155 156 HSMC1_D77 C13

C10 HSMC1_D78 157 158 HSMC1_D79 B12

3.3V 159 160 Presence LED ** To LED4

Notes: 1) ‡ See board schematic for connection details.

2) * Gated through digital switch U3 & U4, (NLAS4717EPMTR2G).

3) ** Connect to GND to turn LED4 on.


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CONNECTOR J2, HSMC2

HSMC2 (J2) is located on the top side of the board and provides 80 single

ended I/Os and 4 transceiver channels. In addition, HSMC2 contains one

dedicated clock input and a clock output connected to PLL8.

The HSMC2 pins are located in bank 7 of the FPGA. This bank is powered at

2.5V. The differential HSMC2_TX(p/n)[0..3] and HSMC2_RX(p/n)[0..3] pins are

located in bank QL1 and powered at 2.5 volts. HSMC2_CLKIN0 is located in

bank 8A and powered at 2.5 volts.


Cyclone IV Pin #


HSMC2 Pin #


Pin #

NC 1 2 NC

NC 3 4 NC

NC 5 6 NC

NC 7 8 NC

NC 9 10 NC

NC 11 12 NC

NC 13 14 NC

NC 15 16 NC

P4 HSMC2_TXp3 17 18 HSMC2_RXp3 R2

P3 HSMC2_TXn3 19 20 HSMC2_RXn3 R1

M4 HSMC2_TXp2 21 22 HSMC2_RXp2 N2

M3 HSMC2_TXn2 23 24 HSMC2_RXn2 N1

K4 HSMC2_TXp1 25 26 HSMC2_RXp1 J2

K3 HSMC2_TXn1 27 28 HSMC2_RXn1 L1

H4 HSMC2_TXp0 29 30 HSMC2_RXp0 J2

H3 HSMC2_TXn0 31 32 HSMC2_RXn0 J1

C21 HSMC2_SDA 33 34 HSMC2_SLC G21



G8 HSMC2_CLKOUT0 39 40 HSMC_CLKIN0 L15

F19 HSMC2_D0 41 42 HSMC2_D1 A18

F18 HSMC2_D2 43 44 HSMC2_D3 B18

3.3V 45 46 12V

E18 HSMC2_D4 47 48 HSMC2_D5 A19

D18 HSMC2_D6 49 50 HSMC2_D7 B19

3.3V 51 52 12V


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E19 HSMC2_D8 53 54 HSMC2_D9 B21

D19 HSMC2_D10 55 56 HSMC2_D11 A20

3.3V 57 58 12V

F20 HSMC2_D12 59 60 HSMC2_D13 B22

D20 HSMC2_D14 61 62 HSMC2_D15 A21

3.3V 63 64 12V

F21 HSMC2_D16 65 66 HSMC2_D17 A23

E21 HSMC2_D18 67 68 HSMC2_D19 A22

3.3V 69 70 12V

F22 HSMC2_D20 71 72 HSMC2_D21 A24

E22 HSMC2_D22 73 74 HSMC2_D23 B24

3.3V 75 76 12V

D22 HSMC2_D24 77 78 HSMC2_D25 B25

D23 HSMC2_D26 79 80 HSMC2_D27 A25

3.3V 81 82 12V

F23 HSMC2_D28 83 84 HSMC2_D29 B27

D24 HSMC2_D30 85 86 HSMC2_D31 A26

3.3V 87 88 12V

E24 HSMC2_D32 89 90 HSMC2_D33 A28

F24 HSMC2_D34 91 92 HSMC2_D35 A27

3.3V 93 94 12V

D25 HSMC2_D36 95 96 HSMC2_D37 A29

E25 HSMC2_D38 97 98 HSMC2_D39 B28

3.3V 99 100 12V

G17 HSMC2_D40 101 102 HSMC2_D41 C18

K17 HSMC2_D42 103 104 HSMC2_D43 C19

3.3V 105 106 12V

G18 HSMC2_D44 107 108 HSMC2_D45 C20

K18 HSMC2_D46 109 110 HSMC2_D47 D21

3.3V 111 112 12V

G20 HSMC2_D48 113 114 HSMC2_D49 C22

K19 HSMC2_D50 115 116 HSMC2_D51 C23

3.3V 117 118 12V

G22 HSMC2_D52 119 120 HSMC2_D53 C24

K21 HSMC2_D54 121 122 HSMC2_D55 C25

3.3V 123 124 12V


Page 21 of 40

G23 HSMC2_D56 125 126 HSMC2_D57 C26

K22 HSMC2_D58 127 128 HSMC2_D59 C27

3.3V 129 130 12V

G24 HSMC2_D60 131 132 HSMC2_D61 C28

H24 HSMC2_D62 133 134 HSMC2_D63 B30

3.3V 135 136 12V

F25 HSMC2_D64 137 138 HSMC2_D65 D27

J25 HSMC2_D66 139 140 HSMC2_D67 D28

3.3V 141 142 12V

D26 HSMC2_D68 143 144 HSMC2_D69 E27

G25 HSMC2_D70 145 146 HSMC2_D71 E28

3.3V 147 148 12V

F27 HSMC2_D72 149 150 HSMC2_D73 F28

F26 HSMC2_D74 151 152 HSMC2_D75 F29

3.3V 153 154 12V

J27 HSMC2_D76 155 156 HSMC2_D77 G26

H27 HSMC2_D78 157 158 HSMC2_D79 G27

3.3V 159 160 Presence LED** To LED5

Notes:

1) ‡ See board schematic for connection details.



CONNECTOR J3, HSMC3

HSMC3 (J3) is located on the right side of the board and provides 17

differential transmit pairs and 17 differential receive pairs. The header

additionally supports two dedicated differential input clocks and two differential

output clocks. All of the differential receive pairs are terminate with 100Ω

resistors.

The transmit pairs can be used as single-ended I/Os without any change to the

board. To use the receive pairs as single-ended I/Os, the differential

termination resistors (R25-R49) must be removed.

The HSMC3 pins are located in banks 5 and 6. These banks are powered at

2.5V. Differential pairs should be configured with the LVDS I/O standard.

Single-ended I/O pins should be configured with the 2.5V I/O standard..


Page 22 of 40


Cyclone IV Pin #


HSMC3 Pin #


Pin #

NC 1 2 NC

NC 3 4 NC

NC 5 6 NC

NC 7 8 NC

H30 HSMC3_TXp22 9 10 HSMC3_TXp23 J29

G30 HSMC3_TXn22 11 12 HSMC3_TXn23 J30

N24 HSMC3_TXp21 13 14 HSMC3_RXp21 L27

M25 HSMC3_TXn21 15 16 HSMC3_RXn21 L28

N25 HSMC3_TXp20 17 18 HSMC3_RXp20 L30

M26 HSMC3_TXn20 19 20 HSMC3_RXn20 K30

M21 HSMC3_TXp19 21 22 HSMC3_RXp19 M27

M22 HSMC3_TXn19 23 24 HSMC3_RXn19 M28

P21 HSMC3_TXp18 25 26 HSMC3_RXp18 K28

N21 HSMC3_TXn18 27 28 HSMC3_RXn18 K29

R24 HSMC3_TXp17 29 30 HSMC3_RXp17 M29

P25 HSMC3_TXn17 31 32 HSMC3_RXn17 M30

H25 HSMC3_SDA 33 34 HSMC3_SLC K24



C29 HSMC3_CLKOUT0 39 40 HSMC3_CLKIN0 B15

H28 HSMC3_D0 41 42 HSMC3_D1 D29

J28 HSMC3_D2 43 44 HSMC3_D3 C30

3.3V 45 46 12V

T28 HSMC3_TXp0 47 48 HSMC3_RXp0 N29

R29 HSMC3_TXn0 49 50 HSMC3_RXn0 N30

3.3V 51 52 12V

P27 HSMC3_TXp1 53 54 HSMC3_RXp1_X Note (3)

P28 HSMC3_TXn1 55 56 HSMC3_RXn1_X Note (4)

3.3V 57 58 12V

R25 HSMC3_TXp2 59 60 HSMC3_RXp2 R30

R26 HSMC3_TXn2 61 62 HSMC3_RXn2 P30

3.3V 63 64 12V

T26 HSMC3_TXp3 65 66 HSMC3_RXp3 R27


Page 23 of 40

T27 HSMC3_TXn3 67 68 HSMC3_RXn3 R28

3.3V 69 70 12V

T23 HSMC3_TXp4 71 72 HSMC3_RXp4 W25

T24 HSMC3_TXn4 73 74 HSMC3_RXn4 W26

3.3V 75 76 12V

U21 HSMC3_TXp5 77 78 HSMC3_RXp5 U27

T21 HSMC3_TXn5 79 80 HSMC3_RXn5 U28

3.3V 81 82 12V

U25 HSMC3_TXp6 83 84 HSMC3_RXp6 V27

T25 HSMC3_TXn6 85 86 HSMC3_RXn6 V28

3.3V 87 88 12V

V25 HSMC3_TXp7 89 90 HSMC3_RXp7 W29

V26 HSMC3_TXn7 91 92 HSMC3_RXn7 W30

3.3V 93 94 12V

W27 HSMC3_TX_CLKp0 95 96 HSMC3_RX_CLKp0 V29

W28 HSMC3_TX_CLKn0 97 98 HSMC3_RX_CLKn0 V30

3.3V 99 100 12v

AA22 HSMC3_TXp8 101 102 HSMC3_RXp8 AA28

Y22 HSMC3_TXn8 103 104 HSMC3_RXn8 Y28

3.3V 105 106 12V

AA27 HSMC3_TXp9 107 108 HSMC3_RXp9 AA30

Y27 HSMC3_TXn9 109 110 HSMC3_RXn9 Y30

3.3V 111 112 12V

AB27 HSMC3_TXp10 113 114 HSMC3_RXp10 AB29

AB28 HSMC3_TXn10 115 116 HSMC3_RXn10 AA29

3.3V 117 118 12V

AB25 HSMC3_TXp11 119 120 HSMC3_RXp11 AC30

AA25 HSMC3_TXn11 121 122 HSMC3_RXn11 AB30

3.3V 123 124 12V

AC25 HSMC3_TXp12 125 126 HSMC3_RXp12 AD29

AB26 HSMC3_TXn12 127 128 HSMC3_RXn12 AD30

3.3V 129 130 12V

AD27 HSMC3_TXp13 131 132 HSMC3_RXp13 AE29

AD28 HSMC3_TXn13 133 134 HSMC3_RXn13 AE30

3.3V 135 136 12V

AE27 HSMC3_TXp14 137 138 HSMC3_RXp14 AC27


Page 24 of 40

AE28 HSMC3_TXn14 139 140 HSMC3_RXn14 AC28

3.3V 141 142 12V

AE25 HSMC3_TXp15 143 144 HSMC3_RXp15 AG30

AE26 HSMC3_TXn15 145 146 HSMC3_RXn15 AF30

3.3V 147 148 12V

AF27 HSMC3_TXp16 149 150 HSMC3_RXp16 AJ30

AF28 HSMC3_TXn16 151 152 HSMC3_RXn16 AH30

3.3V 153 154 12V

AH29 HSMC3_TX_CLKp1 155 156 HSMC3_RX_CLKp1 T29

AG29 HSMC3_TX_CLKn1 157 158 HSMC3_RX_CLKn1 T30

3.3V 159 160 Presence LED** To LED6

Notes: 1) ‡ See board schematic for connection details.


3) Connected to 0Ω resistors for connection to U1-N27 (default) or optionally to U1-V15.

4) Connected to 0Ω resistors for connection to U1-N28 (default) or optionally to U1-W15.



Page 25 of 40

The ViClaro IV-GX software requires an installed version of the Altera Quartus

II FPGA design software (either the Altera Web Edition or the Full Edition).

The ViClaro IV software is supplied by Microtronix on a CD or as a zipped file.

If you received the latter, unzip the file to a temporary file directory and run the

setup.exe file. The software should self-install from the CD or it can be

manually installed by running the setup.exe file.

WARNING: Remove older installations of the ViClaro IV-GX software from the

PC prior to installing the new version of software.

The ViClaro IV-GX Kit includes a number of pre-compiled Quartus reference

designs to demonstrate the functionality of the board.

The designs are supplied as pre-compiled SOF files and also as Quartus

design files with the full source. The SOF files can be run by downloading them

through the JTAG port into the Cyclone IV FPGA on the board.

CONFIGURE USB-BLASTER

This step is required if the USB-Blaster has not yet been configured to work

with the Quartus software.

1. Connect the USB cable to the ViClaro IV-GX board.

2. Plug the other end of the cable into the PC/Laptop.

3. Start Quartus.

4. Connect to the JTAG programmer by selecting > Tools > Programmer >

Hardware.

a. Click on Hardware Setup box. Confirm/select USB-Blaster.

b. Click on Auto Detect box. This will find the programmable devices

on the ViClaro III board.

NOTE: To load SOF or POF files into the FPGA or flash memory, refer to

Appendix A and B respectively.

The ViClaro IV-GX Reference Designs are based on Qsys and the use of the

Altera Avalon-S/T streaming video bus architecture. They are supplied as pre-

compiled SOF files and as Quartus Qsys design files with the full source. The

DVI/HDMI based designs require a variety of video sources

(480i/576i/720p/1080p/1080i) and a monitor with a DVI or HDMI input

supporting resolutions of 720p, 1080p 50/59.94/60Hz, and 1080i 60Hz.

The Reference Designs are listed in the following table.

ViClaro IV-GX Software

Installation

Running Video

Reference Designs

Overview of

Reference Designs


Page 26 of 40

Table 9: Quartus Reference Designs

Description Directory & Filename

SD-HD 1080p Dynamic Scaler

example/HDMI_1_4TX_RX_VIC_IV/scaler_1080p.sof

example/HDMI_A6256_TX_RX_VIC_IV/scaler_1080p.sof

Quad Video Display example/bitec_quad_video/quad_video_example/

quad_video_exammple.sof

720p Text Overlay OSD example/TextOverlay_720p/TextOverlay_720p.sof

HDMI 1.4 1080p Transmitter example/HDMI_1_4_TX_VIC_IV/hdmi_tx.sof

HD-SDI Pass Through exmaple/sdi/sdi_passthrough/sdi_passthrough.sof

MICROTRONIX IP CORES

The ViClaro IV-GX video reference designs incorporate the Microtronix Avalon

Multi-port DDR2 SDRAM Memory Controller and the Microtronix I2C Master-

Slave-PIO Controller. The Kit includes Cyclone IV OpenCore Plus Evaluation

licenses for both of the IP Cores.

To receive your IP core Evaluation licenses contact sales

[email protected] and provide them with the serial number of your board

and the NIC ID of your PC. These licenses are required if you are to recompile

or develop new IP core designs.

NOTE: An OpenCore Plus license enables the designer to compile, simulate

and generate a .sof programming file to trial the IP in-circuit. The board must

be tethered to the PC via the JTAG port. The core will operate for

approximately one hour after which it will need to be re-loaded.

SD-HD DYNAMIC SCALER REFERENCE DESIGN

The SD-HD Dynamic Scaler auto detects the incoming video and scales it to

1080p50. When connected to an interlaced video source, a deinterlacer

converts the interlaced video to progressive for scaling to 1080p50 as shown in

the following diagram. The deinterlacer uses a triple buffer to support frame

conversion. The design supports the following incoming video rates:

720 x 480i @ 60 Hz,

720 x 576i @ 50 Hz,

1280 x 720p @ 50/60 Hz,

1920 x 1080i @ 50/60 Hz, and

1920 x 1080p @ 50 Hz.

There are two variants of the Dynamic Scaler Design: one is based on 8-bit

RGB for use with the HDMI v1.1 Receiver/Transmitter HSMC Daughter Card

Description of

Reference Design

mailto:[email protected]


Page 27 of 40

(A6256); the other is based on 12-bit RGB using the HDMI v1.4 Receiver

(A6291) and the HDMI v1.4 Transmitter (A6290) HSMC Daughter Cards. A

block diagram of the SD-HD Video Scaler is shown below.

Figure 11: Block Diagram of SD-HD Dynamic Scaler Video System

SD-HD Dynamic Scaler Circuit Descriptions

PLL CLOCK DOMAINS

The DDR2 memory uses one PLL running at 167MHz. The same PLL also

generates a 100 MHz clock for the Nios II processor and peripherals. A second

PLL generates a 123.75 MHz clock for the Altera VIP components in the Qsys

system. The HDMI transmitter also operates from the same 123.75 MHz clock.

AVALON MULTI-PORT DDR2 SDRAM MEMORY CONTROLLER

The Avalon Multi-port DDR2 SDRAM Memory Controller operates at 167 MHz

and interfaces to the DDR2 using a 64-bit data bus.

IP BLOCKS

This design uses the Altera VIP suite of IP. The Clocked Video Input and

Clocked Video Output components interface to the HDMI transmitter and

receiver. The deinterlacer uses a triple frame buffer to convert between the

input frame rate and the output frame rate. Incoming progressive video passes

through the deinterlacer unchanged and incoming interlaced video is converted

to progressive using the weave algorithm. The Scaler dynamically converts the

video to 1080p using the Bicubic algorithm. I2C Master Controllers are used to

configure the HDMI Receiver and Transmitter video controllers.

HDMI RECEIVER/TRANSMITTER

The HDMI Receiver and Transmitter interfaces are either 24-bit or 36-bits wide

(depending on the HSMC video cards used). These IC’s are configured by an

I2C master controller by software running on the Nios II processor. The HDMI

v1.1 design uses a single HSMC board with both the HDMI transmitter and


Page 28 of 40

receiver and requires one I2C core. The HDMI v1.4 design uses two HSMC

boards and requires two independent I2C cores.

HDMI v1.1 Hardware Configuration

The HDMI v1.1 system requires the HDMI Receiver/Transmitter HSMC

Daughter Card to be installed on HSMC Connector J2.

HDMI v1.4 Hardware Configuration

The HDMI v1.4 system requires the HDMI v1.4 Receiver board (A6291) to be

installed on HSMC Connector J1 and the HDMI v1.4 Transmitter board (A6290)

to be installed on HSMC Connector J2.

QUAD VIDEO DISPLAY REFERENCE DESIGN

The Quad Video Display Reference Design uses the Bitec Quad Video HSM

Daughter Card shown in Figure 7 below.

The card uses the Texas Instruments TVP5155 quad video decoder to support

four composite video and S-video 8-bit receiver interfaces. The Quad Video

Display Reference Design receives four 480i60 YCbCr S-video input video

streams and merges them into a 4x4 matrix for display on a 1080i60 monitor.

The design demonstrates frame synchronization, video scaling, field alignment

and video mixing. A block diagram of the Quad Video Display video system is

shown in Figure 13 below.

Figure 12: Bitec Quad Video HSMC Daughter Card


Page 29 of 40

Figure 13: Block diagram of the Quad Video Display design

Quad Video Display Circuit Descriptions

PLL CLOCK DOMAINS

The DDR2 memory uses one PLL running at 167MHz. The 1080i60 HDMI

transmitter uses one PLL running at 74.25 MHz. The Qsys system operates

from a PLL that generates a 100 MHz for the Nios II processor, peripherals,

and the video IP.




OP BLOCKS

This design uses the Clocked Video Input and Clocked Video Output VIP block

to interface to the HDMI transmitter and receiver. The deinterlacer uses a triple

frame buffer to convert between the input frame rate and the output frame rate.

The Scaler sizes the incoming video using the Bilinear algorithm and the Mixer

overlays the four incoming video streams onto a 1080i background layer

generated by a Test Pattern Generator. I2C Master Controllers are used to

configure the S-video receiver and the HDMI video transmitter controller.


Page 30 of 40

Hardware Configuration

1) Install the Bitec Quad Video Board on HSMC2, (connector J2 of the ViClaro

IV-GX board).

2) Install the Microtronix HDMI 1.1 Receiver/Transmitter (A6256) HSMC

Daughter Card on HSMC1, (connector J1) of the ViClaro IV-GX board.

3) Connect four 480i YCbCr component video sources to the S-video input

(J2, J3, J4, & J5) of the Bitec board.

4) Connect an HD capable monitor to the HDMI output port (J6) of the HDMI

Receiver/Transmitter board.

5) Apply power to the ViClaro IV board and load the

quad_video_exammple.sof program file into the FPGA. The board should

display the four input video sources in a 4x4 matrix as shown in Figure 15

below.

Figure 14: ViClaro IV-GX Quad Video Display Hardware System


Page 31 of 40

Figure 15: Example output of Quad Video Display Design

720P TEXT OVERLAY OSD REFERENCE DESIGN

The 720p Text Overlay OSD Reference Design supports 1280x720p @ 60 Hz

video with text overlay. The design uses the Microtronix HDMI 1.4 Transmitter

HSMC Daughter Card (A6290) and the HDMI 1.4 Receiver HSMC Daughter

Card (A6291) installed on the ViClaro IV-GX board.

The source input should be 1280x720 50/59.97/60 fps. The HDMI output is set

to 1280x720p 60 fps.

The design takes text strings programmed into the NIOS II and mixes them with

the input video to generate the video output. There are two font sizes: one 26

pixels and the other 40 pixels in height. The text strings can be positioned

using x,y coordinates. The color of each text string is fully user programmable.

A block diagram of the design is shown in Figure 16 below.

Figure 16: Block diagram of 720p Text Overlay OSD Design


Page 32 of 40

720p Text Overlay Circuit Descriptions

PLL CLOCK DOMAINS

The DDR2 memory uses one PLL to generate 167 MHz clocks. This PLL also

generates a 100 MHz clock for the Nios II processor and peripherals. Another

PLL generates a 74.25 MHz clock for the 720p HDMI transmitter and a 94.50

MHz clock for the video IP in the Qsys system.




IP BLOCKS

A Clocked Video Input interfaces the HDMI 1.4 receiver to the Avalon S-T bus.

A triple frame buffer is used to add/drop frames to ensure contiguous video

between the input and output. (Note, there may be a small clock variance

between the two video controllers, even when the incoming video is 720p 60

fps.)

The Nios II processor uses a Custom Instruction to enhance the speed of

writing the text characters into the text buffer memory. Two text buffers are

used so that one can be updated by the processor while the other is being used

by the Frame Reader to generate video. The Frame Reader reads the text from

the active text buffer memory into a line buffer where it is passed to a Color

Plane Sequencer and divided into an alpha channel and the RGB component.

These are then alpha blended and mixed with the incoming video. The Mixer

has a background layer generated by a Test Pattern Generator. Test Pattern

Generators and Color Plane Sequencers are also used to generate the alpha

channels for the background layer and the incoming video.


1) Install the HDMI 1.4 Transmitter board onto HSMC2 (connector J2).

2) Install the HDMI 1.4 Receiver board onto HSMC1, (connector J1).

6) Connect 1280x720 50/59.97/60 fps video source to the HDMI Receiver

board and an HD capable monitor to the HDMI 1.4 Transmitter output.

7) Apply power to the ViClaro IV board and load the TextOverlay_720p.sof

program file into the FPGA. The board should display text overlay as

shown in Figure 17 below. The green text will move in steps across the

screen to demonstrate dynamic placement of text strings.


Page 33 of 40

Figure 17: Example output of 720p Text Overlay design

HDMI 1.4 1080P TRANSMITTER REFERENCE DESIGN

The HDMI 1.4 1080p Transmitter Reference Design utilizes a test pattern

generator as the video source to drive the Microtronix HDMI 1.4 Transmitter

(A6290) board at 1920x1080p60. A block diagram of the Reference Design is

show in the following figure.

Figure 18: HDMI 1.4 1080p Transmitter Block Diagram

PLL CLOCK DOMAINS

The design uses one PLL to generate a 90 MHz clock for the Nios II processor

and peripherals. Another PLL generates 148.50 MHz for the HDMI transmitter

and the video IP.


Page 34 of 40

IP BLOCKS

The design interfaces a VIP Test Pattern Generator operating at 1920x1080

12-bit RGB using the Avalon S-T bus through a Clocked Video Output to the

HDMI 1.4 transmitter.

The Nios II processor runs out of on-chip memory and uses the I2C Master

Controller to configure the HDMI transmitter.


1) Install the HDMI 1.4 Transmitter board onto HSMC2 (connector J2) of the

ViClaro IV-GX board.

2) Attach an HDMI cable from the HDMI board to a monitor.

3) Apply power to the ViClaro IV-GX board.

4) Load the hdmi_tx.sof program file into the FPGA. The board should display

a test pattern on the video monitor.

HD-SDI PASS-THROUGH DESIGN

The HD-SDI Pass-Through Reference Design uses the Terasic Dual

Transceiver SDI-HSMC Daughter Card to demonstrate the use of the Cyclone

IV-GX transceivers for a SDI or AES systems used in video broadcast

applications. The card supports 2 SDI or AES inputs and outputs by utilizing

the GX transceiver interfaces on the Cyclone IV-GX device. The card is shown

in the Figure 19 below and a block diagram of the HD-SDI Pass-Through

Reference Design in Figure 20 below.

Figure 19: Terasic Dual Transceiver SDI HSMC Daughter Card


Page 35 of 40

Figure 20: Block diagram of the HD-SDI Pass-Through Design

PLL CLOCK DOMAINS

The design uses two programmable clock generators on the ViClaro IV GX

board. One clock generator is used to generate a 74.25 MHz reference clock

for the transmitter of the Altera SDI Interface megafunction. The other

programmable clock generates 50 MHz and 74.25 MHz.

The design uses one FPGA PLL to generate two 166.7 MHz clocks for the

DDR2 memory controller, a 50 MHz SDI calibration clock, a 50 MHz SDI

reconfiguration clock, and a 100 MHz clock for the Nios II processor and

peripherals.

A second FPGA PLL is used to generate a 200 MHz audio clock.

IP BLOCKS

The design uses the Altera SDI Interface megafunction to interface to the

Terasic Dual SDI board. The received video is connected to a Qsys system

containing a Clocked Video Input, a Frame Buffer, and a Clocked Video Output.

The received SDI video also connects to four instances of the Altera SDI Audio

Extract megafunction that separate audio embedded in the incoming video.

The output video from the Qsys system connects to the Altera Audio Embed

megafunction that embeds the previously extracted audio.

The Nios II processor runs out of on-chip memory and uses two instances of

the I2C Master Controller to configure the programmable clock generators on


Page 36 of 40

the ViClaro IV GX board. The processor also programs the Clock Video Output

for the supported output video modes.


1) Install the Terasic Dual Transceiver SDI HSMC Daughter Card onto

HSMC2 (connector J2) of the ViClaro IV-GB Board.

2) Connect the SDI source to the SDI_IN_1 connector of the Terasic board.

The source may be either 720p 50/59.97/60 Hz, or 1080i 50/59.97/60 Hz.

3) Connect the SDI load to the SDI_OUT_1 connector of the Terasic board.

The output will be the same resolution as the input and 60 Hz.

4) Apply power to the ViClaro IV-GX board.

5) Load the sdi_passthrough.sof program file into the FPGA. The board

should pass the incoming SDI video to the SDI output.

Figure 21: HD-SDI Pass-Through Hardware

Before running the HDMI 1.1 Receiver/Transmitter board or the HDMI 1.4

Receiver board Reference Designs, it is first necessary to program the Cyclone

IV EP4CGX110 device on the ViClaro IV-GX to configure the EDID EEPROM

Configuring HD EDID for Correct

Refresh Rate


Page 37 of 40

device on the HDMI Receiver/Transmitter and on the HDMI 1.4 Receiver board

to make the transmitter operate at either a 50 or 60 Hz refresh rate. These

SOF files can also be used to verify correct operation of the video source and

display as they pass video directly from input to output.

1. From within Quartus, under the Tools menu, open Programmer.

i.e. > Tools > Programmer

2. Click Auto Detect.

3. Select the EP4CGX110 and right click > Change File.

4. Browse to the location of the hdmi_EDID_50.sof (50 Hz) or the

hdmi_EDID_60.sof (60 Hz) EDID programming file (under the example

directory). Select the appropriate file for the refresh rate of your auxiliary

monitor. It will be located in the directory where the files were extracted.

5. Select/highlight the appropriate file > Open. The file will be listed under the

file column of the EP4CGX110 device.

6. Click the check box under the Program / Configure column.

7. Click on the Start box to program the device. The LED4 labeled CONF

DONE will turn amber when the Cyclone IV device has programmed and

configured the EDID device on the HDMI Rx/TX Board. The ViClaro IV

system is now programmed to pass incoming video to the output port to

verify the PC is configured correctly.

8. Connect the cable from the second DVI/HDMI video port of the PC system

to the RX port of the HDMI Rx/Tx board.

It is now possible to load the ViClaro IV board with one of the DVI based

reference designs.

The procedure to load a .sof Reference Design onto the ViClaro IV-GX board is

as follows:

WARNING: Make sure there is no HDMI cable from the laptop/PC to the

ViClaro IV-GX board until the ViClaro IV-GX board is fully programmed and

operational.

1. From within Quartus, under the Tools menu, open Programmer.

i.e. > Tools > Programmer


3. Select the EP4CGX110 and right click > Change File.

4. Browse to the location of the vip_dynamic_scaler_1080p.sof

programming file. Select the appropriate file for the matching the refresh

rate of your auxiliary monitor. It will be located in the directory where the

files were extracted.

Loading ViClaro IV-GX

Reference Designs


Page 38 of 40

5. Select/highlight the file > Open. The file will be listed under the file column

of the EP4CGX110 device.

6. Click the check box under the Program / Configure column.

7. Click on the Start box to program the device. The LED4 labeled CONF

DONE will turn amber when the Cyclone IV device is programmed and

running.

All of the Qsys based Reference Design examples include software to

configure the hardware. These software projects can be imported into the Nios

II IDE to be recompiled or modified.

1. From within Nios II IDE, under the File menu, select Import.

2. Select Altera Nios II -> Existing Nios II IDE project into workspace, click

Next.

3. Browse to the software directory of the example design of interest. There

will be two subdirectories, the import process must be repeated for each

(e.g. mixer_hdmi, mixer_hdmi_bsp).

4. Select one of the subdirectories under software and click OK.

5. Click Finish to start the import.

6. A dialog may appear asking to remove the Release and/or Debug

directories, click Yes.

7. Repeat for this process for the second subdirectory under software.

Importing

Software


Page 39 of 40

The following procedure can be used to load a SOF file to the FPGA through

JTAG. These steps require the board to be powered and connected to the PC

through a USB cable (USB-Blaster, etc).

1. Start Quartus.

2. From the Tools menu, select Programmer.


4. Select the line with the EP4CGX110 device.

5. Click Change File and browse to the SOF file (reference design) you

wish to load.

6. Check the Program/Configure box.

7. Click Start to program the FPGA.

8. The orange Config Done LED (LED7) will be activated if the load

completes successfully.

Appendix A: Loading Designs

into the FPGA


Page 40 of 40

Designs can be loaded into the on-board flash to configure the FPGA on

power-up. Below is the procedure for programming the flash through the

JTAG.

Converting a SOF File to a JIC for the Flash Device

The SOF file generated by Quartus II must be converted to a JIC file for flash

programming.

1. Open your Quartus project.

2. From the File menu, select Convert Programming Files.

3. Select JTAG Indirect Configuration File (.jic) from the Programming

file type list. The default file name will be output_file.jic.

4. Select EPCS128 as the configuration device and Active Serial as the

mode.

5. Select Flash Loader under Input files to convert. Click Add Device

and select the EP4CGX110.

6. Select SOF Data under Input files to convert. Click Add File and

browse to the SOF file you would like to convert.

7. Select the SOF file under Input files to convert and click Properties if

you wish to enable compression.

8. Click OK to generate the JIC.

Programming the Flash Device

The following procedure can be used to load a converted JIC file to the flash

device through JTAG. These steps require the board to be powered and

connected to the PC through a USB Type A-B cable connected to the UBS

Blaster port. (Note, the board contains an integrated USB-Blaster.)

1. From the Tools menu, select Programmer.


3. Select the line with the EP4CGX110 device.

4. Click Change File and browse to the JIC file created with the

programming file converter.

5. Check the Program/Configure box.

6. Click Start to program the flash.

Appendix B: Loading Designs into On-Board

Flash

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Microtronix ViClaro IV-GX Video Host Board · 2018-11-28 · CYCLONE IV-GX FPGA The ViClaro IV Host...

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