+ All Categories
Home > Documents > Remote System Update Cyclone IV GX Development Kit · 2021. 1. 28. · • Signal Tap II Files –...

Remote System Update Cyclone IV GX Development Kit · 2021. 1. 28. · • Signal Tap II Files –...

Date post: 06-Feb-2021
Category:

Documents
Upload: others
View: 5 times
Download: 0 times
Download Report this document
Share this document with a friend
21
Remote System Update Cyclone IV GX Development Kit
Transcript

  • Remote System Update Cyclone IV GX Development Kit

  • Development Kit and Reference Documents

    • Cyclone IV GX FPGA Development Kit – Device EP4CGX150DF31C7N

    – http://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.html

    • Reference User Guide and AN – Remote System Upgrade Megafunction User

    Guide (ALTREMOTE_UPDATE)

    – AN 521: Cyclone III Active Parallel Remote System Upgrade Reference Design

    2

    http://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.htmlhttp://www.altera.com/literature/ug/ug_altremote.pdfhttp://www.altera.com/literature/ug/ug_altremote.pdfhttp://www.altera.com/literature/ug/ug_altremote.pdfhttp://www.altera.com/literature/ug/ug_altremote.pdfhttp://www.altera.com/literature/ug/ug_altremote.pdfhttp://www.altera.com/literature/an/AN521.pdfhttp://www.altera.com/literature/an/AN521.pdfhttp://www.altera.com/literature/an/AN521.pdfhttp://www.altera.com/literature/an/AN521.pdfhttp://www.altera.com/literature/an/AN521.pdf

  • Changes from AN521 design

    • AP to AS in configuration scheme – Removed PFL – Changed Device and Pin options for AS

    • Perform all commands – Some commands are not performed in AN521 design – Changed design in ru_cb.v – See RSU Function slide for command list

    • Past Status 2 indicator – Added past status 2 indicator LEDs in Factory design

    • SignalTap II for Factory and Application • PLL setting

    – Added 100MHz output for ST II sampling clock

    • Modified for Cyclone IV GX FPGA Development Kit – Assigned clock, user push buttons and user LEDs

    3

  • Design Files

    • Quartus II Archive – CIII_CIV_RU_AS_Factory.qar (Factory design) – CIII_CIV_RU_AS_AP1.qar (Application 1 design) – CIII_CIV_RU_AS_AP2.qar (Application 2 design)

    • Programming Files – CIII_CIV_FactroyImage.sof (Factory design) – CIII_CIV_AppImage1.sof (Application 1 design) – CIII_CIV_AppImage2.sof (Application 2 design) – RU_CIV_devkit_3img.jic (.jic file for EPCS)

    • Generated from above 3 .sof files

    • Signal Tap II Files – ciii_civ_ru_as_Factory.stp – ciii_civ_ru_as_App1.stp – ciii_civ_ru_as_App2.stp

    • MAX II design – max2_c4gx.pof (To enable EPCS in AS)

    4

  • RSU Function

    5

    Suppoted Feature Original Example Design

    read_param

    write_param

    read_ source

    param Operation data_out

    width (bits)

    Factory Application Factory Application

    1 0 00 000

    Master StateMachine Current StateMode (Read Only) • 00—Factory mode

    • 01—Application mode • 11—Application mode with Master State

    Machine User Watchdog Timer Enabled

    2 Y Y

    1 0 01 000 Master StateMachine Past Status 1 2 Y - 1 0 10 000 Master StateMachine Past Status 2 2 Y - 1 0 00 100 Read factory boot address 24 Y -

    1 0 01 100 Read Past Status 1 boot address

    The last application address 24 Y Y -

    1 0 01 111 Read Past Status 1 reconfiguration trigger

    The last reconfiguration trigger 5 Y Y -

    1 0 10 100 Read Past Status 2 boot address The 2nd last application address

    24 Y -

    1 0 10 111 Read Past Status 2 reconfiguration trigger

    The 2nd last reconfiguration trigger 5 Y -

    1 0 01 010 Read current applicationmodewatchdog value 29 Y - Y 1 0 01 011 Read current applicationmodewatchdog enable 1 Y - Y

    1 0 10 100 Read current application mode boot address from input

    register 24 Y - Y

    1 0 11 001 Read the early confdone check bits from input register 1 Y -

    1 0 11 010 Read watchdog time-out value from input register 12 Y - 1 0 11 011 Read watchdog enable bit from input register 12 Y 1 0 11 100 Read boot address from input register 22 Y -

    1 0 11 110 Read to check whether the internal oscillator is Factory set as startup state machine clock from input register

    1 Y -

    0 1 00 001 Write the early confdone check bit 1 Y Y - 0 1 00 010 Write the watchdog time-out value 12 Y Y - 0 1 00 011 Write the watchdog enable bit 1 Y Y - 0 1 00 100 Write application boot address 22 Y Y -

    0 1 00 110 Write to force the internal oscillator as startup Factory

    state machine clock 1 Y -

    Added commands not

    supported in AN521 to

    modified design

    (Cells in orange and

    blue)

  • Design Signals Description (1)

    6

    Pin AK16

    50MHz clock on board

    Pin C12

    PB0

  • Design Signals Description (2)

    7

    Assigned to HSMC port

    Assigned to HSMC port

  • Design Signals Description (3)

    8

    Pin F6, A4, C7, E4

    LED 3-0

    ps2_leds[3..0]

    Pin B6, D12, J9, D4 LED7-4

    Output from the user logic control block. This bus determines the logic state of past status 2 indicator LEDs.

    User logic control block

  • Boot Address

    9

    parameter PG1_START_ADD = 22'h080000; // Flash Memory Address PG1_START_ADD,2'b00 = 24'h200000

    parameter PG2_START_ADD = 22'h100000; // Flash Memory Address PG2_START_ADD,2'b00 = 24'h400000

    BLOCK POF Start Address

    RSU Boot address setting (Ru_address)

    Factory Page_0 24’h000000

    Application1 Page_1 24’h200000 22’h080000

    Application2 Page_2 24’h400000 22’h100000

    BLOCK START ADDRESS END ADDRESS

    Page_0 0x00000000 0x0014C602

    Page_1 0x00200000 0x0034A34E

    Page_2 0x00400000 0x0054A302

    • Memory Map file generated by Convert Programming File

    • Boot address setting in the design ( ru_cb.v )

  • Factory Design Block Diagram

    10

  • Factory Design State Machine Flow

    11

    Factory image configuration

    => Read MSM Current = > Read MSM Past Status 1 => Read MSM Past Status 2

    => Read factory boot address

    => read previous reconfiguration source => Read previous state boot address

    => Reports error if watchdog timer error or nstatus error has occurred

    => read previous reconfiguration source 2 => Read previous state boot address 2

    => Reports error if watchdog timer error or nstatus error has occurred

    => system will idle and wait for start_write

    => Enable or Disable early_condone_check

    => set_watch_dog_timer_value

    => enable_watch_dog timer feature

    => set next boot address (this will load the application configuration 1 OR application configuration 2)

    => force internal oscillator

    => Read early_condone_check

    => Read watch_dog_timer_value

    => Read enable_watch_dog

    => Read next boot address

    => Read force internal oscillator

    => trigger reconfiguration through core nCONFIG assertion

  • Factory Design Waveform (1)

    12

    Waveform after Factory image configured

    Read MSM

    Current

    Read MSM

    Past Status 1

    Read MSM

    Past Status 2

    Read factory

    boot address

    read previous

    reconfiguration

    source

    Read previous

    state boot

    address

    read previous

    reconfiguration

    source 2

    Read previous

    state boot

    address 2

    ciii_civ_ru_as_Factory.stp (power-up trigger)

  • Factory Design Waveform (2)

    13

    Waveform after stat_write

    ciii_civ_ru_as_Factory.stp Enable early

    condone check

    Set watch dog

    timer value

    Enable watch

    dog timer

    Set next boot

    address

    Force internal

    oscillator

    Read early

    condone check

    Read watch dog

    timer value

    Read watch

    dog timer

    Read next boot

    address

    Read internal

    oscillator

  • Application 1 Design Block Diagram

    14

  • Application 2 Design Block Diagram

    15

  • Application Design State Machine Flow

    16

    => Read current Application image boot address

    => read_watchdog_enable

    => read_watchdog_timer_value

    => trigger reconfiguration to revert application image to factory image.

  • Application Design Waveform

    17

    Waveform after start_write

    Read current Application

    image boot address

    Read watch dog enable

    ciii_civ_ru_as_App1.stp, ciii_civ_ru_as_App2.stp

    Read watch dog timer value

  • Status Indicator

    18

    LED3-0/LED7-4

    LED3-0 : Past Status 1

    LED7-4 : Past Status 2

    LED7-4 are only available in factory design

  • Quick Start

    1. Program MAX II with max2_c4gx.pof for AS • Need to set MSEL pins for AS using modified design since original one sets

    MSEL pins for FPP

    2. Program EPCS with RU_CIV_devkit_3img.jic 3. Cycle board power to load Factory image

    • CONF_DONE and LED7-0 are on

    4. Push PB0 to load Application 1 • LED0 is blinking, LED2-3 are on steadily

    5. Push PB0 to return Factory image • nCONFIG, nSTATUS or CRC_ERROR also cause reconfiguration • LED7-0 show previous status

    6. Push PB0 to load Application 2 • LED1 is blinking, LED2-3 are on steadily

    7. Push PB0 to return Factory image • nCONFIG, nSTATUS or CRC_ERROR also cause reconfiguration • LED7-0 show previous status

    19

  • ALTREMOTE_UPDATE Busy Period for Cyclone III/IV

    20

    read_source param Operation Busy Period (clk)

    00 000 Master State Machene Current State Mode

    63

    00/01/10 100 Read boot address 33

    01/10 111 Read Past Status 1 or 2 reconfiguration trigger condition

    59

    01 010 Read current application mode watchdog value

    33

    01 011 Read current application mode watchdog enable

    62

    Busy Period (clk) 47

    Read

    Write

    Following tables show busy period from the waveforms.

  • Summary

    • The designs perform all RSU commands in Cyclone IV

    • Able to see waveforms using Signal Tap II

    • Clarified busy periods for each command

    21


Recommended
Intel Cyclone 10 GX Device - Intel | Data Center Solutions ... · Intel Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation

Intel Cyclone 10 GX Device - Intel | Data Center Solutions ... · Intel Cyclone 10 GX device family delivers higher core, transceiver, and I/O performance than the previous generation

Documents

Cyclone IV GX FPGA Development Board Reference Manual101 Innovation Drive San Jose, CA 95134 MNL-01058-1.2 Reference Manual Cyclone IV GX FPGA Development Board Feedback Subscribe

Cyclone IV GX FPGA Development Board Reference Manual101 Innovation Drive San Jose, CA 95134 MNL-01058-1.2 Reference Manual Cyclone IV GX FPGA Development Board Feedback Subscribe

Documents

Cyclone 10 GX Advance Information Brief · 2017-02-13 · Cyclone 10 GX Advance Information Brief The Cyclone ® 10 GX device family consists of high-performance and power-efficient

Cyclone 10 GX Advance Information Brief · 2017-02-13 · Cyclone 10 GX Advance Information Brief The Cyclone ® 10 GX device family consists of high-performance and power-efficient

Documents

Cyclone V GX FPGA Development Board Reference … Cyclone V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive

Cyclone V GX FPGA Development Board Reference … Cyclone V GX FPGA development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive

Documents

Cyclone V Device Overview - Intel...Cyclone V E Optimized for the lowest system cost and power requirement for a wide spectrum of general logic and DSP applications Cyclone V GX Optimized

Cyclone V Device Overview - Intel...Cyclone V E Optimized for the lowest system cost and power requirement for a wide spectrum of general logic and DSP applications Cyclone V GX Optimized

Documents

Intel® Cyclone® 10 GX CvP Initialization over PCI … › content › dam › altera-www › global › en...Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

Intel® Cyclone® 10 GX CvP Initialization over PCI … › content › dam › altera-www › global › en...Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

Documents

Cyclone IV GX FPGA Development Kit Board xx Parts, xx ... · Cyclone IV GX Power Cyclone IV GX Clocks MAX II DDR2 SDRAM x32 TOP SSRAM & FLASH Embedded USB Blaster 10/100/1000 Ethernet

Cyclone IV GX FPGA Development Kit Board xx Parts, xx ... · Cyclone IV GX Power Cyclone IV GX Clocks MAX II DDR2 SDRAM x32 TOP SSRAM & FLASH Embedded USB Blaster 10/100/1000 Ethernet

Documents

256 10 GX Device Datasheet - infinite-electronic.ru · Intel® Cyclone® 10 GX Device Datasheet Subscribe Send Feedback C10GX51002 | 2018.06.15 Latest document on the web: PDF | HTML

256 10 GX Device Datasheet - infinite-electronic.ru · Intel® Cyclone® 10 GX Device Datasheet Subscribe Send Feedback C10GX51002 | 2018.06.15 Latest document on the web: PDF | HTML

Documents

Cyclone V GX FPGA Development Board Reference Manual · One high-speed mezzanine card (HSMC) co nnectors are available to add additional ... development board reside in the Cyclone

Cyclone V GX FPGA Development Board Reference Manual · One high-speed mezzanine card (HSMC) co nnectors are available to add additional ... development board reside in the Cyclone

Documents

Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide · 2020-06-21 · 1 Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide The Intel Cyclone® 10 GX Native

Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide · 2020-06-21 · 1 Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide The Intel Cyclone® 10 GX Native

Documents

AES3/EBU Reference Design Application Note...the Stratix GX Video Demonstration Board Data Sheet; for more information on the Cyclone Video Demonstration Board see the Cyclone Video

AES3/EBU Reference Design Application Note...the Stratix GX Video Demonstration Board Data Sheet; for more information on the Cyclone Video Demonstration Board see the Cyclone Video

Documents

Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User ... · Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User Guide UG-20061 2017.05.08 Subscribe Send Feedback

Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User ... · Early Power Estimator for Intel® Cyclone® 10 GX FPGAs User Guide UG-20061 2017.05.08 Subscribe Send Feedback

Documents

Microtronix ViClaro IV-GX Video Host Board · 2018-11-28 · CYCLONE IV-GX FPGA The ViClaro IV Host board is fitted with an Cyclone IV-GX EP4CGX110 device in a 780-pin Fine Line BGA

Microtronix ViClaro IV-GX Video Host Board · 2018-11-28 · CYCLONE IV-GX FPGA The ViClaro IV Host board is fitted with an Cyclone IV-GX EP4CGX110 device in a 780-pin Fine Line BGA

Documents

ASMI Parallel Intel® FPGA IP Core User Guide · (2) The synthesis operations for Cyclone III, Cyclone IV GX, Cyclone IV E, and Intel Cyclone 10 LP devices use the cycloneii_asmi

ASMI Parallel Intel® FPGA IP Core User Guide · (2) The synthesis operations for Cyclone III, Cyclone IV GX, Cyclone IV E, and Intel Cyclone 10 LP devices use the cycloneii_asmi

Documents

Pin Information for the Intel Cyclone 10 GX 10CX105 Device · 2021. 2. 1. · Pin Information for the Intel® Cyclone®10 10GX105 Device PT-10GX105-2019.04.22

Pin Information for the Intel Cyclone 10 GX 10CX105 Device · 2021. 2. 1. · Pin Information for the Intel® Cyclone®10 10GX105 Device PT-10GX105-2019.04.22

Documents

AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX

AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX

Documents

Cyclone IV GX Transceiver Starter Kit Board · 2018-03-20 · Cyclone IV GX FPGA Development Kit Board B Wednesday, March 03, 2010 3 15 Cyclone IV GX Configuration (uses JTAG mode

Cyclone IV GX Transceiver Starter Kit Board · 2018-03-20 · Cyclone IV GX FPGA Development Kit Board B Wednesday, March 03, 2010 3 15 Cyclone IV GX Configuration (uses JTAG mode

Documents

Cyclone IV GX FPGA Development Kit User Guide · Cyclone IV GX FPGA Development Kit Subscribe Cyclone IV GX FPGA Development Kit User Guide. ... Altera, The Programmable Solutions

Cyclone IV GX FPGA Development Kit User Guide · Cyclone IV GX FPGA Development Kit Subscribe Cyclone IV GX FPGA Development Kit User Guide. ... Altera, The Programmable Solutions

Documents