modeling and characterization of on-chip interconnects, inductors and transformers kai kang

MODELING AND CHARACTERIZATION OF ON-CHIP INTERCONNECTS, INDUCTORS AND TRANSFORMERS

KAI KANG

NATIONAL UNIVERSITY OF SINGAPORE

AND

ÉCOLE SUPÉRIEURE D’ÉLECTRICITÉ

2008

MODELING AND CHARACTERIZATION OF ON-CHIP

INTERCONNECTS, INDUCTORS AND TRANSFORMERS

KAI KANG

(B. Eng., Northwestern Polytechnical University, P. R. China)

A THESIS SUBMITTED

FOR THE JOINT DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE AND

ÉCOLE SUPÉRIEURE D’ÉLECTRICITÉ

2008

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Acknowledgements

This part of the thesis is probably the hardest to write. It is very difficult for me to find the

words conveying the sincerity and magnitude of my gratitude to those who make this thesis

possible through their significant supports and encouragements. First and foremost, I would

like to thank Prof. Li Le-Wei, my principal thesis supervisor. I really appreciate that he offered

me this great opportunity to study in his group at NUS. His kind decision definitely opens a new

era of my life. I am grateful to him for creating this particularly stress-free environment which

provides a large degree of freedom for me to enjoy my studies and research work. Throughout

my time at NUS, I have been repeatedly surprised by the depth and breadth of his knowledge in

all aspects of electrical engineering and his instincts for research and development for RF &

microwave industries. He also always shares his valuable experiences and his intellectual

maturity with me which are undoubtedly useful to my future career.

I would also like to thank Prof. Saïd Zouhdi, who offered me the great opportunity to

explore French culture and study for a year in Paris, the most beautiful city in the world.

Without his support and advice, my studies at Supélec and LGEP could not be so fruitful. I

would also like to thank Prof. Yin Wen-Yan at Shanghai Jiao-tong University, China. It was his

vision and encouragement that first led me to investigate the modeling of on-chip passive

components and consider the new ideas that eventually led to this thesis. He provides not only

invaluable advice but also role model for me to explore the unknown scientific world with great

interests and perseverance during my graduate studies and even my entire life. I am grateful to

his patience and guidance throughout these years. Special thanks to Dr. Koen Mouthaan for his

valuable discussion and funding support to the test structures fabrication. He has been

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exceptionally helpful in my stay at NUS, during which his door has always been open for me.

Prof. Yeo Tat-Soon has given me a lot of invaluable feedback on my research and has been very

generous with his time on my qualify exam committee.

I would also like to thank all of the helpful people I have encountered while working at

Institute of Microelectronics. First, I would like to thank Dr. Shi Jinglin, who has given me

invaluable advice and help on test structures designs and measurements. Furthermore, I would

like to thank Dr. Subhash C. Rustagi, who gave me the chance to work on a project that would

help direct my graduate studies. His experiences and advice regarding compact modeling and

composing technical papers were very helpful to my research. I am also grateful to other staff at

IME: Dr. James Brinkhoff, Dr. Lin Fujiang, Dr. Zheng Yuanjin, Dr. Xiong Yong-Zhong and Dr.

Sun Sheng.

I have been very lucky to work in a research group with many extraordinarily outstanding

students. I am deeply grateful for the help, encouragement and collaboration of Qiu Cheng-Wei,

Fei Ting, Yuan Tao, Zhang Lei, Feng Zhuo, Xu Wei, Nan Lan, Gao Yuan, Zhao Guang, Fan

Yijin, Li Yanan, She Hao-Yuan and many others. I am also grateful to Dr. Yao Hai-Yin, Dr. Xin

Hong, Dr. Zhang Min, Dr. Zhao Weijiang, Dr. Yuan Ning and Dr. Nie Xiaochun for their

valuable help and friendship. Special thanks to Mr. Jack Ng for keeping the computer systems

up and running. I would like to extend my appreciation to former members of Li group: Dr. Sun

Jin, Mr. Pan Shu-Jun, Dr. Liu En-Xiao and many others.

My friends at and outside NUS have provided important recreational and emotional support

throughout the years: He Li, Dr. Chen Jianfeng, Shi Shaomei, Dr. Guo Rui, Dr. Wang Qiuhong,

Li Ling, Wang Yadong, Zhang Tianxia, Dr. Ren Chi, Zhang Li, Darwin Chai, Liu Xiaofeng, Wu

Man, Guo Minxuan, Yuan Yin, Dong Yang and many others. I will fondly remember all those

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dinner gatherings, parties and trips during holidays.

Last, but not certainly not least, I would like to thank all my family members for their love,

support and constant encouragement in the long course of my study. I am very grateful to my

parents in-law for treating me as their own son and for providing the much needed support. I

would like to thank my mother and my father who have been there throughout my life and

love me unconditionally despite all my failings. One really could not ask for more and I

eternally indebted to them. And lastly, I offer my dearest thanks to my wife, Jing, to whom I

owe this degree most to. Her constant love, support, kindness and funniness helped me to

always keep my perspective and enjoy what I was doing.

V

Table of Contents

ACKNOWLEDGEMENTS ........................................................................................ II

TABLE OF CONTENTS .............................................................................................. V

SUMMARY .............................................................................................................. VIII

LIST OF TABLES ...................................................................................................... IX

LIST OF FIGURES ...................................................................................................... X

CHAPTER 1. INTRODUCTION ................................................................................ 1

1.1 On-Chip Interconnects ......................................................................................... 1

1.1.1 Background ................................................................................................. 1

1.1.2 Motivation ................................................................................................... 3

1.2 On-Chip Inductors and Transformers .................................................................. 6

1.2.1 Background ................................................................................................. 6

1.2.2 Motivation ................................................................................................... 8

1.3 Thesis Organization ............................................................................................. 9

1.4 Original Contributions ....................................................................................... 10

1.5 Publication List .................................................................................................. 14

CHAPTER 2. MODELING OF ON-CHIP SINGLE INTERCONNECT ............. 18

2.1 Introduction ........................................................................................................ 18

2.2 A Wideband Scalable and SPICE-Compatible Model ....................................... 20

2.2.1 Skin Effect ................................................................................................. 21

2.2.2 Proximity and Substrate Skin Effects ........................................................ 23

2.2.3 Substrate Skin Effect and Complex Image Method .................................. 26

2.2.4 Model Set-up ............................................................................................. 33

2.3 Effect of Dummy Metal Fills ............................................................................. 35

2.4 Empirical Formulas for Elements in Series Branch ........................................... 36

2.5 Measurements and De-embedding ..................................................................... 38

2.6 Experimental Results and Model Validation ...................................................... 40

2.7 Summary ............................................................................................................ 45

CHAPTER 3. CHARACTERIZATION OF ON-CHIP COUPLED (A)SYMMETRICAL INTERCONNECTS .................................................... 46

VI

3.1 Introduction ........................................................................................................ 47

3.2 Coupled On-Chip Interconnects ........................................................................ 48

3.3 Distributed Parameters and Propagation Constants ........................................... 51

3.3.1 Resistances and Inductances ...................................................................... 52

3.3.2 Capacitances and Conductances ................................................................ 55

3.3.3 Propagation Constants ............................................................................... 63

3.3.4 Slow-wave Factors .................................................................................... 68

3.4 Pulse Responses ................................................................................................. 70

3.5 Average Power Handling Capabilities (APHC) ................................................. 75

3.6 Test Structure Fabrication and Measurements ................................................... 80

3.7 Experimental Results and Discussions .............................................................. 81

3.8 Summary ............................................................................................................ 84

CHAPTER 4. MODELING AND DESIGN OF ON-CHIP INDUCTORS ............ 86

4.1 Introduction ........................................................................................................ 87

4.2 Greenhouse Method Incorporating with CIM Technique .................................. 89

4.3 Temperature-Dependent Substrate Conductivity ............................................... 93

4.4 Eleven-Element Equivalent Circuit Model of On-chip Inductors ..................... 94

4.5 Results and Discussions ..................................................................................... 95

4.5.1 Square Spiral Inductor ............................................................................... 95

4.5.1.1 Variations in the Substrate Conductivity………………………………98 4.5.1.2 Temperature Effects…………………………………………………..101

4.5.2 Differential Inductor .................................................................................103

4.6 Design of A Vertical Tapered Solenoidal Inductor ............................................105

4.6.1 Theory and Formulation ...........................................................................106

4.6.2 Layout .......................................................................................................107

4.6.3 Measurement Results and Discussions .....................................................109

4.7 Summary ........................................................................................................... 111

CHAPTER 5. FREQUENCY-THERMAL CHARACTERIZATION OF ON-CHIP TRANSFORMERS WITH PATTERNED GROUND SHIELDS ............... 113

5.1 Introduction ....................................................................................................... 114

5.2 Geometries of On-Chip PGS Transformers ...................................................... 116

5.3 Modified Temperature-Dependent Equivalent-Circuit Models ........................ 117

5.3.1 Equivalent Circuit Model for an Interleaved Transformer ....................... 117

VII

5.3.2 Equivalent Circuit Model for a Center-tapped Interleaved Transformer ..122

5.3.3 Temperature Effects ..................................................................................124

5.4 Fabrication and Measurements .........................................................................132

5.5 Extraction of Performance Parameters and Discussion ....................................133

5.5.1 Maximum Available Gain (Gmax) ..............................................................133

5.5.2 Q Factor ....................................................................................................137

5.5.3 Power Loss ...............................................................................................139

5.6 Summary ...........................................................................................................140

CHAPTER 6. CONCLUSIONS .............................................................................. 141

6.1 Summary ...........................................................................................................141

6.2 Future Work ......................................................................................................144

BIBLIOGRAPHY ..................................................................................................... 145

VIII

Summary

In today’s semiconductor industries, the mask cost increases dramatically, which makes

the cost of a re-design more significant. On the other hand, on-chip passive components such

as interconnects, inductors and transformers are widely used in high speed digital,

mixed-signal and radio frequency integrated circuits (ICs). Therefore, accurate modeling of

circuit behavior, especially for these passive components, is crucial for first-time-right

designs.

This research focus on modeling and characterization of on-chip interconnects, inductors

and transformers. Firstly, a fully scalable and SPICE-compatible interconnects model is

established and this model is accurate over a wideband frequency range from DC up to 110

GHz which has been verified by using measured S-parameters. In addition, this model also

shows the capability to estimate the impact of metal dummy fills. Secondly, frequency- and

temperature-dependent characteristics of on-chip coupled asymmetrical and symmetrical

interconnects are investigated in detail, and a model for coupled interconnects is established

and compared with experimental results.

Furthermore, an eleven-element equivalent circuit model is established for simulating

on-chip spiral inductors. The substrate skin effect is correctly characterized by this model.

Additionally, a vertical tapered solenoidal inductor is designed to achieve a high resonance

frequency. Finally, extensive studies on the performances of on-chip transformers with and

without patterned ground shields at different temperatures are carried out. These transformers

are fabricated using 0.18-μm RF CMOS processes and are designed to have either interleaved

or center-tapped interleave geometries, respectively.

IX

List of Tables

Table 2.1 The Coefficients of Empirical Formulas for the Elements in Series Branch of the Proposed

Model ..................................................................................................................................... 37

Table 2.2 The Values of Lumped Elements of the Proposed Model for Interconnects with Different

Widths and Lengths by Using (2.51) and (2.53)-(2.56) ........................................................ 43

Table 3.1 Coefficients of Aluminum, Gold, and Copper ........................................................................ 50

Table 3.2 Effects of Variation in Different Parameters on the avP (VE: Very Effective; EL: Effective,

but Limited) ........................................................................................................................... 79

Table 5.1 Coefficients for Different Metals over a Temperature Range of 200 to 900 K .................... 125

Table 5.2 Silicon Resistivity Values at Different Temperatures ........................................................... 129

Table 5.3 Extracted Circuit Parameters of (non)PGS Transformer of Desgin 1 with N = 4 ................ 129

Table 5.4 Extracted Equivalent Circuit Parameters of Transformer of Design 2 with N = 4 ............... 129

X

List of Figures

Fig. 1.1 Moore’s law predicts the doubling of transistor count every two years. Here is an example,

the transistor count for Intel microprocessors as a function of the years. ................................ 2

Fig. 1.2 International Technology Roadmap for Semiconductors 2005 predictions for device and

interconnect delays. ................................................................................................................. 4

Fig. 1.3 Worldwide GSM customers from 1993 to 2006 ....................................................................... 7

Fig. 2.1 (a) The cross-section of an interconnect is divided into six segments to capture the laterally

non-uniform current distribution. (b) The frequency dependent resistance of the

interconnect calculated by our method is compared with simulation results by using Q3D

extractor. The length of the interconnect is 1000 μm and σ=5.8×107 S/m. ............................ 22

Fig. 2.2 A single interconnect parallel with N ground lines ................................................................. 24

Fig. 2.3 (a) An interconnect with six parallel ground lines. (b) The resistance and inductance of two

such structures with different width are calculated by using our model and the Q3D

extractor, respectively. In these cases, only skin and proximity effects are considered.

Length =1 cm and σ=5×107 S/m. ........................................................................................... 26

Fig. 2.4 A straight filament unit line current parallel to the lossy substrate with a finite thickness. ... 28

Fig. 2.5 One segment of the proposed model. Ns is the number of segments. .................................... 33

Fig. 2.6 (a) Cross section, and (b) top view of an interconnect on M6 with dummy metal fill-cells

from M5 to M1 fabricated by 0.18 μm CMOS technology. Dark cells are dummies. The

width, spacing and pitch of dummies are wd, sd and p, respectively. ..................................... 36

Fig. 2.7 The cross-section of the test interconnects fabricated in 0.18 μm CMOS technology. All the

test interconnects are located on M6. The widths of interconnects are either 6 μm or 10 μm,

while the lengths of interconnects are from 400 μm to 1000 μm. All numbers labeled in the

figure are in μm. .................................................................................................................... 38

Fig. 2.8 Configurations of the measured structures. (a) The THRU structure and (b) the interconnect

test-structure; the circuit models of (c) the THRU structure and (d) the interconnect

test-structure. The reference planes correspond to the symmetric plane depicted in (c). ...... 39

XI

Fig. 2.9 Simulated S-parameters by using our model are compared with measured results and

simulation results by Momentum for two interconnects with length of 900 µm and width of

10 µm, and length of 800 µm and width of 6 µm, respectively. The lumped-elements in the

series branch of our model are obtained by either analytical method in (2.51) (for solid line)

or empirical formulas in (2.59) (for dashed line), while those in the shunt branch are given

by (2.53)-(2.56) ...................................................................................................................... 41

Fig. 2.10 Smith Charts of simulated S-parameters by using (2.51) and (2.53)-(2.56) are compared

with measured results for four interconnects with different lengths and widths, l=300 µm,

w=10 µm, l=800 µm, w=10 µm, l=600 µm, w=6 µm and l=900 µm, w=6 µm,

respectively. The frequency range is from DC up to 110GHz. Symbols represent

measurement results and solid lines stand for simulations results. These smith charts show

the good scalability and high accuracy of our model. ........................................................... 42

Fig. 2.11 The measurement results for a test interconnect with dummy metal fills are compared with

simulated S-parameters by using our model including the dummy effects (solid lines) and

excluding the dummy effects (dashed lines), respectively. The length and width of the

interconnects are 900 μm and 6 μm, respectively. ................................................................. 44

Fig. 3.1 On-chip coupled interconnects: (a) cross-sectional view and (b) equivalent circuit model. .. 49

Fig. 3.2 Self-resistances 11R and 22R , and mutual resistance 12R for asymmetrical coupled

interconnects versus for different line thicknesses at room temperature. .............................. 54

Fig. 3.3 (a) Mutual- resistance ( 12R ) and (b) mutual–inductance )( 12L for asymmetrical coupled

interconnects versus frequency at different temperatures. ..................................................... 55

Fig. 3.4 Mutual capacitance )(12 fC as a function of frequency for asymmetrical coupled

interconnects for different line spacings and silicon conductivities. ..................................... 59

Fig. 3.5 Mutual conductance )(12 fG versus silicon conductivity for different (a)symmetrical

coupled interconnects at different frequencies. ..................................................................... 61

Fig. 3.6 Mutual conductance )(12 fG versus silicon conductivity for asymmetrical coupled

interconnects at different frequencies and temperatures. ....................................................... 63

XII

Fig. 3.7 Attenuation constants versus frequency for (a)symmetrical interconnects(dash line: based

on (3.42) and (3.43)): (a) 221 == WW µm, 0.1=siσ S/m; (b) 221 == WW µm,

10=siσ S/m; and (c) 41 =W µm, 22 =W µm, 0.1=siσ S/m. ....................................... 67

Fig. 3.8 Attenuation constants versus for asymmetrical interconnects with the same parameters as

shown in Fig. 3.6. .................................................................................................................. 68

Fig. 3.9 oeSWF , versus frequency for symmetrical interconnects for different line widths and

silicon conductivities with T = 300 K. ................................................................................. 69

Fig. 3.10 oeSWF , versus silicon conductivity for symmetrical interconnects for different frequencies,

with T=300K. ......................................................................................................................... 70

Fig. 3.11 Waveform distortion and crosstalk of a periodic square pulse propagating in coupled

symmetrical interconnects (a) ),(1 tyv and (b) ),(2 tyv . ................................................. 73

Fig. 3.12 Square pulse responses in coupled symmetrical interconnects (a) y = 0.5 mm and

(b) y = 1 mm. ......................................................................................................................... 74

Fig. 3.13 Thermal models for coupled interconnects with the spacing ,max eoee WWS ≥ . ......... 75

Fig. 3.14 avP versus frequency for coupled interconnects on silicon substrate for different line

widths. .................................................................................................................................... 79

Fig. 3.15 TEM cross-sections of coupled lines with line width and spacing of 0.15 µm. Inset shows

schematic top view of GSG configuration. ............................................................................ 80

Fig. 3.16 Equivalent circuit model of a coupled transmission line pair. These sections are cascaded to

represent distributed nature of transmission line. .................................................................. 81

Fig. 3.17 Measured and simulated s-parameters ((a) S11, and (b) S12) for 0.15µm wide, 0.30 µm

thick and 500 µm long coupled lines. The edge to edge line spacing of 0.15, 0.45 and 1.05

µm are represented by (1), (2) and (3) respectively. .............................................................. 82

Fig. 3.18 Measured and simulated far-end-noise for a 0.15 µm wide and 1000 µm long coupled lines.

The aggressor line input signal was a pulse with width of 5 nS, period of 10 nS, rise/fall

XIII

time of 80 pS and amplitude of 1 V. ...................................................................................... 84

Fig. 4.1 An image inductor with a complex distance D below the real inductor, and the arrows in the

metal traces represent the current direction. .......................................................................... 89

Fig. 4.2 Frequency-dependent eleven-element equivalent-circuit model of on-chip spiral inductors. 94

Fig. 4.3 Quality factors for the fabricated inductors and the model with a die photograph of a 4.5-turn

inductor fabricated in 0.18um CMOS technology. ................................................................ 96

Fig. 4.4 Simulated results compared with the measurement data. The thickness and conductivity of

the silicon substrate is 500um and 10S/m, respectively. ........................................................ 97

Fig. 4.5 Inductances of the inductors on silicon substrates with different conductivities as a function

of frequency. .......................................................................................................................... 99

Fig. 4.6 The mutual inductance between the real and image inductors, with the substrate

conductivity of 10,000 S/m. The spiral inductors have turns from 1.5-turn to 5.5-turn. ....... 99

Fig. 4.7 The substrate resistances due to eddy currents of a group of inductors ( =σ 10 S/m). ...... 100

Fig. 4.8 The substrate resistance due to eddy currents with different substrate conductivities for n=

2.5 and 5.5, respectively....................................................................................................... 100

Fig. 4.9 (a) The inductances of an inductor with n = 3.5 at different temperatures, and (b) the

substrate resistance due to eddy currents for inductors of n= 2.5 and 3.5-turn, respectively,

and with σ=10 S/m at 300 K. ............................................................................................... 101

Fig. 4.10 (a) The inductances, (b) the substrate resistance due to eddy currents, and (c) the mutual

inductances between the inductor and substrate eddy currents for a 3.5-turn inductor as a

function of temperature at different frequencies, with 10, 000 /S mσ = at 300K. ............ 103

Fig. 4.11 Layout of an 8-turn symmetric inductor. ............................................................................ 103

Fig. 4.12 Simulated inductances of an 8-turn differential inductor. ................................................... 104

Fig. 4.13 The substrate resistance due to eddy currents of an 8-turn differential inductor with

different substrate conductivities. ........................................................................................ 105

Fig. 4.14 Lumped physical model of a vertical tapered solenoidal inductor and its simplified circuit

model. .................................................................................................................................. 106

XIV

Fig. 4.15 The 3-D view, and (b) the top-view of a 3-turn vertical tapered solenoidal inductor. Blue,

yellow and green lines represent for M6, M5 and M4 layers, respectively. The oxide layers,

silicon substrate and test pads are not included. .................................................................. 108

Fig. 4.16 Q-factors of a 2.2 nH traditional inductor and a 2.1 nH VTS inductor against frequency .. 109

Fig. 4.17 Q-factors of 3-turn VTS inductors without the floating shielding, with the horseshoe

patterned shielding and with the ladder shielding against frequency .................................. 110

Fig. 4.18 Q-factors of a 3-turn and a 4-turn VTS inductor under different temperatures against

frequency ............................................................................................................................. 111

Fig. 5.1 Top and cross-sectional views of on-chip interleaved (Design 1) and center-tapped

interleaved (Design 2) PGS transformers ( 1t = 2 µm, 2t =0.54 µm, 1D = 0.9 µm, H = 6.7 µm,

and siD = 500 µm). ............................................................................................................. 116

Fig. 5.2 The small-signal circuit models for interleaved non-PGS transformer (Design 1) .............. 119

Fig. 5.3 The small-signal circuit models for an interleaved PGS transformer (Design 1) ................. 121

Fig. 5.4 The equivalent circuit model for a center-tapped interleaved non-PGS transformer (Design

2). ......................................................................................................................................... 123

Fig. 5.5 The series resistances of the primary and secondary coils versus frequency for N = 4 of

transformers of Design 1 and Design 2, respectively. ......................................................... 126

Fig. 5.6 Series inductances of the primary and secondary coils versus frequency for a transformer of

N = 4. ................................................................................................................................... 127

Fig. 5.7 Comparison of the extracted and simulated Z-parameters. .................................................. 131

Fig. 5.8 Extracted rκ and mκ for transformer (Design 1) of N=4. ............................................... 132

Fig. 5.9 The maxG values of transformer (Design 1) with and without a PGS versus frequency at

different temperatures, respectively. .................................................................................... 134

Fig. 5.10 The maxG values of PGS and non-PGS transformers (Design 2) versus frequency at different

temperatures, respectively. ................................................................................................... 135

XV

Fig. 5.11 The minNF of a (non) PGS transformers of Design 1 versus frequency at different

temperatures ......................................................................................................................... 136

Fig. 5.12 The 1Q -factors of the primary coil of a (non) PGS transformer of Design 1 versus

frequency at different temperatures ..................................................................................... 138

Fig. 5.13 The 1Q -factors of (non) PGS transformers of Designs 2 versus frequency at different

temperatures. ........................................................................................................................ 138

Fig. 5.14 Power losses versus frequency for (non)PGS transformer of Design 1 at different

temperatures ......................................................................................................................... 139

Fig. 5.15 Power loss versus frequency for (non)PGS transformers of Design 2 at different

temperatures ......................................................................................................................... 139

Chapter 1 Introduction

1

Chapter 1. Introduction

On-chip interconnects, inductors and transformers are widely used in advanced high-speed

digital, mixed-signal and radio frequency (RF) integrated circuits (ICs). Therefore, a thorough

understanding of their characteristics becomes a necessity for successful designs. In this thesis,

modeling and simulation efforts are devoted to exploring the characteristics of on-chip

interconnects, inductors and transformers.

1.1 On-Chip Interconnects

1.1.1 Background

In the past four decades, the semiconductor industry has advanced at an incredible rate in

both productivity and performance. The size of transistors and the switching delay have been

continuously reduced. Transistor channel lengths have steadily decreased from 2.0 μm in

1980 to 0.35 μm in 1995. Presently, processes with channel lengths as small as 20 nm are in

development [1]. These benefits make it possible for a particular function to be implemented

using less silicon area and with faster response. Thus, the number of transistors on each chip

is increasing [2], as shown in Fig. 1.1.


2

Fig. 1.1 Moore’s law predicts the doubling of transistor count every two years. Here is an example [2],

the transistor count for Intel microprocessors as a function of the years.

In other words, their density is also increasing. As a consequence, multilevel interconnect

networks are needed to connect those millions of transistors to distribute clock and other

signals and to provide power/ground to the various circuits/systems on a chip. The

fundamental development requirement for interconnects is to meet the high-speed

transmission needs of chips, despite further down-scaling of feature sizes. The speed of an

electrical signal in an IC is dominated by both the switching delay of the transistor and the

interconnect delay. However, scaling of interconnects increases their latency, especially for

global interconnects. Since the length of local and intermediate interconnects usually shrinks

with traditional scaling, the impact of their delay on performance is minor. Global

interconnects, which have the greatest wire lengths, will impact the delay most significantly.

Calculations using the existing roadmap values in the International Technology Roadmap

Years


3

for Semiconductors 2005 (ITRS) for technology generations from 180 nm down to 15 nm

show that the delay of scaled interconnect increases by approximately 10 ps while the delay

of fixed length interconnects increases by approximately 2000 ps. To improve the

performance of global interconnects, new technologies such as copper and low-k dielectric

materials have been introduced, reducing the interconnect resistance and capacitance. Copper

metallization provides lower resistance than similarly sized aluminum interconnects. New

dielectrics, such as Fluorinated Silica Glass (FSG) and Black Diamond, have low permittivity,

approaching 3.0, which can provide lower capacitance for the interconnects [1].

1.1.2 Motivation

As shown in Fig. 1.2, ITRS 2005 has illustrated the growing problem of global

interconnect delay [1]. Interconnect delay becomes dominant, whereas the transistor

switching speed no longer limits circuit performance. Due to the growing importance of

interconnect delay, circuit designers have been putting increasing efforts on interconnect

modeling, analysis and design.

In order to accurately model on-chip interconnects, we must thoroughly understand their

loss mechanisms. With an increase in operation frequency, the length of global interconnects

can become comparable to a wavelength. Therefore, a simple RC model is no longer valid to

model global interconnects [3, 4]. Instead, critical long interconnects, such as data buses and

clock trees, have to be treated as transmission lines. This means that global interconnects will

be characterized and modeled by distributed resistance, inductance, capacitance and

conductance [5-7].

At high frequencies, currents in an interconnect are pushed to the surface of the


4

interconnect due to the finite metal conductivity, a phenomenon known as the skin effect.

Additionally, magnetic fields generated by other interconnects in the vicinity will cause the

current in the interconnect to distribute non-uniformly, which is called the proximity effect.

Both the skin and proximity effects increase the resistance of an interconnect with increasing

frequency [8]. Furthermore, magnetic fields can induce eddy currents in the silicon substrate

because of its conductive nature. Substrate eddy currents may cause significant ohmic losses

at high frequencies. This phenomenon is known as the substrate skin effect [9, 10].

Fig. 1.2 International Technology Roadmap for Semiconductors 2005 predictions for device and interconnect delays [1].

The substrate skin effect causes not only an increase in the resistance, but also a decrease

in the inductance of an interconnect, because substrate eddy currents partially cancel the

magnetic field generated by the interconnect [9]. Additionally, as the return current of a signal

always follows the path with the smallest impedance, and the reactance (ωL) dominates the

impedance of an interconnect at high frequencies, the current may flow back through the


5

nearest ground paths or even other signal lines in complicated interconnect networks [8]. As a

result, the inductance may further decrease.

The aforementioned distributed parameters can be extracted by the Partial Elements

Equivalent Circuits (PEEC) method [11] or full wave numerical methods such as Methods of

Moments (MoM) [12], Finite Element Method (FEM) [13, 14] and Finite-Difference

Time-Domain method (FDTD) [15, 16]. Though these methods can provide accurate results,

they normally result in a severe computational burden, especially in chip level simulations.

As an alternative, the loop-based method offers designers another valuable avenue for

modeling on-chip interconnects due to its simplicity [8]. Without degrading the accuracy of

the results, this method speeds up the simulation significantly by avoiding discretization of all

the conductors in the problem space – a major reason causing the computational inefficiency

of PEEC and full-wave numerical techniques. The challenge of the loop based method is the

difficulty in determining the current return paths. However, gridded co-planar ground/power

distributions are widely adopted in most high-speed digital chips. So global interconnects,

such as signal wires in clock networks, are usually optimized to have VDD/GND shields to

provide closely located return paths [8, 17, 18]. Hence, the loop based method may be a good

choice to model on-chip global interconnects.

In order to model the substrate skin effect, the silicon substrate is generally treated as a

low conductive medium that is characterized by its conductivity and permittivity. By using

numerical approaches such as PEEC and full-wave methods, the silicon substrate has to be

meshed to obtain accurate results, at the cost of computational efficiency. For the sake of

simplicity, the complex image method (CIM) may be adopted. The CIM was introduced by

Wait and Spies in [19] to calculate the electric field generated by a line-current above a


6

ground. The CIM technique replaces a conducting substrate of finite thickness by an image

current which has a complex distance from the real conductor for evaluation of the electrical

field. Over the past forty years, the CIM technique has been successfully implemented to

obtain solutions to the eddy current effects in the conductive earth surface [20] and to model

the substrate skin effect for on-chip interconnects [9, 21]. The simplicity and robustness of

CIM technique has made it possible to calculate the total electrical and magnetic fields about

a conductive surface, without using complicated mathematics.

Obviously, an interconnect model with frequency dependent distributed parameters is not

compatible with SPICE-based circuit simulators, and is not suitable for simulation in the

time-domain. Therefore, an equivalent circuit model, consisting of a ladder network with

frequency independent elements, may be used to approximate frequency dependent

characteristics.

1.2 On-Chip Inductors and Transformers

1.2.1 Background

RF transceivers fabricated by CMOS technology are widely used in cellular phones and

wireless local area network (WLAN) devices to meet the low cost requirements of the fast

growing wireless communication market. Thanks to the development of low cost handsets,

cellular telephones have enjoyed enormous growth over the past decade. For example, the

number of GSM mobile phone subscribers worldwide has risen from 1 million in 1993 to 2.2

billion in 2006 [22], as shown in Fig. 1.3. New standards, such as the General Packet Radio

Service (GPRS), the Universal Mobile Telecommunications Systems (UMTS), and the Time


7

Division-Synchronous Code Division Multiple Access (TD-SCDMA), have been set-up to

allow additional attractive entertainment functionality through data services, such as internet

access and live video streaming. Thus, the total number of worldwide cellular phone users is

estimated to increase to 4.3 billion in 2011.

Fig. 1.3 Worldwide GSM customers from 1993 to 2006 [22].

This dramatically increased cell phone market benefits from the technological advances in

CMOS processes. Deep submicron transistors, due to the constantly shrinking feature size of

CMOS technologies as mentioned in the previous section, allow the integration of the analog

and digital blocks to form mixed-signal ICs for “system-on-chip” solutions. Fully integrated

chip solutions are desired to eliminate off-chip components and to reduce cost. The number of

board-level passive components and ICs drops with increased integration, which reduces the

overall costs of assembly and parts. Decrease in the number of passive components on board


8

leads to smaller board sizes and usually lower power consumption, since there is no need to

drive off-chip low impedance components. Furthermore, on-chip passive components have

the advantage of well controlled interconnecting parasitics over process variation, which

enhances the reliability and the controllability of the end products. Therefore, on-chip passive

components, such as resistors, capacitors, inductors and transformers, are widely used in

RFICs. On-chip inductors and transformers are widely applied for impedance matching, RF

filters, voltage controlled oscillators (VCO), power amplifiers (PA) and low noise amplifiers

(LNA).

In the past, on-chip passive components were integrated during front end processing,

where doped monocrystalline Si substrate, polycrystalline Si and Si-oxides or Si-oxynitrides

were used. Due to their vicinity to the Si substrate, those passive devices had poor

performance, especially when used at high frequencies. Therefore, low loss, low parasitic,

high quality passive components in the interconnect levels are highly demanded [1].

1.2.2 Motivation

Today, on-chip spiral inductors in the upper thick Al- or Cu-metallization levels are used

to fabricate low resistivity coils. They have sufficient spacing from the silicon substrate to

achieve optimized quality factors. Since these spiral inductors are fabricated using the

standard interconnect process, they suffer similar losses as on-chip interconnects. In addition

to the Ohmic loss, due to the resistance of inductors at low frequencies, the skin and

proximity effects cause non-uniform current distribution and increase the resistance and loss

at high frequencies. Current crowding effects are also known to occur in corners and bends of

inductors at high frequencies. Furthermore, both the electrical field penetrating into the


9

silicon substrate through the oxide capacitance, and the substrate eddy currents induced by

the magnetic field, cause substrate loss at high frequencies due to the conductive silicon.

As a result, on-chip inductors typically exhibit the lowest Q-factor of the RF passives. In

addition, the high operating frequencies, at which deep sub-micron and nano-scale CMOS

devices are able to operate, have made RFICs prone to the quality of the passive components

[23]. Therefore, accurate models of on-chip inductors are highly desired for first-time-right

designs.

A conventional transformer is a magnetically coupled system of inductors. On-chip

transformers have been widely used in designs for on-chip impedance matching, baluns, and

low-noise amplifier feedback. In addition to the losses caused by similar mechanisms as

inductors, on-chip transformers also suffer from losses due to lateral conduction currents

flowing in the substrate between the primary and secondary coils. Such losses, together with

those from shunt conduction current flowing in the substrate, are caused by the time-varying

electric field at high frequencies. In order to reduce such losses, one potential approach is to

employ an appropriate patterned ground shield (PGS), which may stop the electric field

leaking into the substrate [24].

1.3 Thesis Organization

Chapter 2 presents a fully scalable and SPICE compatible wideband model of on-chip

interconnects. This model also has the capability to estimate the impact of dummy metal fills.

The model is validated by a 3D quasi-static field solver, a full-wave electromagnetic field

simulator and measurements. The simulated S-parameters of the model agree well with the

measured S-parameters of on-chip test interconnects with different widths and lengths over a


10

wide frequency range from DC up to 110 GHz.

Chapter 3 discusses the electromagnetic-thermal characteristics of on-chip coupled

asymmetrical and symmetrical interconnects based on several extended formulas to

determine all frequency- and temperature-dependent distributed parameters. These

characteristics include wideband series impedances and shunt conductances, conductive and

dielectric attenuation constants of even (c) and odd (π)- modes, pulse waveform distortion

and crosstalk, and average power handling capability (APHC). The proposed model for

on-chip coupled interconnects is validated by experimental results.

Chapter 4 provides a frequency-dependent eleven-element equivalent circuit model. The

complex image method is applied to analyze the frequency and temperature dependencies of

substrate eddy currents for inductors on a lossy silicon substrate. The validity of the model is

established by comparing the simulated and measured results.

Chapter 5 investigates the performance of on-chip CMOS transformers with and without

patterned ground shields at different temperatures. These transformers are designed to have

either interleaved or center-tapped interleaved geometries, but with the same inner

dimensions and metal track spacings. All performance parameters of these transformers, such

as frequency- and temperature-dependent maximum available gain, minimum noise figure,

quality factor of the primary or secondary coil, and power loss are characterized and

compared with two-port S-parameters measured at different temperatures.

Chapter 6 concludes this dissertation. Future work is also proposed.

1.4 Original Contributions

The original contributions of this thesis are presented as follows:


11

• A DC-to-110 GHz wideband scalable and SPICE-compatible model for on-chip

interconnects was developed in Chapter 2. All the elements in this model can be

calculated by with an analytic technique and closed-form formulas. This analytic

technique is based on the modified effective loop inductance approach and the

complex image method. Both the closed-form formulas and the analytic technique

only need geometry and process parameters of the interconnects to calculate the

model elements. Therefore, the scalability of the model has been ensured. At the

same time, all elements in the model are frequency-independent. Thus, this model

is compatible with SPICE-based circuit simulators. The accuracy of this model

has been validated from DC up to 110 GHz in terms of S-parameters by both a

full-wave EM field solver and measured results. To the best knowledge of the

author, this model is the first scalable and SPICE-compatible model for on-chip

interconnects with high accuracy from DC up to 110 GHz. This interconnect

model is not only useful for digital circuits designs, but is also applicable to

CMOS RF and microwave circuits designs.

• On-chip coupled (a)symmetrical interconnects were characterized in Chapter 3.

The electromagnetic-thermal characteristics of these interconnects were

investigated in detail. This included the determination of wideband series

impedances and shunt conductances, conductive and dielectric attenuation

constants of even (c) and odd (π) modes, pulse waveform distortion and crosstalk,

and average power handling capability (APHC). Compared with previous studies

of coupled symmetrical interconnects, the present work has focused on (i)


12

asymmetrical coupled configurations; (ii) both electromagnetic and thermal

characteristics; and (iii) all geometric and physical parameters of the configuration,

particularly metal line thickness, line conductivity, silicon conductivity and

thermal conductivity. Based on the numerical examples, effective ways to

suppress silicon substrate loss and coupling effects, reduce crosstalk between two

interconnects, and enhance their power handling capability have been found. All

these issues are of great importance in implementing coupled symmetrical and

asymmetrical interconnects in high-speed digital and high-frequency RF circuits.

Then, based on the detailed investigation of coupled interconnects, an equivalent

circuit model was developed. To validate the proposed model, a group of on-chip

coupled interconnects was fabricated and measured in both the frequency domain

and the time domain. A good agreement between the measured and modeled

response over a wide frequency band up to 40 GHz was obtained. The model

closely reproduces the cross-talk waveforms between coupled lines for different

lengths, widths and line spacing.

• A scalable frequency-dependent eleven-element equivalent circuit model for

on-chip inductors was established in Chapter 4. Compared to the conventional

π-network model of inductors, an RL loop is added through a mutual inductive

coupling link in the proposed model. This loop is used to model the substrate eddy

currents. For the sake of simplicity, the complex image method (CIM)

incorporating the Greenhouse approach has been applied to characterize the

substrate skin effect. This technique avoids meshing the conducting silicon


13

substrate and provides a set of closed-form formulas for calculating the resistance

and inductance of the added RL loop caused by the substrate eddy currents. Further,

this technique can analyze the variation of the substrate eddy currents with

temperature. Other elements in the model can also be simply obtained by

closed-form formulas. To validate this model, a set of on-chip inductors was

fabricated. The accuracy and scalability of this model has been demonstrated by

good agreement between simulated and measured results.

• A vertical tapered solenoid inductor was designed in Chapter 4. The outer-most

turn of this inductor is fabricated on the top metal layer, while the innermost turn is

fabricated on the bottom metal layer. Each metal layer has only one turn, with the

diameter decreasing on each lower layer. This vertical tapered solenoid structure

can significantly reduce the inter-wire capacitance as well as the underpass

capacitance. This reduction in the parasitic capacitance of the inductor can

increase its self-resonance frequency (fsr). As compared with a traditional planar

inductor, this novel inductor was shown to increase fsr from 21.3 GHz to far

beyond 25 GHz, and the frequency of the peak quality factor (fQmax) by 160% from

4.05 GHz to 10.55 GHz. The self-shielding characteristic of this inductor can

eliminate the requirement of including floating shields underneath the inductor.

Due to its high fQmax and fsr, the vertical tapered solenoid inductor can be used at

multi-tens of Gigahertz or in broadband RF applications.

• Frequency-thermal characterization of on-chip transformers with and without


14

patterned ground shields (PGS) was carried out in chapter 5. These transformers

were fabricated using a 0.18 μm RF CMOS process and were designed to have

either interleaved or center-tapped interleaved geometries. The measured results

demonstrate that there exist significant differences in the performance parameters

between interleaved and center-tapped interleaved configurations. Firstly, the

maximum available gain maxG and 1Q -factor usually decrease with temperature,

however, temperature effects on both maxG and 1Q -factor may be reversed

beyond a certain frequency. Secondly, with the same geometric parameters,

interleaved transformers exhibit better low-frequency performance than

center-tapped interleaved transformers, whereas the center-tapped configurations

possess lower values of minNF at higher frequencies. Thirdly, with rising

temperature, the degradation in performance of the interleaved transformers can

be effectively compensated by implementing a PGS, while for center-tapped

transformer, the performance improvement offered by PGS is small.

1.5 Publication List

• Journal publications

[1] K. Kang, L.-W. Li, and W.-Y. Yin, “Distortion of a square pulse wave with finite rise

time in edge-coupled microstrip lines on LTCC substrate,” Microwave and Optical

Technology Letters, vol. 42, no. 1, pp. 8-13, July 5, 2004.

[2] K. Kang, T.-S. Yeo, J. Shi and B. Wu, “ Experimental characterization of on-chip

single and double-coupling spiral inductors” International Journal of Infrared and

Millimeter Waves, vol. 25, no. 10, pp. 1535-1544, Oct. 2004.


15

[3] J. Shi, K. Kang, T.-S. Yeo and B. Wu, “Temperature effects of the performance of

on-chip spiral inductors used in RF(MM)ICs” International Journal of Infrared and

Millimeter Waves, vol. 25, no. 10, pp. 1511-1522, Oct. 2004.

[4] J. Shi, W. Y. Yin, K. Kang and L. W. Li, “Frequency-thermal characterization of

on-chip transformers with patterned ground shields” , IEEE Trans. Microwave Theory

and Techniques, vol. 55, no. 1, pp. 1-12, Jan. 2007.

[5] K. Kang, J. Shi, W.-Y. Yin, L.-W. Li, S. Zouhdi, S. C. Rustagi, K. Mouthaan,

“Analysis of frequency and temperature dependent substrate eddy currents in on-chip

spiral inductors using complex image method (CIM)”, IEEE Trans. Magnetics, vol.

43, no. 7, pp. 3243-3253, Jul. 2007.

[6] K. Kang, J. Shi, S.C. Rustagi, L.-W. Li, K. Mouthaan, W.-Y. Yin and S. Zouhdi,

“On-chip vertical tapered solenoid inductor with high self-resonance frequency”, IEE

Electronics Letters, vol. 43, no. 16, pp. 867-869, Aug. 2007.

[7] W. Y. Yin, K. Kang, J. F. Mao, “Electromagnetic-thermal characterization of on-chip

coupled (a)symmetrical interconnects”, IEEE Trans. Advanced Packaging, vol. 30, no.

4, pp. 851-863, Nov. 2007.

[8] R. Kumar, K. Kang, S. C. Rustagi, K. Mouthaan and T. K. S. Wong, “SPICE

compatible modeling of on-chip coupled interconnects”, IEE Electronics Letters, vol.

43, no. 23, Nov. 2007.

[9] S. Sun, J. Shi, L. Zhu, S. C. Rustagi, K. Kang, and K. Mouthaan, “40 GHz compact

TFMS meander-line bandpass filter on silicon substrate”, IEE Electronics Letters, vol.

43, pp. 1433-1434, Dec. 6th , 2007

[10] Q. Hua, W. Y. Yin, L. Zhou, J. F. Mao, K. Kang, and L. Zhu, “Improved circuit


16

model for coplanar-waveguide microstrip-line transition on silicon substrate,”

Microwave Opt. Tech. Lett., vol. 50, pp. 141-144, Jan. 2008.

[11] W.-Y. Yin, J.-Y. Xie, K. Kang, J. Shi, J.-F. Mao, and X.-W. Sun, “Vertical topologies

of miniature multi-spiral stacked inductors”, IEEE Trans. Microwave Theory and

Techniques, vol.56, no. 2, pp. 475~486, Feb. 2008.

[12] K. Kang, L. Nan, S. C. Rustagi, K. Mouthaan, J. Shi, R. Kumar, W.-Y. Yin, and L.-W.

Li, “A wideband scalable and SPICE-compatible model for on-chip interconnects up

to 110 GHz”, IEEE Trans. Microwave Theory and Techniques, vol. 56, no. 4, pp.

942~951, April 2008

• Conference publications:

[13] K. Kang, J. Shi, W.-Y. Yin, L.-W. Li, and T.-S. Yeo, “Experimental and theoretical

characterizations of finite-ground coplanar waveguides with discontinuities” in Proc.

2004 Progress In Electromagnetics Research Symposium, Nanjing, China, August

28-31, 2004, p. 404

[14] K. Kang, L.-W. Li, W.-Y. Yin, B. Wu, S.C. Hui, and L. Guo, “Effects of

frequency-dependent coupling between on-chip two neighboring spiral inductors” in

Proc. 2004 Progress In Electromagnetics Research Symposium, Nanjing, China,

August 28-31, 2004, p. 405

[15] K. Kang, W.-Y. Yin, and L.-W. Li, “Transfer functions of on-chip global

interconnects based on distributed RLCG interconnects model”, in Proc. of 2005

IEEE AP-S International Symposium and USNC/URSI National Radio Science

Meeting, Washington DC, USA, July 3-8, 2005


17

[16] K. Kang, W.-Y. Yin, and L.-W. Li, “Transfer Functions of on-Chip Global

Interconnects Based on Distributed RLCG Model”, in Proc. of 2005 Progress In

Electromagnetics Research Symposium, HongZhou, China, August 22-26, 2005

[17] K. Kang, J. L. Shi, L. W. Li , S. C. Rustagi , K. Mouthaan, W. Y. Yin and S. Zouhdi,

"Vertical Tapered Solenoidal Inductor with Zero Spacing," IEEE MTT-S,

International Microwave Symposium IMS 2006, June 11-16, 2006, San Francisco,

USA.

[18] K. Kang, L.-W. Li, S. Zouhdi, J. Shi and W.-Y. Yin, “Electromagnetic-thermal

analysis for inductances and eddy current losses of on-chip spiral inductors on lossy

silicon substrate”, in EuMIC 2006, Sep. 10-15, Manchester, UK

[19] K. Kang, L. Nan, S. C. Rustagi , K. Mouthaan, J. L. Shi, R. Kumar and L.-W. Li, “A

wideband scalable and spice-compatible model for on-chip interconnects up to 80

GHz”, IEEE RFIC Symposium, June 3-5, 2007, Honolulu, Hawaii.

[20] R. Kumar, S.C. Rustagi, K. Kang, K. Mouthaan and T.K.S. Wong, “Characterization

and Modeling of CMOS on-chip coupled interconnects”, ESSDERC, Munich,

Sep.11-13, 2007.

Chapter 2 Modeling of On-Chip Single Interconnect

18

Chapter 2. Modeling of On-Chip Single Interconnect

A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to

110 GHz is presented in this chapter. The series branches of the proposed multi-segment model

consist of an RL ladder network to capture the skin and proximity effects as well as the substrate

skin effect. Their values are obtained from a technique based on a modified effective loop

inductance approach and complex image method. A CG network is used in the shunt branches

of the model, which accounts for capacitive coupling through the oxide and substrate losses due

to the electrical field as well as the impact of dummy metal fills. The values of these elements

are determined by analytical and semi-empirical formulas. The model is validated by a 3D

quasi-static field solver, full-wave EM simulator and measurements. The simulated

S-parameters of the model agree well with the measured S-parameters of on-chip interconnects

with different widths and lengths over a wide frequency range from DC up to 110 GHz.

2.1 Introduction

Recently, silicon technology has entered the realm of millimeter-wave frequencies and


19

several silicon-based systems have been reported that operate at these frequencies [25-27]. In

these applications, on-chip interconnects are widely used in matching networks [25-27] and

connections between multiple elements in an integrated phased array [27]. Thus, a wideband

and accurate model for on-chip interconnects becomes a necessity, especially in circuit

designs at mm-wave frequencies. However, there is no report so far on accurate interconnect

models valid up to high frequencies in the vicinity of 100 GHz.

On the other hand, due to the high frequencies of operation of today’s high-speed digital

integrated circuits, global interconnects such as clock trees and data buses can not be treated

as a lumped element or characterized by a simple RC model any more since their lengths can

be comparable to the signal wave-lengths [3, 4, 28]. Additionally, the resistance of

interconnects increases significantly at high frequencies due to both skin- and proximity

effects, whereas the inductance of interconnects decreases with frequency [8]. At the same

time, on-chip interconnects also suffer from serious substrate losses caused by the penetration

of the electrical field in the lossy silicon substrate through the capacitive coupling and eddy

currents induced by the time-varying magnetic field. These frequency-dependent behaviors

of on-chip interconnects can be characterized by the Telegrapher’s equations [5] and the

partial element equivalent circuit (PEEC) analysis [11]. However, these methods are difficult

to directly apply in SPICE-like circuit simulators. Recently, an RL ladder network comprising

frequency independent R and L elements was used to model the skin effect [29], and this

method was extended to characterize proximity effects based on an effective loop inductance

approach [8, 30]. However, the substrate losses due to the capacitive coupling and the

substrate skin effect are not considered in these models. Further, to meet metal density rules,

high amounts of dummy metal fills are usually required by today’s advanced IC technologies


20

[31, 32]. Thus, the interconnect model should also have the capability of incorporating the

impact of these dummy metal fills.

The objective of this chapter is to establish an equivalent circuit model for on-chip

interconnects to rigorously characterize its frequency dependent behavior due to skin and

proximity effects as well as substrate eddy currents and the impact of dummy metal fills over

a wide frequency range from DC up to 110 GHz. All the lumped elements in the model are

frequency independent and their values are directly obtained from structural and geometrical

parameters. This ensures proper scalability of the model parameters because no optimization,

tuning or fitting for these parameters is involved. The values of the lumped elements in the

series branch of the model are calculated by using a technique based on the modified effective

loop inductance model and the complex image method, while those in the shunt branch are

given by analytical and semi-empirical equations.

2.2 A Wideband Scalable and SPICE-Compatible Model

In order to accurately model on-chip interconnects, we first develop a technique for

characterizing the frequency dependent resistance due to the skin effect for a single line. This

technique is then extended to model the proximity effect and substrate skin effect of an

interconnect surrounded by several parallel ground lines, by incorporating the modified

effective inductance loop model and complex image method. Thirdly, other lumped elements

are obtained by analytical equations or semi-empirical formulas, followed by an approach to

estimate the impact of dummy metal fills. Based on the above results, a set of empirical

formulas by using a multiple regression technique is provided for IC designers to quickly

calculate lumped elements in the proposed model.


21

2.2.1 Skin Effect

The resistance of an interconnect can be approximately obtained by the sum of DC and

AC resistances [33],

0( ) dc acTR f R R f f= + . (2.1)

The first term in (2.1) is the DC resistance and given by ( )dcR l w tσ= ⋅ ⋅ , where l, σ, w,

and t denote length, conductivity, width and thickness of the interconnect, respectively. RacT

in the second term of (2.1) is the AC resistance at f0. The total AC resistance is proportional

to f due to the skin effect. The skin effect is a well-known physical phenomenon, which

results in vertically and laterally non-uniform current flows in a rectangular conductor. In

order to capture the laterally non-uniform current distribution in an interconnect at high

frequencies, its cross-section is divided into six segments, as shown in Fig. 2.1(a). In each

segment, only the vertical non-uniform current distribution exists [34]. Due to symmetry, a

PEEC-like formulation is established in (2.2), where the self inductances Lii and the mutual

inductances Mij are obtained as in [35]

11 11 16 12 15 13 14 1

21 26 22 22 25 23 24 2

31 36 32 35 33 33 34 3

( ) ( ) ( )( ) ( ) ( )( ) ( ) ( )

ac

ac

ac

V R j L M j M M j M M IV j M M R j L M j M M IV j M M j M M R j L M I

ω ω ωω ω ωω ω ω

+ + + +⎛ ⎞ ⎛ ⎞ ⎛ ⎞⎜ ⎟ ⎜ ⎟ ⎜ ⎟= + + + + ⋅⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟ ⎜ ⎟+ + + +⎝ ⎠ ⎝ ⎠ ⎝ ⎠

.

(2.2)

The increase in ac resistance at f0 caused by vertical current non-uniformity is

approximately given by

0, 0.5ac ii

i

flRw

π μσ

⋅ ⋅= (2.3)


22

(a)

1 10 1000

2

4

6 Model

Symbols: Q3D

Res

ista

nce

(Ω)

Frequency (GHz)

W(μm) t(μm) max error 15 1 7.4% 30 1 10% 40 1 9.6% 10 2 7.5% 15 2 0.4% 30 2 4.4% 40 2 3.4% 50 2 1.1% 60 2 2.3%

(b)

Fig. 2.1 (a) The cross-section of an interconnect is divided into six segments to capture the laterally non-uniform current distribution. (b) The frequency dependent resistance of the interconnect calculated by our method is compared with simulation results by using Q3D extractor. The length of the interconnect is 1000 μm and σ=5.8×107 S/m.

where i=1,2, and 3, wi is the width of i-th section, μ denotes the permeability of the

interconnect, and f0 is fixed to 1 GHz in our study. Thus, the total AC resistance is given by

1 2 32( )acTVR Re

I I I⎡ ⎤

= ⎢ ⎥+ +⎣ ⎦. (2.4)

The RacT values obtained in this way are validated up to 100 GHz with the help of Q3D

extractor as shown in Fig. 2.1. Q3D extractor is a 3D/2D quasi-static electromagnetic-filed

simulator, which utilizes the Method of Moments (MOM) and the Finite Element Method

(FEM) to compute RLCG parameters of a structure [33]. We observe that the maximum


23

error of the model is less than 10% over a wide range of W (4<W/t<40). For W/t<4, this

method overestimates the effect of lateral non-uniformity in the current distribution.

2.2.2 Proximity and Substrate Skin Effects

In high-speed digital ICs, the structure of multi-level interconnects is usually very

complex. A signal interconnect invariably runs parallel to other signal lines and

power/ground lines on the same metal layer, and with orthogonal lines on the neighboring

upper and lower metal layers. Therefore, the mutual inductive coupling induced by

neighboring wires must be considered. To accurately extract inductance effects, the most

commonly used and well-developed technique is the partial element equivalent circuit (PEEC)

analysis, which is based on the concept of partial inductance [36]. However, the PEEC

method offers accurate results at the cost of computational efficiency and simplicity, because

it always leads to a dense inductance matrix even with recent efforts in sparse approximation

of the inductance matrix [37] and its inverse [38]. The loop inductance approach, recently

reported, circumvents this difficulty to a large extent and is widely adopted [8, 17, 18, 30].

The major challenge of this technique is the difficulty in determining current return paths in a

real chip environment. However, most VLSI chips use a gridded co-planar power distribution

[8] and signal wires in the clock networks are usually optimized to have VDD/GND shields to

provide closely located return paths [17, 18]. In these well-designed structures, the loop

inductance approach may be preferred for a fast estimation of the inductance. Hence, this

technique is adopted here to extract the inductance as well as the resistance of interconnects

fast and accurately.


24

Fig. 2.2 A single interconnect parallel with N ground lines

Without loss of generality, we consider a signal line parallel to N ground lines as shown in

Fig. 2.2 for application of the loop inductance approach. By choosing a source voltage of

unity, the return currents in N ground lines in Fig. 2.2 can be calculated as

( 1) ( 1) ( 1) ( 1) 1 1[ ] [ ] [ ] [ ] [1]TN N N N N N g N NM Z M I× + + × + + × × ×⋅ ⋅ ⋅ = (2.5)

where ( 1)[ ] N NM + × is the mesh matrix [39], ( 1) ( 1)[ ] N NZ + × + denotes the impedance matrix, and

1[ ]g NI × represents the return currents in the ground lines. Elements in the impedance matrix

are determined by

( ) ( ),( )

( ),ii ii

ijij

R f j L f i jZ f

j M f i jω

ω+ =⎧

= ⎨ ≠⎩ (2.6)

where i,j=1,…,N+1, Rii and Lii are the self resistance and inductance of the signal line or

ground lines, and Mij is the mutual inductance between the lines. 1[ ]g NI × can be normalized as

∑=

=N

igiggn III

1][][ (2.7)

The effective loop impedance is then given by

( )[ ] [ ] [ ][ ] [ ]T Tloop gn gnZ I M Z M I= . (2.8)


25

If accurate results are sought from (2.8) over a wide frequency band, the whole structure

must be finely discretized and meshed. However, to circumvent this, we propose the use of an

asymptotic technique - at DC, the resistance dominates and the impedance matrix reduces to a

resistance matrix; whereas at extremely high frequencies, the inductance is dominant, the

impedance matrix can be simply substituted by the inductance matrix [8, 30]. Hence, the

resistance matrix [R] is used in (2.5) instead of the impedance matrix [Z] to calculate return

currents in ground lines at DC. Based on the calculated return currents, the effective loop DC

resistance Rloop,DC and effective loop DC inductance Lloop,DC are obtained by simply

substituting the resistance matrix [R] and the inductance matrix [L] for the impedance matrix

[Z] in (2.8), respectively. Similarly, the inductance matrix [L] instead of the impedance matrix

[Z] is used to calculate return currents at the extremely high frequency to obtain the Lloop,HF.

In order to obtain Rloop,HF, a method similar to that used to calculate the

frequency-dependent resistance for a single line in the previous section is adopted and (2.3) is

used to establish the impedance matrix. Thus, the effective loop resistance is given by

, , 0( )loop loop DC loop acTR f R R f f= + . (2.9)

where f0 = 1 GHz. In our study, Rloop,HF is obtained by Rloop,HF = Rloop(110 GHz) since the

highest frequency in the measurement is 110 GHz.

Thus, all these four parameters, i.e., Rloop,DC, Lloop,DC, Lloop,HF and Rloop,HF, are obtained

without meshing any interconnects. To validate our method, the effective loop resistance and

inductance for two sets of test structures are simulated by using the technique described in

this section and using the 3D quasi-static field solver Ansoft Q3D extractor [33], respectively.

The test structures consist of a signal interconnect with three parallel ground planes on each


26

side as shown in Fig. 2.3 (a). As shown in Fig. 2.3(b), a good agreement between our method

and Q3D extractor from DC up to 100 GHz is found.

(a)

1 10 10020

40

60

80

100

120

140

160

180

200

220

Rloop,HF=Rloop(f)@110GHz

Rloop,DC=Rloop(f)@DC

Case A Case B Model Q3D Model Q3DLloop,DC(nH) 9.72 9.81 8.54 8.65Lloop,HF(nH) 5.87 6.27 4.69 5.19

R

loop

(f) (Ω

)

Frequency (GHz)

ModelSymbols: Q3D

case A: w=4μm & t=1μm case B: w=8μm & t=1μm

(b)

Fig. 2.3 (a) An interconnect with six parallel ground lines. (b) The resistance and inductance of two such structures with different width are calculated by using our model and the Q3D extractor, respectively. In these cases, only skin and proximity effects are considered. Length =1 cm and σ=5×107 S/m.

2.2.3 Substrate Skin Effect and Complex Image Method

Because of the low resistivity of the silicon used in today’s CMOS technologies, substrate

eddy currents can be induced by the time-varying magnetic field generated by interconnects

at high frequencies. These currents will increase the total loss of interconnects. Traditionally,

silicon substrate can be treated as the conducting medium and be discretized to calculate

substrate eddy currents by using PEEC or other full-wave approaches. In order to avoid the

heavy computational burden of discretization, the complex image method (CIM) is applied

here. As discussed in Chapter 1, the CIM technique provides us a simple approach for


27

modeling substrate skin effect without being involved in complex mathematical treatments.

The CIM technique will be introduced in detail in this section. In a homogeneous conductive

medium, such as a silicon substrate, the displacement current can be negligible as compared

with the conductive current at lower frequencies, and as a consequence the charge distribution

on the conductive surface of the material is absent [40]. Thus, the basic field equations [41]

are

E j Hωμ∇× = − , (2.10)

H J∇× = . (2.11)

where E , H , and J are electrical field, magnetic field strength and current density,

respectively. Invoking a Coulomb gauge, the field within the conductive medium can be

determined by the magnetic vector potential [42]:

E j Aω= − (2.12)

1H Aμ

= ∇× ; (2.13)

and the vector potential A satisfies

2 0A j Aωμσ∇ − = (2.14)

where μ and σ are permeability and conductivity of the silicon substrate respectively. Without

loss of generality, the filamental unit line current in the z-direction is assumed to be located on

the y-axis at the location of (0, hox), where hox denotes the oxide thickness, as shown in Fig.

2.4.


28

Fig. 2.4 A straight filament unit line current parallel to the lossy substrate with a finite thickness.

The line current is assumed to be:

0 ˆcos( )I I t zω= . (2.15)

The oxide layer and the silicon substrate are located below the current carrying filament.

The regions above the current filament and below the silicon substrate are free space. Under

a 2-D approximation, it is obvious that the magnetic vector potential has a nonzero

component only in the z-direction, and (2.14) can be simplified as

2 ( , ) ( , ) 0z zA x y j A x yωμσ∇ − = . (2.16)

The total field in Region I should be the sum of the fields generated by the current filament

and the distributed eddy currents induced inside the silicon substrate. In Region III, the field

arises only from the eddy currents. Hence, we have

2

1 0( , ) ( ) ( )z oxA x y x y hμ δ δ∇ = − (2.17)

22 2( , ) ( , )z zA x y j A x yωμσ∇ = (2.18)


29

2

3 ( , ) 0zA x y∇ = . (2.19)

Here δ(x) is the Dirac-delta function. The appropriate solutions to Eqs. (2.17)-(2.19) are

expressed by the Fourier integrals [40, 41] as follows:

01

1 20

( ) cos( ) ,( , )

( ) ( ) cos( ) , 0

my

zmy my

R m e mx dm y bA x y

Q m e Q m e mx dm y b

∞ −

∞ −

⎧ ≥⎪= ⎨⎪ ⎡ ⎤+ ≤⎣ ⎦⎩

∫∫ ≺

(2.20)

2 1 20( , ) ( ) ( ) cos( )qy qy

zA x y K m e K m e mx dm∞ −⎡ ⎤= +⎣ ⎦∫ (2.21)

3 0( , ) ( ) cos( )my

zA x y M m e mx dm∞

= ∫ (2.22)

where ( )R m , 1( )Q m , 2 ( )Q m , 1( )K m , 2 ( )K m and ( )M m are unknown spectral functions to be

determined, b= oxh , and q and m have the relationship

2 2 2

0q m jγ ωμ σ− = = . (2.23)

In Region I, the magnetic flux density, due to the filament, is determined by

0 01 2 2

ˆ2 ( )

I rBx y b

μπ

=+ −

(2.24)

where r is the unit vector from source point to the field point. The x- and y-components of

1B can be expressed by converging Fourier integrals [40] as follows:

0 01 0

cos( )2

b y mx

IB e mx dmμπ

∞ − −= ∫ (2.25)

0 01 0

sin( )2

b y my

IB e mx dmμπ

∞ − −= ∫ . (2.26)

For ( , )zx

A x yBy

∂=

∂and ( , )z

yA x yB

x∂

= −∂

, by comparing (2.20) with (2.25) and (2.26), (2.20)


30

can be expressed as

0 01 20

( , ) ( ) cos( )2

b y mmy

zI eA x y Q m e mx dm

mμ

π

− −∞ −⎡ ⎤

= +⎢ ⎥⎣ ⎦

∫ . (2.27)

The remaining undetermined spectral functions are derived by applying the boundary

conditions , 1,i x i xB B += and , 1,i y i yB B += at y= 0 and –t, where i = 1 and 2, respectively. After

the laborious process, the solutions are derived as

0 02

1

( )bmI eK m

Cμπ

−

= and ( ) qmemqmqC qt −+

−+

= 22

1 (2.28)

21 2( ) ( )qtq mK m e K m

q m+

=−

(2.29)

( ) ( )1 2( ) ( ) ( )m q t m q tM m K m e K m e− += + (2.30)

0 02 2 2

( )( )( )( )2 ( ) ( )

bm qt qt

qt qt

I e q m q m e eQ mm q m e q m e

μπ

− −

−

+ − −= −

+ − − (2.31)

where 2 ( )Q m can be further simplified [9] to

0 02

coth( )( )2 coth( )

bmI e q qt mQ mm q qt m

μπ

− −= −

+ (2.32)

Thus, the magnetic vector potential in Region I is

1 ( , )zA x y ( )0 00

coth( ) cos( )2 coth( )

b y mm y bI e q qt m e mx dm

m q qt mμ

π

− −∞ − +⎡ ⎤−

= −⎢ ⎥+⎣ ⎦∫ . (2.33)

While (2.33) will lead to a numerical integration directly, we want to see if 1 ( , )zA x y can be

expressed in terms of the direct field and the indirect field from the image source

approximately. With a certain amount of hindsight [9, 19], we expand the following function


31

( ) coth( )coth( )

mdq qt mf m eq qt m

−=

+ (2.34)

into a Taylor series about m=0. Herein, d is a constant complex distance to be determined below. Thus, we have

( )0

nn

nf m a m

∞

=

= ∑ (2.35)

where the expansion coefficients na are given by

( )

0

(0) 1! !

n n

n nm

f d fan n dm

=

⎛ ⎞= = ⎜ ⎟

⎝ ⎠. (2.36)

The first three expansion coefficients are obtained as

0

0 00

( ) 1m

d f madm

=

= = (2.37)

1

1 10

( ) 2coth( )m

d f ma ddm tγ γ

=

= = − (2.38)

22

2 20

( ) 2coth( )m

d f ma ddm tγ γ

=

⎛ ⎞= = −⎜ ⎟

⎝ ⎠. (2.39)

If we choose the complex depth of

2 (1 ) tanh[(1 ) / ]coth( )

d j j tt

δ δγ γ

= = − + , (2.40)

the expansion coefficients a1 and a2 are zero. Thus, it is seen that higher-order terms in (2.35)

can be neglected [9] so that the magnetic vector potential in Region I can be expressed as:


32

( )

( )0 01 0

( , ) cos2

oxox m y h dm y h

zI e eA x y mx dm

m mμ

π

− + +− −∞ ⎡ ⎤

≈ −⎢ ⎥⎣ ⎦

∫ (2.41)

where d is given by [9]

(1 ) tanh[(1 ) ]d j j tδ δ= − + (2.42)

and the skin depth δ is determined as

0

1f

δπ μ σ

= . (2.43)

For a general current distribution ( , )zJ x y , the corresponding vector magnetic potential

( , )zA x y can be expressed in terms of the two-dimensional Green’s function as

0( , ) ( , ', ') ( ', ') ' 'z zA x y G x y x y J x y dx dy

∞= ∫ . (2.44)

By comparing (2.41) and (2.44), the Green’s function in Region I can be written as

1( , ' 0, ' )oxG x y x y h= =( )

( )00

cos2

oxox m y h dm y he e mx dmm m

μπ

− + +− −∞ ⎡ ⎤

≈ −⎢ ⎥⎣ ⎦

∫ (2.45)

where the second term accounts for the contribution of the image filament line current located

at 2 oxD h d= + below the real line current. Thus, the field in Region I is the sum of the direct

field and the image source field. On the other hand, the conductive substrate can be replaced

by a perfect ground plane centered below the real line current at y = D/2.

By considering the complex equivalent inductance [9]

( ) ( ) IldAIjRL ∫ ⋅=Ψ=+ ωωω , (2.46)


33

the effective substrate resistance Rsub,eddy due to eddy currents in the substrate induced by the

time varying magnetic field can be accurately calculated as

[ ], ( ) 2 Im ( )sub eddyR f f M fπ= ⋅ (2.47)

where

2 2

0( ) ln[ 1 ] 12

l lM f ll l

μπ

⎧ ⎫Θ Θ⎪ ⎪⎛ ⎞ ⎛ ⎞= + + − + +⎨ ⎬⎜ ⎟ ⎜ ⎟Θ Θ⎝ ⎠ ⎝ ⎠⎪ ⎪⎩ ⎭ (2.48)

2 4 6 8 10

2 4 6 8 10exp(ln )12 60 168 360 660

w w w w wDD D D D D

Θ = − − − − − . (2.49)

Here, w and l are width and length of the signal line, respectively, D is given by the

relationship 2 oxD h d= + , and d is obtained by (2.42)

Therefore, (2.9) is further modified as

, , 0 ,( ) ( )loop loop DC loop acT sub eddyR f R R f f R f= + + . (2.50)

2.2.4 Model Set-up

Fig. 2.5 One segment of the proposed model. Ns is the number of segments.


34

It is well understood and widely adopted that a frequency independent lumped-element

circuit can accurately approximate frequency dependent behaviors of on-chip interconnects

due to skin, proximity and substrate skin effects [8, 18, 30, 43]. Furthermore, only knowing

the resistance and inductance of an interconnect at DC and at high frequencies is good enough

to synthesize the series branch of such circuits. Therefore, a frequency independent

lumped-element equivalent circuit is adopted in our study, which is compatible to SPICE-like

circuit simulators.

Fig. 2.5 shows one segment of our proposed wide band scalable and SPICE-compatible

model for on-chip interconnects. The number of segments, Ns, depends on the wire length

and signal wavelength. The series branch of the model consists of an RL ladder network,

whose values can be obtained from the effective loop inductance and resistance by using [43]:

1 ,Loop HFL L= , 1 ,Loop HFR R= ,

( )2 , , , ,Loop HF Loop DC Loop HF Loop DCR R R R R= × − ,

( )2

,2 , ,

, ,

Loop HFLoop DC Loop HF

Loop HF Loop DC

RL L L

R R⎛ ⎞

= − ⎜ ⎟⎜ ⎟−⎝ ⎠. (2.51)

The shunt branch comprises Cox accounting for the capacitance of the oxide layer, and Csi in

parallel to Rsi, each of which represents the substrate capacitive coupling and loss,

respectively. Cox can be calculated by using the analytical formulas in [44]. For completeness

of the model and easy reference, this formula is reproduced here

[ ] [ ] ( )2ox ox BOT ox req VP ox req TOP oxC C w h C t h C w t hε ε ε= + + +⎡ ⎤⎣ ⎦ , (2.52)

where εox and hox are the permittivity and the thickness of the oxide layer, and the functions of


35

εreq, CBOT, CVP, and CTOP were given in Table I and II in [44]. Csi and Rsi are obtained from

modified equations based on [45] and are given by

o effsiC l

Fε ε

α⋅

= ⋅ ⋅ (2.53)

( ) 0.5

21 1 10

si

si si

FRh w l

βσ −

⋅= ⋅

⎡ ⎤+ + ⋅⎣ ⎦

(2.54)

and

( ) 0.5

1 12 2 1 10

si sieff

sih wε εε −

+ −= +

+ (2.55)

81 ln2 4

si

si

h wFw hπ

⎛ ⎞= +⎜ ⎟

⎝ ⎠ (2.56)

where ε0, εsi, l, w, and hsi are the permittivity of air, the permittivity of the silicon substrate,

the width of the interconnect, the length of the interconnect and the thickness of silicon

substrate, respectively. α and β in (2.53) and (2.54) are fitting coefficients and can be

estimated, for instance, α=1.98 and 0.19325 3.5105wβ = − × + , where w is in μm.

2.3 Effect of Dummy Metal Fills

The typical structure of an interconnect with dummy metal fills fabricated in a standard

0.18 μm CMOS technology is shown in Fig. 2.6. The width of a square dummy metal fill is wd

and all the dummy fills are inserted with spacing sd to each other. These dummies will affect

the oxide capacitance Cox between the interconnect and the silicon substrate. The oxide

capacitance Cox of a square of p×p area, as shown in Fig. 2.6(b), for an interconnect without

dummies can be simply calculated using a parallel plate approximation of


36

20

6 1

oxox

M M

pChε ε

−

= (2.57)

where ε0, εox and hM6-M1 are the permittivity of free space, the permittivity of oxide layer and

the thicknesses of oxide layers from M1 to M6. In the 0.18 μm CMOS process here,

hM6-M1=1.44×5=7.2 μm, as shown in Fig. 2.6(a). Similarly, Cox of the same area for an

interconnect with dummies can be estimated by

( )2 2 20 0

6 1

' ox ox dox

M M eff

p w wCh h

ε ε ε ε

−

−= +

220

06 1 6 1

1 1oxox d

M M eff M M

p wh h hε ε ε ε

− −

⎛ ⎞= + −⎜ ⎟⎜ ⎟

⎝ ⎠ (2.58)

where heff is the effective thickness of the oxide layer between dummy metal fills in

different metal layers. In our study, heff =(1.44-0.54) ×5=4.5 μm, as shown in Fig. 2.6(a). The

second term in (2.58) is the increased capacitance due to the existence of dummy metal fills.

M6

M5

M4

M3

M2

M1

2.05 µm

1.44 µm0.54 µm

wd sd

p

M6

M5

M4

M3

M2

M1

2.05 µm

1.44 µm0.54 µm

wd sd

p

p

p

(a) (b)

Fig. 2.6 (a) Cross section, and (b) top view of an interconnect on M6 with dummy metal fill-cells from M5 to M1 fabricated by 0.18 μm CMOS technology. Dark cells are dummies. The width, spacing and pitch of dummies are wd, sd and p, respectively.

2.4 Empirical Formulas for Elements in Series Branch

In order to make our model easily used by digital IC designers, we provide a set of

empirical formulas for elements in series branch of our model, i.e. R1, R2, L1 and L2. These


37

formulas are obtained by applying a multiple regression technique to fit a large data pool

generated from (2.51). This data pool consists of more than two hundred interconnects with

different widths and lengths. The widths and lengths for these interconnects are randomly

chosen in the range from 2 μm to 30 μm for the width, and 200 μm to 1200 μm for the length.

Table 2.1 The Coefficients of Empirical Formulas for the Elements in Series Branch of the Proposed Model

a0 a1 a2 a3 a4 a5 a6 a7 a8

R1 -2.1273301 1.3081E-2 6.7143E-2 6.7916E-6

R2 -0.0407170 1.2100E-3 2.2570E-4 0.651395 -0.859704 1.4148E-2 3.1379E-3 -6.6008E-7

L1 0.1224537 -4.4640E-3 7.2261E-4 -0.889037 1.328043 2.4279E-3 -3.1320E-3 -1.0903E-7

L2 -0.0050661 -8.5906E-5 5.4229E-5 -0.059582 0.101631 2.2026E-4 -3.6532E-4 1.3020E-7 1.2220E-7

The closed-form formulas for R1, R2, L1 and L2 have the general form as

1 21 2 1 2 0 1 2 3 4, , ,R R L or L a a w a l a w a w− −= + ⋅ + ⋅ + ⋅ + ⋅ ( )22 2

5 6 7 8a l w a l w a l w a l+ ⋅ + ⋅ + ⋅ + ⋅

(2.59)

where the coefficients, ai (i=0,1,…8), are tabulated in Table 2.1. The units of w and l in (2.59)

are both μm. L1 and L2 are calculated in nH, while R1 and R2 are obtained in Ω. Statistical

measure of goodness-of-fit, R square, is equal to 100%, which indicates a perfect fit to (2.51)

by using (2.59). When we fitted (2.59), we fixed the thickness of the interconnects to 2 μm,

which is the nominal thickness of M6 in a typical RF CMOS technology, because long global

interconnects are always allocated at the top metal layer. Additionally, we assumed that the

structure of test interconnects is similar to the structure shown in Fig 2.7, i.e., a signal line

parallel to two ground lines, since this G-S-G configuration is commonly adopted for on-chip

measurements. The default metal is aluminum. Thus, combining (2.53)-(2.56) and (2.59), we

provide a set of closed-form formulas, which can be easily used to quickly calculate the


38

values of lumped elements in the proposed model as shown in Fig. 2.5.

Fig. 2.7 The cross-section of the test interconnects fabricated in 0.18 μm CMOS technology. All the test interconnects are located on M6. The widths of interconnects are either 6 μm or 10 μm, while the lengths of interconnects are from 400 μm to 1000 μm. All numbers labeled in the figure are in μm.

2.5 Measurements and De-embedding

To verify our model, a group of on-chip interconnects with widths varying from 6 µm to

10 µm, lengths ranging from 400 µm up to 1000 µm, and with or without metal dummy metal

fills was fabricated in a commercial 0.18 µm CMOS technology. The technology consists of

six metallization layers, and the interconnects were placed on the top layer. The metal

dummies inserted were 2×2 µm2 in size, and repeated uniformly with a spacing of 2 µm on all

metallization layers. The structure of an interconnect without metal dummies in cross-section

view is shown in Fig. 2.7. The signal interconnect parallel with two ground lines constitutes

the G-S-G configuration to meet the on-chip measurement requirement. Measurements were

performed using the Anritsu W3700 broadband VNA for 110 GHz, SUSS semi-auto probe

station and Cascade infinity G-S-G probes. The system was calibrated to the probe-tip-planes

using LRM+ calibration method [46].


39

Symmetric plane

l

(a) (b)

Reference planes

l/2 l/2L

Probe-tip-planes Probe-tip-planes

Symmetric plane

l

(a) (b)

Reference planes

l/2 l/2L

Probe-tip-planes Probe-tip-planes

Y Y

Z Z

parasitics parasitics

Y Y

Z Z


DeviceUnder Test

(DUT)

Symmetric plane Reference planes

(c) (d)

Y Y

Z Z


Y Y

Z Z


Y Y

Z Z


DeviceUnder Test

(DUT)

Symmetric plane Reference planes

(c) (d)

Fig. 2.8 Configurations of the measured structures. (a) The THRU structure and (b) the interconnect test-structure; the circuit models of (c) the THRU structure and (d) the interconnect test-structure. The reference planes correspond to the symmetric plane depicted in (c).

The de-embedding technique using a two-impedance model, reported in [47-49], is adopted in

this study. Fig. 2.8 shows the configurations of the measured structures. A THRU structure is

utilized to de-embed the interconnect test-structures to the desired reference planes. This

method is applicable where the interconnects on both sides of the device under test (DUT) have

the same length of l/2. The THRU is designed as a combination of the contact pads and the two

cascaded l/2 long interconnects. Using symmetry, the THRU can be modeled as two mirrored

lumped networks as shown in Fig. 2.8(c) while the interconnect test-structure is represented as a

cascade of three networks in Fig. 2.8(d). The lumped elements Y and Z are frequency

dependent parameters reflecting the pad and interconnects parasitics respectively and can be


40

found using the following equation

1 11 1THRU

a b Z YZ Zc d Y YZ Y

+⎛ ⎞ ⎛ ⎞⎛ ⎞=⎜ ⎟ ⎜ ⎟⎜ ⎟+⎝ ⎠ ⎝ ⎠⎝ ⎠

(2.60)

where (a, b,c, d)THRU is the ABCD-matrix converted from the measured S-parameters of

the THRU. Hence, the ABCD-matrix of the DUT is obtained from

1 11 1

1 1DUT meas

a b Z a b YZ Zc d Y YZ c d Y

− −+⎛ ⎞ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞=⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟+⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠

(2.61)

where (a, b,c, d)meas is the ABCD-matrix obtained from the measured S-parameters of

the interconnect test-structures. It is noted that the length of the interconnect used in the

“thru” calibration structure is 100 µm and after de-embedding the length of the interconnect

will reduce by 100 µm from its original length before de-embedding. For instance, a 1000µm

long interconnect will become a 900 µm long interconnect after de-embedding. Thus,

hereafter, the length of interconnect always refers to its length after de-embedding.

2.6 Experimental Results and Model Validation

Two interconnects with l=900 µm, w=10 µm and l=800 µm, w=6 µm are simulated

by our model and compared with the measurement results and simulation results by using

full-wave solver Momentum [127] in terms of S-parameters in Fig. 2.9. In order to obtain

accurate results, both grounds parallel to the signal interconnect are meshed into three cells

with the same length but one third of its original width. As shown in Fig. 2.9, a good

agreement is found from DC to 110 GHz. It should be noted that the simulated results


41

Fig. 2.9 Simulated S-parameters by using our model are compared with measured results (symbols) and simulation results by Momentum (dots) for two interconnects with length of 900 µm and width of 10 µm, and length of 800 µm and width of 6 µm, respectively. The lumped-elements in the series branch of our model are obtained by either analytical method in (2.51) (for solid line) or empirical formulas in (2.59) (for dashed line), while those in the shunt branch are given by (2.53)-(2.56)

using empirical formulas (2.59) incorporating (2.53)-(2.56) are almost exact with the results

by using (2.51) and (2.53)-(2.56), which indicates the empirical formulas (2.59) are accurate

enough to calculate the lumped-elements in the series branch of the proposed model and

characterize on-chip interconnects.

Fig. 2.10 shows the excellent agreement between measured and modeled S-parameters

plotted in the Smith Chart. In addition, the values of the lumped elements in the proposed

models for fabricated test interconnects with widths 6 µm and 10 µm and lengths ranging


42

from 300 µm to 900 µm are tabulated in Table 2.2. All the values in Table 2.2 are obtained by

(2.51) and (2.53)-(2.56). The simulation results by using our model agree well with the

measurement data from DC to 110 GHz for all the fourteen test interconnects, though some of

them are not plotted here. The number of segments of our model, Ns, is chosen from 5 to 15,

which depends on the lengths of the interconnects.

Fig. 2.10 Smith Charts of simulated S-parameters by using (2.51) and (2.53)-(2.56) are compared with measured results for four interconnects with different lengths and widths, l=300 µm, w=10 µm, l=800 µm, w=10 µm, l=600 µm, w=6 µm and l=900 µm, w=6 µm, respectively. The frequency range is from DC up to 110GHz. Symbols represent measurement results and solid lines stand for simulations results. These smith charts show the good scalability and high accuracy of our model.


43

Table 2.2 The Values of Lumped Elements of the Proposed Model for Interconnects with Different Widths and Lengths by Using (2.51) and (2.53)-(2.56)

w (μm) l (µm) R1(Ω) R2(Ω) L1(nH) L2(nH) Cox (fF) Csi (fF) Rsi (Ω)

300 5.86875 0.84774 0.28804 0.02381 24.20500 37.65148 66.02972

400 8.60990 1.11563 0.38568 0.03961 32.27330 50.20191 49.52217

500 11.61970 1.38133 0.48047 0.05869 40.34170 62.75234 39.61788

6 600 14.83440 1.64585 0.57257 0.08078 48.41000 75.30277 33.01486

700 18.20420 1.90971 0.66221 0.10560 56.47840 87.85319 28.29852

800 21.69170 2.17321 0.74957 0.13294 64.54670 100.40382 24.76120

900 25.26930 2.43649 0.83486 0.16259 72.61500 112.95425 22.00990

300 4.52607 0.52954 0.26401 0.02262 26.53330 41.68692 51.54000

400 6.81970 0.69667 0.35356 0.03762 35.37770 55.58256 38.65500

500 9.38200 0.86279 0.44025 0.05579 44.22210 69.47820 30.92407

10 600 12.14920 1.02841 0.52426 0.07686 53.06650 83.37364 25.77000

700 15.07150 1.19379 0.60579 0.10060 61.91090 97.26928 22.08853

800 18.11140 1.35906 0.68506 0.12676 70.75530 111.16492 19.32750

900 21.24150 1.52428 0.76225 0.15516 79.59980 125.06056 17.18000

Our model is also able to characterize interconnects in the presence of dummy metal fills

by using (2.58) to estimate Cox. For our test interconnects with dummies, the Cox increases by

15%. S-parameters of a 900 µm long and 6 µm wide interconnect with dummies are measured

and compared with the simulated results from our model in Fig. 2.11. The solid lines


44

represent the results obtained from our model including the effect of dummy metal fills, while

the dashed lines account for the results by using our model excluding the dummy metal fills.

Again, a good agreement is obtained, demonstrating the capability of our model to

characterize the impact of dummy metal fills.

10 20 30 40 50 60 70 80 90 100 110

-30

-25

-20

-15

-10

-5

-20

0

20

40

60

80

l=900μmw=6μmwith dummies

Symbols: Measured data The proposed model w/i dummies The proposed model w/o dummies

dB

(S11

)

Frequency (GHz)

Pha

se(S

11)

(a)

(b)

Fig. 2.11 The measurement results for a test interconnect with dummy metal fills are compared with simulated S-parameters by using our model including the dummy effects (solid lines) and excluding the dummy effects (dashed lines), respectively. The length and width of the interconnects are 900 μm and 6 μm, respectively.


45

2.7 Summary

A wide band scalable and SPICE compatible lumped element model for on-chip

interconnects is successfully developed in this chapter. This model has been validated by

measurements for a group of interconnects with different widths and lengths. The model is

accurate from DC up to 110 GHz and it is also able to predict the impact of dummy metal fills.

In addition, a set of closed-form formulas for calculation of the lumped elements in the model

is provided here. These formulas can be easily used by IC designers to characterize on-chip

global interconnects.

Chapter 3 Characterization of On-Chip Coupled Interconnects

Chapter 3. Characterization of On-Chip Coupled (A)Symmetrical Interconnects

Based on several extended formulas to determine all frequency- and temperature-dependent

distributed parameters of on-chip coupled asymmetrical and symmetrical interconnects on

silicon substrates, electromagnetic-thermal characteristics of interconnects were investigated in

detail, including (a) wideband series impedances and shunt conductances; (b) conductive and

dielectric attenuation constants of even (c) and odd (π)- mode; (c) pulse waveform distortion

and crosstalk; and (d) average power handling capability (APHC). In these investigations, a set

of modified formulas was proposed to determine the mutual conductance and capacitance of

asymmetrical configuration. Appropriate thermal models were employed to evaluate the rise in

temperature of metal interconnects, where the lateral heat dissipation was taken into account for

different spacings between two interconnects. Parametric calculations were performed to

capture the hybrid effects of all geometric and physical parameters of metal interconnects, such

as line thickness, line conductivity, and silicon conductivity. All numerical examples are

believed to be useful in the design of (a)symmetrical interconnects for digital and radio

frequency circuits. The proposed model is validated by experimental results.


47

3.1 Introduction

During the past decades, many studies have been carried out for electromagnetic

modeling of single metal-insulator-silicon interconnects. Based on a large number of

theoretical works, several analytical equations have been proposed for fast calculating of

per-unit-length series impedance and shunt admittance, slow-wave factor, attenuation

constant and characteristic impedance of a single silicon-based interconnect [50-57]. These

equations have been verified experimentally, and they have been shown to be very useful for

global simulation and optimization of high-density and high-speed three-dimensional

interconnects. On the other hand, many works were also done for modeling of coupled

interconnects [7, 9, 58-63]. For example, based on the complex image method, Weisshaar et

al [9] proposed some analytical equations for the self- impedance, self-admittance, and

mutual impedance of coupled interconnects. Furthermore, the series impedance of

interconnects on multilayer silicon substrates was reported in [63]. Based on hybrid

conformal mapping and complex image method, Chiu [64] derived a set of equations for the

mutual impedance and mutual admittance of silicon substrate, which is significant and

important in the fast electromagnetic optimization of symmetrically coupled interconnects in

various silicon-based integrated circuits.

To accurately describe wideband electromagnetic characteristics of coupled interconnects,

effects of all geometric and physical parameters, such as metal line thickness, electrical

conductivity and even operating temperature, must be treated appropriately. The temperature

rise due to Joule heating or self-heating of all on-chip metal lines can degrade the interconnect

performance significantly [65-68], such as signal waveform distortion, electromigration,

power handling and even thermal breakdown of the interconnect. In a high-power RF circuit,


48

thermal effects on interconnect performance are another serious design constraint.

In this chapter, electromagnetic-thermal modeling of on-chip coupled (a)symmetrical

interconnects is performed, including all distributed parameters, conductive and dielectric

attenuation constants of even (c) and odd )(π -modes, pulse waveform distortion, crosstalk

and even average power handling capability (APHC). To predict the APHC of coupled

interconnects, the frequency- and temperature-dependent variables related to coupled

interconnects must be accurately captured first. Since silicon conductivity siσ has a

dominant effect on the interconnect performance, procedures used to predict APHC of

single normal and thin film microstrip lines on polyimide and polyimide/GaAs substrates are

not effective to handle the metal-insulator-silicon interconnects.

3.2 Coupled On-Chip Interconnects

Fig. 3.1(a) shows the cross-sectional view of an on-chip coupled interconnect on

double-layer 2SiO and silicon substrates. Two interconnects are characterized by metal line

widths of 1W and 2W , line thickness of 1t , and line conductivity of )(Tσσ = , where T is

the operating temperature. For the symmetrical case, we have 1W = 2W . The permittivities of

2SiO and silicon are represented by oxε and siε = )(Tsiε , respectively. The silicon

conductivity is =siσ )(Tsiσ , which is also very sensitive to temperature. The thickness of

2SiO is oxt , and oxt is much smaller than the thickness of silicon, denoted by D. The

thermal conductivities of 2SiO and silicon are given by )(1 Tκ and )(2 Tκ , respectively,

Fig. 3.1(b) shows the equivalent circuit model of the coupled interconnects, where the

per-unit-length series resistances, mutual resistance, series inductances, mutual inductance

are represented by 11R and 22R , 12R , 11L and 22L , and 12L , respectively. When 1W = 2W ,


49

we have 11R = 22R and 11L = 22L . The shunt capacitances with respect to 2SiO and silicon

layers, and the shunt silicon conductances of the coupled interconnects are denoted by 1oxC

and 2oxC , 1siC and 2siC , 1siG and 2siG , respectively. In particular, the mutual capacitance

and conductance of the silicon substrate are represented by simC and simG , respectively. It is

believed that this equivalent model can also be easily extended to cases of multi-layer silicon

substrates or multiple interconnects on single-layer silicon substrate.

(a)

SiO2

silicon

L1(f)

R1(f)

Cox1

Csi1(f)Gsi1(f)

L2(f)

R2(f)

Cox2

Gsi2(f)Csi2(f)

CmGsim

Csim

W1

Lm(f)

Y

Y=0

(b)

Fig. 3.1 On-chip coupled interconnects: (a) cross-sectional view and (b) equivalent circuit model.

For coupled interconnects made of aluminum, gold or copper, the temperature-dependent

electrical conductivity )(Tσ over 253 to 500 K can be described as follows:


50

∑=

×=3

0

710)(n

nnTaTσ (S/m) (3.1)

where the curve fitting coefficients na (n = 0, , 3) are obtained based on the data given in

[69] and summarized in Table 3.1. Physically, as temperature increases, the value of )(Tσ

for all metals decreases monotonously.

Table 3.1 Coefficients of Aluminum, Gold, and Copper

0a 1a 2a 3a

Aluminum 9.99227 -0.03134 0.00004 -1.7425 810−×

Gold 11.11207 -0.03257 0.00004 -1.6706 810−×

Copper 16.96471 -0.05724 0.00008 -3.6809 810−×

For an extrinsic silicon semiconductor, it is well known that the drift current with an

electric field applied can be described by

EpnqJJJ pnpn )( μμ +=+= (3.2)

where nJ ( pJ ), n (p), and nμ ( pμ ) are electron (hole) drift current density, electron

(hole) density, and electron (hole) mobility, respectively. The corresponding electrical

conductivity can be described by [70]

[ ])()(106.1)( 19 TTT pnsi μμσ +×= −

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎟⎟⎠

⎞⎜⎜⎝

⎛−

⎥⎥⎦

⎤

⎢⎢⎣

⎡×⋅

kTE

mmm

T gpn

2exp1083.4 2

**2/321 (3.3)

where *nm is the electron effective mass , *

pm the hole effective mass, gE the silicon band

gap, and k the Boltzmann constant.


51

For most doped silicon materials, )(Tsiσ ∝ β−T . When lattice scattering is dominant

( )5.1=β , the extrinsic conductivity for p-type silicon can be evaluated by [70]

2/3

19

300)300(106.1)(

−− ⎟

⎠⎞

⎜⎝⎛=×≈

TKTnT ppsi μσ (S/cm) (3.4)

where the hole-mobility at room temperature is a function of dopant concentration given as

follows:

minminmax

)/(1)300( μ

μμμ α +

+−

==refp

p nnKT (3.5)

with maxμ sVcm ⋅= /495 2 , minμ = sVcm ⋅/7.47 2 , α = 0.76, refn = 16 36.3 10 cm−× , pn

representing the substrate dopant concentration.

3.3 Distributed Parameters and Propagation Constants

For coupled asymmetrical interconnects, both “c” and “π” modes can be supported with

different propagation constants denoted by )( fcγ and )( fπγ [71, 72], respectively. For

symmetrical interconnects, the supported modes are reduced to even- and odd- modes, with

propagation constants )( feγ and )( foγ . The propagation constants )( fcγ and

)( fπγ can be represented by

)( fcπ

γ = )()( fjf ccππ

βα + (3.6)

and

)( fcπ

α = )()( ff dcd

ccc ππ

αα + (3.7)

where )( fcπ

β and )( fcπ

α in (3.6) are phase and attenuation constants, respectively, and


52

)( fcccπ

α and )( fdcdπ

α in (3.7) are conductive and substrate attenuation constants,

respectively.

To accurately characterize these frequency- and temperature-dependent variables, an

alternative is to first characterize all frequency-dependent distributed parameters in Fig.

3.1(b), i.e.,

[ ] ⎥⎦

⎤⎢⎣

⎡=

2212

1211

RRRR

R , [ ] ⎥⎦

⎤⎢⎣

⎡=

2212

1211

LLLL

L , [ ] ⎥⎦

⎤⎢⎣

⎡=

2212

1211

CCCC

C , [ ] ⎥⎦

⎤⎢⎣

⎡=

2212

1211

GGGG

G . (3.8)

3.3.1 Resistances and Inductances

At a given temperature, the series self-resistance )( 2211 RR and self-inductance )( 2211 LL

in (3.8) can be calculated by

),(])(/[1),( 22,1112,122,11 TfRtWTTfR ac+= σ (3.9)

))(,(Im2),( 22,1122,11 TfLfTfR sicfac σπ−= (3.10)

))(,(Re[),( 22,1122,11 TfLTfL sicf σ= (3.11)

⎪⎭

⎪⎬

⎫

⎪⎩

⎪⎨

⎧

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛++⎟⎟

⎠

⎞⎜⎜⎝

⎛+=

2

2,1

2

2,1

022,11 ))(,(8

11))(,(

321ln4

))(,(TfD

WW

TfDTfL

sieff

sieffsicf σ

πσπ

μσ

(3.12)

)](/)1tanh[()(2

1))(,( TDjTjtTfD sisioxsieff δδσ +−

+= (3.13)

where [ ], ( )eff siD f Tσ is the effective depth of the silicon substrate [9] and

[ ]01/ ( )si sif Tδ π μ σ= .


53

Substituting (3.13) into the formula of mutual inductance of edge coupled symmetrical

microstrip lines, the mutual impedance 12Z can be derived, as shown in [64]. Furthermore, it

can be modified to be applicable for asymmetrical coupled interconnects, and given by

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

++=+=

2

0121212

))(,(21ln

4),(),(),(

SWTfDjTfLjTfRTfZ sieff σ

πωμω (3.14)

where W = 2/)( 21 WW + . Based on these equations, we can extract 11R , 22R , and 12R of the

asymmetrical interconnects at room temperature T = 298 K, with W1=2 μm, W2=1 μm, S=2

μm, tox=3 μm, D=300 μm, σ =3.5×107 S/m, for n-type highly doped silicon substrate σsi =104

S/m [62]. The metal line thicknesses are chosen to be 1t =1 and 2 μm, respectively, as shown

in Fig. 3.2. It is obvious that 11R and 22R are very sensitive to the variation of line

thickness, but 12R does not change as 1t is increased from 1 to 2 μm. To check the accuracy

in the characterization of 11R , 22R and 12R , we compared our results with those reported in

[62] and [64], and excellent agreements are obtained. The series resistances 11R and 22R

can be described by

[ ])(1)()( 029822,1122,11 TTCfRfR mTTT −+= = (3.15)

where mTC is the temperature coefficient of resistance. For interconnects made of aluminum

or copper, the values of mTC are found to be 31073.3 −× and 3102.3 −× /K, respectively.


54

0 2 4 6 8 10Frequency(GHz)

0

100

200

300

400

500

R11

, R22

and

R12

(ohm

/cm

)R22

R11

R12

R22

R11

W1=2um, W1=1um, S=2umtox=3um, D=300um t1=1um(solid lines); 2um(dash lines)circular dots: Weisshaar et al.

Fig. 3.2 Self-resistances 11R and 22R , and mutual resistance 12R for asymmetrical coupled

interconnects versus for different line thicknesses at room temperature.

With the same geometry as that shown in Fig. 3.2, Fig. 3.3(a) and 3(b) demonstrate the

calculated mutual-resistance ( 12R ) and mutual-inductance )( 12L versus frequency at

temperatures T= 300, 350, and 450K, respectively. At room temperature (300K), the donor

concentration of an n-type silicon substrate is assumed to be n = 315105 −× cm , which

corresponds to a conductivity of 111 S/m [73]. It is obvious that the mutual impedance 12Z is

very temperature- and frequency-dependent even for the cases with slight doping. At a given

frequency, as temperature increases the value of 12R decreases, whereas 12L increases.

Physically, temperature rise will cause the decrease in siσ , which further cause the increase

in skin depth siδ . Hence, the rise in temperature will reduce the magnetic field intensity in

substrate induced by metal interconnects. These mechanisms are explicitly represented by

12R and 12L , as shown in Fig. 3.3.


55

0 4 8 12 16 200

20

40

60

80

100

120

aluminum

IIIIIIW1=2um, W2=1um,S=2um, t1=1um

tox=3um, D=300um

450K

350K

T=300K

R12

(ohm

/cm

)

Frequency(GHz)

(a)

0 4 8 12 16 209.95

10.00

10.05

10.10

10.15

10.20

10.25

10.30

10.35

W 1 S W 2

to x

D

t 1

Ξ

Ξ

o x

s i ΞS i= 1 0 0 0 0S /m

Ξ

450K

350K

T=300K

L12(

nH/c

m)

Frequency(GHz)

(b)

Fig. 3.3 (a) Mutual- resistance ( 12R ) and (b) mutual–inductance )( 12L for asymmetrical coupled

interconnects versus frequency at different temperatures. σsi =104 S/m.

3.3.2 Capacitances and Conductances

Each element in the overall shunt admittance matrix of the above coupled interconnects

can be expressed by


56

[ ] ⎥⎦

⎤⎢⎣

⎡=

)()()()(

)(2221

1211

fYfYfYfY

fY (3.16)

where

145632

11 )(//)]()(//[11)(

ZfZfZfZZZfY

+++= ,

)]()][(//)()()](//)(//[)(1

1)(

41416541563

212

fZZfZZfZfZfZZfZfZZ

ZfY

+++++−

−=

)]()][(//)()()](//)(//[)(1

1)(

63634563541

221

fZZfZZfZfZfZZfZfZZ

ZfY

+++++−

−=

365412

22 )(//)]()(//[11)(

ZfZfZfZZZfY

+++= ,

and [9]

,)()(

1)(,1,1,1

114

232

11 fCjfG

fZCj

ZCj

ZCj

Zsisioxmox ωωωω +

====

)()(

1)(5 fCjfGfZ

simsim ω+= ,

)()(1)(

226 fCjfG

fZsisi ω+

= . (3.17)

In [64], the formulas to calculate frequency-dependent mutual conductance simG and

capacitance simC are only for symmetrically coupled configuration. For asymmetrical case

shown in Fig. 3.1(a), following the similar procedure proposed in [64], simG and simC can

be calculated by

),( TfGsim =2)()()(

kKkKTsi

′σ (3.18)

),( TfCsim = ),()(

0 TfGT sim

si

si

σεε (3.19)


57

where )(⋅K is the complete elliptic integral of the first kind, 21 kk −=′ , and

))((

)(

sysx

ssyx

dddddddd

k++

++= (3.20)

( , ) 1.5 ( , )cosh cosh

( , ) ( , )ave ave

xave ave

S W jh f T S W jh f Td

h f T h f Tπ π⎧ ⎫ ⎧ ⎫⎡ ⎤ ⎡ ⎤+ + + +⎪ ⎪ ⎪ ⎪⎣ ⎦ ⎣ ⎦= −⎨ ⎬ ⎨ ⎬

⎪ ⎪ ⎪ ⎪⎩ ⎭ ⎩ ⎭ (3.21)

0.5 ( , ) ( , )cosh cosh

( , ) ( , )ave ave

save ave

W jh f T S W jh f Td

h f T h f Tπ π⎧ ⎫ ⎧ ⎫⎡ ⎤ ⎡ ⎤+ + +⎪ ⎪ ⎪ ⎪⎣ ⎦ ⎣ ⎦= −⎨ ⎬ ⎨ ⎬

⎪ ⎪ ⎪ ⎪⎩ ⎭ ⎩ ⎭ (3.22)

[ ]⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧ +

−−=),(

),(5.0cosh1

TfhTfjhW

dave

avey

π (3.23)

)1)((),( )(/ TDsiave

SIeTTfh δδ −−= . (3.24)

Therefore, we can further accurately capture the frequency- and temperature-dependent

mutual capacitance 12C and conductance 12G using (3.27) and (3.28) as listed below. They

play key roles in the characterization of the coupling effects between two lines on a silicon

substrate. Since the effects of the finite metal line thickness 1t in Fig. 3.1(a) are taken into

account, the capacitances 1oxC , 2oxC , and mC should be calculated by some special

methods, such as those proposed in [44]:

[ ] [ ] [ ] ⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

−+⎟⎟⎠

⎞⎜⎜⎝

⎛=

oxTOP

oxVP

ox

oxoxBCP

ox

ox

ttW

Ctt

C

ttSt

St

WC

C

1

2,112

1

2,1

0

2,1 25.0)(

2/5.01

1276.0,εε

(3.25)

[ ] [ ] )(2/1

87.02/

2,

2/1

5.0 2,12

1

12

1

0 SW

C

ttSS

tSt

C

ttS

CCP

ox

oxBCP

ox

ox

m

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

+⎟⎠

⎞⎜⎝

⎛

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+

=εε

(3.26)

where [ ]BOTC , [ ]VPC , [ ]TOPC , and [ ]CPC are defined in [44] and calculated numerically.


58

From the shunt admittance matrix in (3.16), the shunt conductance and capacitance matrices

can be further calculated by

[ ] [ ])(Re)( fYfG = (3.27)

[ ] [ ] ω/)(Im)( fYfC = (3.28)

Fig. 3.4 shows the extracted capacitance 12C over 0.1 to 20GHz for two asymmetrical

coupled interconnects with line spacing of S =2 µm and 4 µm, respectively. It should be

emphasized that, in order to calculate 12C , we need to first calculate 1siC , 1siG , 2siC , and

2siG , based on the works reported in [9, 74-76], where the high-frequency effects on the line

characteristic impedance, effective permittivity and effective line width should be treated

appropriately. The capacitive coupling is a function of operating frequency, line spacing, line

thickness, and silicon conductivity, etc. Fig. 3.4 shows that, as siσ increases up to 10 S/m,

12C becomes frequency-independent at low frequencies. If we further increase siσ to as

high as 1000 S/m, 12C becomes a constant over 0.1 to 20 GHz approximately. Physically, as

frequency approaches zero, the displacement current is negligible as compared to the

conduction current in a lossy silicon substrate. Under such circumstances, 12C is dominant

by mC , i. e., the capacitance between two interconnects through 2SiO and air (Fig. 3.1(b)).

As frequency increases, due to skin effects, the conduction current flowing between two

interconnects can be neglected approximately, when compared with the displacement

current. Hence, the silicon substrate behaves as a dielectric for the electrical coupling

between two interconnects. As a result, 12C approaches to simC at high frequencies. The

larger the silicon conducitivity siσ , the higher the frequency where the displacement current


59

can be comparable to the conduction current. Therefore, 12C is dominant by mC and tends

to be frequency-independent from 0.1 to 20 GHz approximately, when siσ = 1000 S/m.

0 1 10Frequency(GHz)

-0.8

-0.6

-0.4

-0.2

0.0

C12

(pF/

cm)

.1 20

W1=4um, W2=1um, t1=1um tox=2um, D=500um

1S/m

10S/m

100S/m

1S/m10S/m

100S/mS=4um

S=2um

Fig. 3.4 Mutual capacitance )(12 fC as a function of frequency for asymmetrical coupled

interconnects for different line spacings and silicon conductivities.

Fig. 3.5(a)-(c) show the mutual conductance 12G versus silicon conductivity at f =1, 5, 10,

15 and 20 GHz, respectively. It should be emphasized that the 12G versus frequency for

on-chip coupled interconnects of either slightly or heavily doped case, shown in [64], can be

easily reproduced using our code. In Fig. 3.5(a), two line widths are === WWW 21 2 and 4

µm, respectively. In Fig. 3.5(b), 121 === WWW µm, with line spacing of 1=S and 2 µm,

respectively. In Fig. 3.5(c), 41 =W µm, 12 =W µm, with S = 2 and 4 µm, respectively. Over

an ultra-wide range of silicon conductivity from the case of slight doping ( siσ = 01.0 S/m ) to

that of high doping ( siσ = 410 S/m ) , following observations can be made.

(1) 12G does not change monotonously with siσ , with a sharp knee in each curve. For a

slightly doped silicon substrate ( 5<siσ S/m), 12G increases linearly with siσ . After that


60

knee, with increasing siσ , 12G increases dramatically and then rolls off after it reaches a

peak value. This fast drop is caused by the skin effects of conducting substrate for highly

doped case, i. e. siσ ～10 4 S/m. With high conductivity siσ , the electrical field in the

substrate concentrates near the interface between silicon and 2SiO layers. As siσ

approaches infinity, the silicon substrate will behave as a perfect conductor, and therefore,

there will be no conduction current flowing through the silicon substrate between coupled

interconnects. Then, most of electrical field is only coupled through the capacitances simC

and mC rather than simG . As a result, the substrate loss, due to electrical coupling between

two interconnects, is reduced. This is also the reason of the decrease in 12G .

(2) At a certain value of siσ , 12G reaches its maximum ( (max)12G ). The higher the

operating frequency, the larger the value of (max)12G . In Fig. 3.5(a)-(c), corresponding to (max)

12G ,

siσ is in the range of 10010 << siσ S/m.

0 0 1 10 100 1000 100000

4

8

12

16

20

G12

(mS/

cm)

10

5

1

15

f=20GHz

W=2um(solid line), 4um(dot line)S=2um, t1=1um, tox=2umD=500um

.1.01

(a) mS μ2= , === WWW 21 2 (solid line) and 4 µm (dot line)

W S W

tox

D

t1

ox

si si

Silicon Conductivity (S/m)


61

. 0 0 1 10 100 1000 10000

Silicon conductivity(S/m)

0

2

4

6

8

10

G12

(mS/

cm)

.01 .1

f=20GHz

15

10

5

1

W=t1=1um, tox=2um, D=500umS=1um(solid line), 2um(dot line)

(b) 121 === WWW µm, 1=S (solid line) and 2µm (dot line)

0 0 1 10 100 1000 10000

Silicon conductivity(S/m)

0

4

8

12

16

G12

(mS/

cm)

.01 .1

f=20GHz

15

10

51

W1=4um, W2=1um, t1=1umtox=2um, D=500umS=2um(solid line), 4um(dot line)

(c) 41 =W µm, 12 =W µm, 2=S (solid line) and 4µm (dot line)

Fig. 3.5 Mutual conductance )(12 fG versus silicon conductivity for different (a)symmetrical

coupled interconnects at different frequencies.


62

(3) (max)12G increases with increasing line width (Fig. 3.5(a)) or line spacing (Fig. 3.5(b,

c)). Based on a number of numerical simulations, it is found that when S=1, 2, 3, and 4 µm,

we have

(max)12G = fWWW ⋅+⋅+++ )2.06.1()00396.002201.0()00245.000716.0( (3.29)

(max)12G = fWWW ⋅+⋅+++ )2.08.1()00372.002196.0()00258.000729.0( (3.30)

(max)12G = fWWW ⋅+⋅+++ )2.00.2()00345.002182.0()00265.000742.0( (3.31)

(max)12G = fWWW ⋅+⋅+++ )2.02.2()00323.002123.0()00269.000755.0( (3.32)

where the frequency is in GHz and W is in µm. Evidently, when the parameters of W and S are

given, (max)12G is proportional to the operating frequency. Corresponding to (max)

12G , the value

of siσ is noted by (max)siσ , and when the substrate thickness is 300～500 µm, it is found

that,

(max)siσ ～ fWS ⋅+⋅+ )](2.04.1[ . (3.33)

With the same geometry as that in Fig. 3.3, except for the silicon thickness mD μ500= , Fig.

3.6 shows the effects of rise in temperature on the mutual conductance 12G at f = 5 and 10

GHz, respectively. It is interesting to note that the rise in temperature has no effect on (max)12G ,

which tends to shift to larger value of siσ . This is reasonable because the silicon

conductivity decreases with temperature. As a result, (max)12G at higher temperature with the

same value as that at room temperature needs a larger conductivity.


63

0.01 0.1 1 10 100 1000 100000

1

2

3

4

5 W 1 S W 2

t o x

D

t 1

o x

s i S i= 1 0 0 0 0 S /m

500

400

300K

10GHz

5GHz

G12

(mS/

cm)

silicon conductivity (S/m)0.01 0.1 1 10 100 1000 10000

0

1

2

3

4

5 W 1 S W 2

t o x

D

t 1

o x

s i S i= 1 0 0 0 0 S /m

500

400

300K

10GHz

5GHz

G12

(mS/

cm)

silicon conductivity (S/m)

Fig. 3.6 Mutual conductance )(12 fG versus silicon conductivity for asymmetrical coupled

interconnects at different frequencies and temperatures.

3.3.3 Propagation Constants

At a given temperature, the frequency-dependent propagation constants )( fcπ

γ of the c-

and π -modes can be calculated by [71, 72]

[ ] 2/1

212

21212 )()(4)()(

21

2)()()( fbfbfafafafafc +−±

+=

πγ (3.34)

with variables given by

1 1 1( ) ( ) ( ) ( ) ( )m ma f Y f Z f Y f Z f= + , 1 1 2( ) ( ) ( ) ( ) ( )m mb f Z f Y f Y f Z f= +

2 2 2( ) ( ) ( ) ( ) ( )m ma f Y f Z f Y f Z f= + , 2 2 1( ) ( ) ( ) ( ) ( )m mb f Z f Y f Y f Z f= +

1,2 11,22 11,22( ) ( ) ( )Z f R f j L fω= + , 1,2 11,22 11,22( ) ( ) ( )Y f G f j C fω= +

12 12( ) ( ) ( )mZ f R f j L fω= + , 12 12( ) ( ) ( )mY f G f j C fω= + . (3.35)

The characteristic impedances of interconnects 1 and 2 for c- and π -modes, respectively, are


64

determined by

)]()()()[()()()(

)(,2,

221

1,1 fRfZfZffZfZfZ

fZcmc

mc

πππ γ −

−= , (3.36)

)]()()()[()]()()()[(

)(,1,

221,

2,2 fZfRfZffZfZfZfR

fZmcc

mcc −

−=

ππ

ππ γ

(3.37)

where )(, fRc π can be referred to as in [71, 72] .

In particular, when WWW == 21 , (3.34) is reduced to the propagation constants of even-

and odd-modes, respectively, so,

)]()([)()()( 4321 fPjfPfPjfPfeo

ωωγ +±+= (3.38)

where )(1 fP , )(2 fP , )(3 fP and )(4 fP are given by

)]()()()([)()()()()( 121211112

121211111 fCfLfCfLfGfRfGfRfP +−+= ω ,

)()()()()()()()()( 12121212111111112 fLfGfCfRfLfGfCfRfP +++= ,

)]()()()([)()()()()( 111212112

111212113 fCfLfCfLfGfRfGfRfP +−+= ω ,

)()()()()()()()()( 11121112121112114 fLfGfCfRfLfGfCfRfP +++= . (3.39)

The characteristic impedances of )(00

fZ eo

are determined by

)(

)()()( 1

0 ffZfZ

fZe

me

γ+

= , )(

)()()( 1

0 ffZfZ

fZo

mo

γ−

= . (3.40)

When we choose 01211 == RR , 01211 == GG , and rewrite )()( 11 fLfLo = ,

)()( 11 fCfCo = , )()( 12 fLfLm = , )()( 12 fCfCm −= , (3.38) is reduced to that of the ideal

lossless case [71, 77]:


65

)]()()()([)()()()()( fCfLfCfLfCfLfCfLjjf moommmooeo

eo

−±−== ωβγ . (3.41)

At room temperature, Fig. 3.7(a)-(c) show the wideband attenuation constants versus

frequency for (a)symmetrical interconnects on slightly doped substrates for different

geometric and physical parameters. In Fig. 3.7(a) and (b), 221 == WW µm, and in Fig.

3.7(c), 41 =W µm and 22 =W µm. From these results, the following conclusions can be

drawn.

(a) At very low frequency, the losses are dominated by conductive loss of lines. The line

with smaller thickness will have larger DC resistance, which will result in a larger attenuation

constant at low frequency. To our best knowledge, in several previous works, the effects of

line thickness of interconnect have not been taken into account, such as in [73].

(b) With increasing frequency, the conductive loss in substrate will increase, which is

contributed by increasing shunt conduction currents and eddy currents. The conductive loss

in metal lines will also increase. As a result, the attenuation constants increase fast with

frequency.

(c) At higher frequency, the total loss is still dominated by the conductive losses of

metal lines and silicon substrate, and therefore, the attenuation constants always increase with

frequency.

(d) The )(, fc πα values of c- and π - modes at higher frequencies are much more

sensitive to the variation of line thickness than those at lower frequencies, and especially for

c- and odd-modes.

(e) For normal symmetrical coupled microstrip interconnects on low-loss microwave

polyimide or GaAs substrates, )( feα is usually smaller than )( foα , and


66

2

)()]()([)(2

)()()()()( 01211

0

1211 fZfGfGfZ

fRfRfff e

edecee

++

+=+= ααα (3.42)

2)()]()([

)(2)()()()()( 01211

0

1211 fZfGfGfZ

fRfRfff o

odocoo

−+

−=+= ααα . (3.43)

For coupled interconnects on the silicon substrate with 0.1=siσ S/m (Fig. 3.7(a)) or 10

S/m (Fig. 3.7(b)), using (3.42) and (3.43) (dash line), one cannot accurately capture the

attenuation constant of odd-mode at low frequencies. Only when the operating frequency is

above 1 GHz for slightly doped substrate, )( feα can be accurately captured using (3.42).

Physically, it can be predicted that the rise in temperature will cause an increase in

attenuation constant, which is mainly due to the decrease in electrical conductivity of metal

interconnects. As shown in Fig. 3.8, the parameters are chosen to be the same as those in Fig.

3.6, and the donor concentration of the n-type silicon substrate is set to be n = 15105× cm-3.

0 0 1 10Frequency(GHz)

0.0

0.4

0.8

1.2

1.6

Atte

nu. C

onst

ants

(dB/

mm

)

.01 .1 20

even

odd

t1=1um

1.5um

2um

t1=1um1.5um2um

W1=W2=S=tox=2um, D=500umσsi=1.0S/m

(a)


67


0.0

1.0

2.0

3.0

Atte

nu. C

onst

ants

(dB/

mm

)

.01 .1 20

even

odd

t1=1um1.5um

2um

t1=1um

1.5um

2um

W1=W2=S=tox=2um, D=500umσsi=10S/m

(b)


0.0

0.4

0.8

1.2

1.6

Atte

nu. C

onst

ants

(dB/

mm

)

.01 .1 20

c-mode

π-mode

t1=1um

1.5

2.0

t1=1um1.52.0

W1=4um, W2=S=tox=2um, D=500umσsi=1.0S/m

(c)

Fig. 3.7 Attenuation constants versus frequency for (a)symmetrical interconnects(dash line: based

on (3.42) and (3.43)): (a) 221 == WW µm, 0.1=siσ S/m; (b) 221 == WW µm, 10=siσ S/m;

and (c) 41 =W µm, 22 =W µm, 0.1=siσ S/m.


68

0.1 1 100

1

2

3

4

5 W 1 S W 2

t o x

D

t 1

ℵ

ℵ

o x

s i ℵS i= 1 0 0 0 0 S /m

ℵ

300K

400

300K

400

-modeπ

c-modeA

ttenu

.Con

stan

ts(d

B/m

m)

Frequency (GHz)

Fig. 3.8 Attenuation constants versus for asymmetrical interconnects with the same parameters as shown in Fig. 3.6.

Relatively, the effect of temperature rise on the attenuation constant of c-mode is more

pronounced than that of −π mode. However, as frequency increases, the πα will increases

much faster than cα . Similar phenomenon is also observed in Fig. 3.7(b) for even-mode in

symmetrical interconnects.

3.3.4 Slow-wave Factors

The slow-wave factors of c- and π -mode of asymmetrical interconnects at certain

temperature can be determined by:

0

,,

)()(

kf

fSWF cc

ππ

β= (3.44)

where πβ ,c can be obtained from (3.34), and 000 εμω=k . For symmetrical

configurations, (3.44) is reduced to

0

,,

)()(

kf

fSWF oeoe

β= (3.45)

Fig. 3.9 shows the oeSWF , versus frequency of interconnects with 0.1=siσ and 10 S/m,


69

221 === SWW µm (dotted lines), and 421 == WW µm, 2=S µm (dash lines), respectively.

It is shown that, for smaller value of siσ =1.0 S/m, eSWF and oSWF tend to be

frequency-independent at high frequencies, especially for even-mode. The value of eSWF

increases with increasing line width, whereas oSWF decreases. On the other hand, it is

obvious that both eSWF and oSWF decrease with increasing frequency. This is because at

higher frequencies the leakage of the electromagnetic field into silicon substrate will be more

significant, especially for the case of larger value of siσ , i.e. heavily doped substrate. At

room temperature, eSWF and oSWF versus siσ at frequencies f = 5, 10 and 20 GHz are

plotted in Fig. 3.10. It is obvious that eSWF is much more sensitive to the variation of

silicon conductivity than oSWF .

1 10Frequency(GHz)

2

3

4

5

6

Slow

Wav

e Fa

ctor

(SW

F)

20

even

odd

S=tox=2um, t1=1um, D=500umW1=W2=2um(dotted line), 4um(dash line)

1.0S/m

σsi=10S/m

Fig. 3.9 oeSWF , versus frequency for symmetrical interconnects for different line widths and silicon

conductivities with T = 300 K.


70

0 0 1 10 100 1000 10000Silicon conductivity (S/m)

2

3

4

5

Slow

Wav

e Fa

ctor

(SW

F)

.01 .1

even

odd

5GHz

10GHz

20GHz

5GHz

10GHz20GHz

W1=W2=2um, S=tox=2umt1=1um, D=500um

Fig. 3.10 oeSWF , versus silicon conductivity for symmetrical interconnects for different frequencies,

with T=300K.

3.4 Pulse Responses

Based on the calculated propagation constants of guided modes in the infinitely long

coupled (a)symmetrical interconnects, their pulse response characteristics, such as waveform

distortion, time delay and crosstalk, can be further characterized. Supposing that single

square pulse with a finite rise time is injected into the left line in Fig. 3.1(b), its Fourier

transform can be expressed by [78]

( )[ ] [ ]

3

111

21

)1(sinsin2)2

(sin

)1(80,~

ω

πτπτπτ

τ

τ

fqfqf

qqyfV

−⎥⎦⎤

⎢⎣⎡ −

×−

== (3.46)

where fπω 2= , while τ , 1τ , and q stand for three adjustable pulse parameters [78]. In

time domain, the voltage waveforms of the signal and sensing lines can be determined by


71

dfyff

tjyff

yfVtyv oeeo ]2

)()([exp]

2)()(

cosh[)0,(~),(1γγ

ωγγ +

−−

== ∫+∞

∞−

(3.47)

dfyff

tjyff

yfVtyv oeeo ]2

)()([exp]

2)()(

sinh[)0,(~),(2γγ

ωγγ +

−−

== ∫+∞

∞−

(3.48)

At T = 300 K, Fig. 3.11(a, b) show the propagated periodic pulse waveforms ),(1 tyv

and ),(2 tyv in the coupled interconnects recorded at y = 0.4, 0.6, 0.8, and 1 mm,

respectively. Waveform distortions of the signal at different positions can be easily observed.

The longer the wave propagats, the more attenuation the wave experiences. The wave delays

at different observed points were obvious due to the distributed effects of interconnects. The

pulse parameters are set to be 125=τ ps, 501 =τ ps, =q 0.05, and 10 5ττ = , where 0τ

is the input pulse spacing. Fig. 3.11(a, b) show that the attenuation of ),(1 tyv strongly

depends on line thickness, line conductivity and silicon conductivity. The maximum of

crosstalk ),((max)2 tyv captured numerically, can be reduced by choosing some geometric

parameters of the interconnects appropriately. For instance, as shown in Fig. 3.11(b)

( )421 mWW μ== , while the 2SiO thickness oxt increases from 2 to 4, 6 and 8 mμ , the

value of ),((max)2 tyv is captured at each time. By data fitting, it is found that

),1((max)2 tmmyv = =0.19455-0.00479 oxt (3.49)

and there is linear dependence between ),((max)2 tyv and oxt . The thicker insulator layer can

decouple the metal interconnect from the silicon substrate much effectively, and as a result,

the crosstalk will be reduced significantly.


72

0 400 800 1200 1600 2000Time(ps)

-0.2

0.0

0.2

0.4

0.6

0.8

V1(y

, t)

y=0.4mm0.6mm0.8mm1mm

W1=W2=4um, tox=2um, t1=S=1um, D=500um

σsi =10S/m

0 100 200 300 400 500 600Time(ps)

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

v1(y

, t)

W1=W2=4um, tox=2umt1=S=1um, D=500um

y=1mm

0.8mm

0.4mm

0.6mm

0.2mm

σsi=10S/m

(a)


73

0 400 800 1200 1600 2000Time(ps)

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

V2(y

, t)

y=1mm0.8mm0.4mm0.6mm

0 100 200 300 400 500 600Time(ps)

-0.2

-0.1

0.0

0.1

0.2

v2(y

, t)

W1=W2=4um, tox=2umt1=S=1um, D=500um

y=1mm

0.8mm

0.4mm0.6mm

0.2mm

σsi=10S/m

(b)

Fig. 3.11 Waveform distortion and crosstalk of a periodic square pulse propagating in coupled

symmetrical interconnects (a) ),(1 tyv and (b) ),(2 tyv .


74

0 100 200 300 400 500 600Time(ps)

-0.2

0.0

0.2

0.4

0.6

0.8

v1(y

=0.5

mm

, t) a

nd v

2(y=

0.5m

m, t

)

W1=W2=tox=2um, t1=1um, D=500umσsi =10S/m

S=1um2um3um4um

S=1um

2um

3um

4um

v1(y, t)

v2(y, t)

(a)

0 100 200 300 400 500 600Time(ps)

-0.2

0.0

0.2

0.4

0.6

v1(y

=1m

m, t

) and

v2(

y=1m

m, t

)

S=1um2um3um

4um

S=1um

2um3um

4um

v1(y, t)

v2(y, t)

(b)

Fig. 3.12 Square pulse responses in coupled symmetrical interconnects (a) y = 0.5 mm and (b) y = 1 mm.

Fig. 3.12(a) and (b) show the propagated pulse waveforms ),(1 tyv and ),(2 tyv at y

= 0.5 and 1 mm, as the spacing between two interconnects increases from S = 1, to 2, 3 and 4

µm gradually. Since the mutual coupling between the two interconnects is very sensitive to

the spacing S, the magnitude of ),(2 tyv is reduced significantly with increasing spacing S

from 1 to 4 µm, due to the reduction of capacitive coupling effects between the two

interconnects.


75

3.5 Average Power Handling Capabilities (APHC)

Fig. 3.13 Thermal models for coupled interconnects with the spacing

,max eoee WWS ≥ .

For silicon-based coupled interconnects, we can use peak and average power handling

capabilities (PHC) to characterize their performance thresholds. The peak value of PHC is

mainly determined by the electrical field breakdown strength of insulator layer and its

thickness. The APHC of coupled interconnects is determined by (a) conductive loss due to

their finite thickness and electrical conductivity; (b) edge current loss in silicon substrate; (c)

finite thermal conductivities of both insulator layer and silicon substrate; and (d) maximum

operating temperature that interconnects can tolerate. Hence, based on the above proposed

procedure and an appropriate thermal model, we can calculate the rise in temperature per

Watt absorbed by the interconnects, and finally to determine their APHC. It should be noted

that the thermal model proposed in [79-81] is only for single and coupled microstrip lines on

double-layer polyimide and GaAs substrates. Since there is a significant difference in

material properties between GaAs and silicon, the previous thermal model must be modified

to incorporate silicon. As shown in Fig. 3.13, an effective depth oxeffeff tDd −= )Re( is

introduced to characterize the heat dissipation in silicon substrate. Physically, as siσ

approaches zero and at lower frequency, this model will be reduced to that given in [81]. In

W S W

tox

D

t1

ox

si si

45 45 45 45o ooodeffHeat flow Heat flow


76

Fig. 3.13, the spacing S is assumed to be larger than the maximum of eeW or eoW [81],

where eeW and eoW are the effective widths of the two interconnects at low frequencies for

even and odd modes, respectively.

Following a similar procedure proposed in [81], the temperature rise per Watt only due to

the conductive loss of the two interconnects is calculated by

)()( fqfT cm =Δ⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧ ′

+′

∫ ∫+1 1

10 21

D dD

D

eff zdzdκκ

= )( fqc ∑=

2

1i i

iDκ

(3.50)

where 1κ and 2κ are the average thermal conductivities of 2SiO and silicon from room

temperature ( )ambT to the maximum temperature )150(max CT o≈ . It should be noted that the

effective depth effd will be reduced to 2D as siσ approaches to zero, and )( fqc in (3.50)

is determined by

])()(

[1152.0)(eo

co

ee

cec W

fW

ffq

αα+= (3.51)

where

eeoo

eo

eeoo SWFfZal

dDfW eff

⋅

+=

)]([Re][120

)(0

0

1π. (3.52)

The temperature rise only contributed by silicon substrate loss is calculated by

11)()(1152.0)()( r

Wf

WfrfqfT

eo

do

ee

dedd ⋅⎥

⎦

⎤⎢⎣

⎡+=⋅=Δ

αα (3.53)

where )( fdeα and )( fdoα are odd- and even-mode substrate attenuation constants, and

11

1

211

1 11 2 1 1 2 10

( 2 )1 1 1 1(1 ) (1 ) [ )2( ) 2( )

effD dDeff eff

effeff effD

d d DDz zr dz dz D dD D D d D dκ κ κ κ

+ ⎡ ⎤+′ ′′ ′= − + − = − + −⎢ ⎥

+ +⎢ ⎥⎣ ⎦∫ ∫

(3.54)


77

Therefore, the APHC of the coupled interconnects is determined by

)()()( max

fTfTTT

fPdm

ambav Δ+Δ

−= (3.55)

On the other hand, when the spacing S < ,min eoee WW , the situation becomes slightly

complicated, and )( fqc and )( fqd given above should be modified to be [81]:

])(2)(2

[1152.0)(SWf

SWf

fqeo

co

ee

cec +

++

=αα

(3.56)

and

⎥⎦

⎤⎢⎣

⎡+

++

=SWf

SWf

qeo

do

ee

ded

)(2)(21152.0

αα. (3.57)

Therefore, main steps to fast evaluate the frequency-dependent avP of coupled interconnects

on silicon substrate are summarized as follows:

Step 1: to characterize all frequency-dependent distributed parameters )],([ fR )],([ fL

)],([ fC and )]([ fG ;

Step 2: according to all distributed parameters obtained, to calculate conductive

attenuation constants )( fceco

α ( )( fcccπ

α ), substrate attenuation constants )( fdedo

α ( )( fdcdπ

α ),

characteristic impedances )(00

fZ eo

( )(00

fZ cπ

), slow wave factors )(00

fSWF eO

( )(00

fSWF cπ

),

and effective widths of the two interconnects eeeo

W ( ece

Wπ

);

Step 3: based on an appropriate thermal model, to calculate the rise in temperature of

interconnects;

Step 4: to calculate avP using (3.55).

In [65-68], the temperature rise of an interconnect due to Joule heating is characterized


78

based on the known current density. But in most cases, the current density is an unknown

quantity needed to be determined alternatively. The accuracy of the above procedure of fast

evaluating of the avP is directly related to the accuracies in the characterization of all

quantities in Step 1 and Step 2 and the established thermal model in Step 3 used to determine

the rise in temperature. For single interconnect on a double-layer polyimide and GaAs, the

accuracy of the predicted avP was verified indirectly, which can be referred to [79].

As an example, Fig. 3.14 shows the avP versus frequency for coupled interconnects,

with =siσ 10 S/m, 11 == tS µm, 4,221 == WW and 6 µm, respectively. Since S <

,min eoee WW , (3.56) and (3.57) are employed to calculate the rise in temperature, and the

values of 1κ and 2κ are chosen to be )/(0.11 CmW o=κ and )/(1342 CmW o=κ . It is

obvious that avP decreases with increasing operating frequency. At a given frequency, avP

can be enhanced significantly with increasing line width, which is similar to that reported in

[79-81] for polyimide and GaAs substrate. However, it must be understood that the way to

extract the frequency-dependent conductive and dielectric attenuation constants and the

thermal model to predict the temperature rise in [81] are not suitable for

metal-insulator-semiconductor interconnects, due to the strong effects resulted from the

silicon conductivity. Table 3.2 summarizes the possible methodologies to enhance the power

handling capabilities of coupled interconnects, where ToxR and TsiR are the thermal

resistances of 2SiO and silicon layers, respectively.


79

0 3 6 9 12 15Frequency(GHz)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Pav(

W)

W1=W2=2um

4um6um

S=t1=1um, tox=2um, D=500umσsi =10S/m , Tmax=150 Co

Fig. 3.14 avP versus frequency for coupled interconnects on silicon substrate for different line

widths.

Table 3.2 Effects of Variation in Different Parameters on the avP (VE: Very Effective; EL:

Effective, but Limited)

Parameters avP Parameters avP

↓f ↓⇒ )(, fdcα ↑ (VE) ↑1κ ↓⇒ ToxR ↑ (VE)

↑2,1W ↓⇒ )( fcα ; ↑↓⇒ )( fdα ↑ (EL) ↓siσ ↓⇒ )( fdα ↑ (EL)

↑1t ↓⇒ )( fcα ↑ (EL) ↑2κ ↓⇒ TsiR ↑ (VE)

↑1σ ↓⇒ )( fcα ↑ (EL) ↑D ↑ (EL)

↑S ↑ (EL) ↓ambT ↑ (VE)

↓oxt ↓⇒ ToxR ↑ (EL) ↑maxT ↑ (VE)


80

3.6 Test Structure Fabrication and Measurements

Copper interconnects with widths ranging from 150 nm to 1 µm, 300 nm thickness, and

lengths of 500 and 1000 µm were fabricated using damascene process on a film stack

consisting of 10 µm thick SiO2 and 50 nm of SiN deposited on 200 mm diameter, <100>

oriented p-Si substrate with resistivity of 10 Ω-cm. 50 nm thick SiN layer and 300 nm thick

SiO2 were deposited as passivation layers.

The test structures were designed in GSG (ground-signal-ground) configuration with

widely separated ground bars to suppress the excitation of CPW modes for RF

characterization. The schematic top views of the test structures for 0.15 µm coupled lines and

the TEM cross-sections are shown in Fig. 3.15. The spacing between the two lines was varied

as 1, 3 and 7 times of the line width.

Fig. 3.15 TEM cross-sections of coupled lines with line width and spacing of 0.15 µm. Inset shows schematic top view of GSG configuration.

On-wafer s-parameter measurements were carried out using Cascade Microtech Infinity

probes and HP8510C Network Analyzer over a frequency range from 50 MHz to 40 GHz

using line-reflect-reflect-match (LRRM) technique for calibration. The measured data was


81

de-embedded using open-dummy pad admittances. The time domain characterization of the

interconnects was carried out using an Agilent 81134A 3.36 GHz pulse generator and Agilent

DSO81204A 12 GHz oscilloscope.

3.7 Experimental Results and Discussions

km

Oxide

Si

Oxide

Rsi Csi

Cox

Cm

Rsim

Csim

Rsi Csi

Cox

R1

L1

R2

L2R1

R2

L2

Section 1

Section 2…..

Line 1

L1

Line 2

km

Oxide

Si

Oxide

Rsi Csi

Cox

Cm

Rsim

Csim

Rsi Csi

Cox

R1

L1

R2

L2R1

R2

L2

Section 1

Section 2…..

Line 1

L1

Line 2

Fig. 3.16 Equivalent circuit model of a coupled transmission line pair. These sections are cascaded to represent distributed nature of transmission line.

In Chapter 2, the frequency-independent RL ladder networks were successfully applied to

represent frequency-dependent behavior of a single on-chip interconnects due to skin,

proximity and substrate eddy currents effects. On the other hand, as indicated in previous

Chapters, Rsi and Csi can be safely treated as frequency-independent elements for the silicon


82

0 10 20 30 40-50

-40

-30

-20

-10

S12-Mag.-Measured S12-Mag.-Simulated S12-Ph.-Measured S12-Ph.-Simulated

Frequency (GHz)

S12

Mag

(dB

)

-1.0

-0.5

0.0

0.5

1.0

1.5(3)

(2)

(1)

(3)

(1)

(2)

S12 P

hase (radians)

(a)

0 10 20 30 40-8

-7

-6

-5

-4

-3

-2

-1

0 S11-Mag.-Measured S11-Mag.-Simulated S11-Ph.-Measured S11-Ph.-Simulated

Frequency (GHz)

S11

Mag

(dB

)

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

(3)(2)

(3)

(1)

(1)

(2)

S11 P

hase (radians)

(b)

Fig. 3.17 Measured and simulated s-parameters ((a) S11, and (b) S12) for 0.15µm wide, 0.30 µm thick and 500 µm long coupled lines. The edge to edge line spacing of 0.15, 0.45 and 1.05 µm are represented by (1), (2) and (3) respectively.

substrate with the resistivity of 10 Ω-cm. Thus, the model for coupled on-chip interconnects

shown in Fig. 3.1 has been modified to the one shown in Fig. 3.16. This modified model is


83

easily embedded in SPICE-like circuit simulators since all the elements in the model are

frequency-independent. Three and six sections of Fig. 3.16 are used to represent 500, 1000

µm long coupled lines, respectively.

The model parameters were calculated using the methods discussed in previous sections

and the asymptotic techniques described in Chapter 2. The models were further refined using

Levenberg-Marquardt optimization algorithm available in ICCAP to improve the accuracy of

the extracted parameters. Fig. 3.17 shows the measured and simulated transmission and

reflection s-parameters for a pair of coupled 0.15 µm wide single lines with a spacing of 0.15,

0.45 and 1.05 microns respectively. We found a good agreement between measured and

simulated s-parameters for longer lines of 1000 µm as well. The worst case rms error was less

than 10%.

The cross-talk noise in coupled lines was characterized in the time-domain. A pulse with

a period of 10 nS and width of 5 nS, a rise/fall time of 80 pS, and an amplitude of 1 volt was

applied to the aggressor line. The near end of the victim line was open ended, while its far end

is terminated in a 50-Ω resistance by an oscilloscope. Fig. 3.18 shows the simulated and

measured far-end of line noise signal at falling edge of pulse for 0.15 µm wide and 1000 µm

long coupled lines for two different lines spacing of 0.15 µm and 0.45 µm, respectively.

Again, we observe an excellent match validating the application of the model in the

time-domain circuit analysis.


84

4800 5000 5200 5400 5600

-80

-60

-40

-20

0

Am

plitu

de (m

V)

Time (pS)

L=1000μm W=0.15 μm Thickness=0.30 μm

S=0.15 μm Measured S=0.15 μm Simulated S=0.45 μm Measured S=0.45 μm Simulated

Fig. 3.18 Measured and simulated far-end-noise for a 0.15 µm wide and 1000 µm long coupled lines. The aggressor line input signal was a pulse with width of 5 nS, period of 10 nS, rise/fall time of 80 pS and amplitude of 1 V.

3.8 Summary

Several methodologies have been proposed for global modeling of on-chip coupled

symmetrical and asymmetrical interconnects, including their wideband frequency- and

temperature-dependent distributed parameters, conductive and dielectric attenuation

constants of even(c)- and odd )(π -modes, pulse waveform distortion and crosstalk, and

even average power handling capability (APHC). Compared with the previous studies on

coupled symmetrical interconnects, the present work has been focused on (a) asymmetrical

coupled configurations; (b) both electromagnetic and thermal characteristics; and (c) all

geometric and physical parameters of the configuration, in particular metal line thickness,

line conductivity, silicon conductivity and its thermal conductivity. Based on our numerical

examples, effective ways have been found to suppress silicon substrate loss and coupling

effects, reduce crosstalk between two interconnects, and enhance their power handling

capability. All these issues are of great importance in the implementation of coupled


85

symmetrical and asymmetrical interconnects in high-speed digital and high-frequency RF

circuits. A group of on-chip coupled interconnects was fabricated and measured in both the

frequency domain and the time domain. A good agreement between the measured and

modeled response over a wide frequency band up to 40 GHz is obtained. The model

excellently reproduces the cross-talk waveforms between coupled lines for different lengths,

widths and line spacing.

Chapter 4 Modeling and Design of On-Chip Inductors

86

Chapter 4. Modeling and Design of On-Chip Inductors

In the first part of this chapter, the analysis of frequency and temperature dependencies

of substrate eddy currents for single-ended and differential spiral inductors on a lossy

silicon substrate is carried out using the Greenhouse method incorporating with the complex

image method (CIM). A set of accurate closed-form expressions for calculating inductances

and substrate losses due to substrate eddy currents is derived. Based on these formulas, a

frequency-dependent eleven-element equivalent circuit model is proposed. The validity of

the model is established by comparing the simulated and measured results, and a good

agreement is found.

In the second part of this chapter, a novel vertical tapered solenoidal inductor is

designed, fabricated and analyzed. Due to its vertical tapered solenoidal structure, this

inductor can increase the peak quality factor frequency (fQmax) by 160% from 4.05 GHz to

10.55 GHz, and the self-resonance frequency (fsr) from 21.3 GHz to far beyond 25 GHz, as

compared to a traditional planar inductor. The self-shielding characteristic of this inductor

can eliminate the requirements of floating shields underneath the inductor. The performance


87

of the inductor is characterized at different temperatures.

4.1 Introduction

The high operating frequencies, at which deep sub-micron and nano-scale CMOS

devices are able to operate, have brought radio-frequency integrated circuits (RFICs) in the

realm of CMOS making the quality factor of the on-chip spiral inductors a focus of intensive

research. The quality factor of the on-chip inductor is limited by the losses due to the finite

conductivity of the metal and the conducting silicon substrate. Non-perfect metal wires used

to form spiral inductors cause ohmic loss due to the non-zero resistance at low frequencies.

Additionally the non-uniform current distribution in metal wires at high frequencies increases

the losses and degrades the quality factor of inductors. This loss mechanism has been

extensively studied as skin- and proximity-effects [23, 34, 82-91].

The electric field of the spiral inductor itself penetrates into the silicon substrate through

the underlying oxide leading to the substrate loss [23, 34, 82-91]. This loss is further aggravated

by the eddy currents induced by the time varying magnetic field due to the ac current in the

inductor spiral and becomes a source of further degradation of the inductor quality factor. This

loss is expected to increase with frequency. It may further decrease the inductance of a spiral

inductor with frequency. As the conductivity of the semiconductors strongly depends on

temperature, the substrate eddy currents are expected to be temperature-dependent as well.

There are a few reports on the characterization of substrate eddy current effects of

inductors and on-chip interconnects [10, 34, 91, 92]. For the sake of simplicity, Talwalkar et

al. treated a multi-turn inductor as the sum of two orthogonal coplanar transmission lines with

an effective width [34], while Huo et al. adopted a ladder RL network to approximate the


88

frequency-dependent loss and decrease in inductance due to the eddy currents in the substrate

[91]. Niknejad and Meyer [10] rigorously derived the vector potential of a current filament

over multi-layer conducting substrates in two-dimensions. Starting from Maxwell’s equation,

they presented a modified PEEC technique for modeling substrate eddy currents without

discretizing the silicon substrate.

The complex image method (CIM) incorporates the traditional PEEC technique to model

eddy currents in the Si substrate [92]. The aim of this technique is to speed up the simulation

without discretization of all the conductors in the problem space - a major drawback of the

traditional PEEC approach. However, no closed-form expressions are available for

calculation of the resistance and inductance caused by the substrate eddy current because

eddy currents are complex functions of the process and geometry parameters and they are

frequency and temperature dependent. The CIM was introduced by Wait and Spies in [19], to

calculate the electric field generated by a line-current above a ground. The CIM technique [19]

replaces a conducting substrate with finite thickness by an image current which has a

complex distance from the real conductor for evaluation of the electrical field. It is noted that

in the conventional method of image currents, for example in [93], the calculation of the

electrical field requires an infinite series of image currents to replace a magnetic substrate. In

its present form however the conventional method does not cater for the computation of eddy

currents. Over the past forty years, the CIM technique has been successfully implemented to

obtain solutions to the eddy current effects in the conductive earth surface [20] and to model

substrate skin effect for on-chip interconnects [9, 21], because this approach provides a

simple picture that enables one to write down the total field above a conductor immediately

without being involved in complex mathematical treatments.


89

In this chapter, the CIM technique is employed to study the substrate losses and

closed-form equations are derived for the calculation of frequency- and temperature-

dependent inductances and eddy-current losses in the substrate.

4.2 Greenhouse Method Incorporating with CIM Technique

According to the Greenhouse method [85, 94], the overall inductance of a spiral can be

computed by summing the self-inductance of each wire segment, and the positive and

negative mutual inductance among all pairs of wire segments. However, the Greenhouse

method does not take into account the effect of the substrate eddy currents.

Fig. 4.1 An image inductor with a complex distance D below the real inductor, and the arrows in the metal traces represent the current direction.

By using the CIM technique and based on the analysis in Chapter 2, it can be assumed that an

image spiral inductor is located below the real spiral inductor with a complex distance of D, as

shown in Fig. 4.1. The complex distance D is given by


90

2 oxD h d= + (4.1)

where oxh is the thickness of the oxide layer and d is given in (2.42) of Chapter 2 and

re-produced here,

(1 ) tanh[(1 ) ]d j j tδ δ= − + (4.2)

with the skin depth δ determined by 0

1f

δπ μ σ

= .

The image spiral inductor has the exact geometry with the real one but with the current flowing

in the opposite direction. To evaluate the overall inductance of an n-turn square spiral, it

involves 4n self-inductance terms, and the total self-inductance [85] [35] can be computed by

4 40

1 1

2ln( ) 0.52 3

n ni

s i ii i i

l w tL L lw t l

μπ= =

⎡ ⎤+= = + +⎢ ⎥+⎣ ⎦

∑ ∑ (4.3)

where w, t, and li represent the width, thickness, and length of the wire segment is in meters,

respectively, while Li denotes the wire segment’s self-inductance in Henry. We let l1 and l2

denote the lengths of two longest wire segments in the outermost turn, then the lengths of all

other segments [94] are determined by

2 1 1 ( 2)( )il l i w s− = − − + (4.4)

2 2 ( 1)( )il l i w s= − − + (4.5)

with 2i ≥ . Each wire segment in the real inductor has its counterpart segment of the same

geometry in the image inductor. We use li’ to name the wire segment in the image inductor

and count them similarly to those in the real inductor, i.e., from the longest segment in the


91

outmost turn to the shortest one in the inner turn. The length of the wire segment in the image

inductor li’ is exactly the same as its counterpart segment in the real inductor li. The mutual-

inductance between two parallel wires with lengths li and lj ( )i jl l≤ can be calculated by

[35]

[ ],2 2 ( ) ( )T i j iM M M l Mδ δ= = + − (4.6)

where 2 2

0( ) ln[ 1 ] 12

l l GMD GMDM l lGMD GMD l l

μπ

⎧ ⎫⎪ ⎪⎛ ⎞ ⎛ ⎞= + + − + +⎨ ⎬⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠⎪ ⎪⎩ ⎭

(4.7)

2 4 6 8 10

2 4 6 8 10exp(ln )12 60 168 360 660

w w w w wGMD dd d d d d

= − − − − − (4.8)

( ) / 2j il lδ = − . (4.9)

The units for d and l are in meters and M is in Henry. For an n-turn square spiral inductor, the

number of wire segment pairs generating positive mutual-inductance both in the real inductor

is

4 (2 1)N n N− − (4.10)

where [ ]N n= is the integer part of n catering to a possible quarter turn in square type of

structures. On the other hand, the number of complex positive mutual-inductance terms

caused by the pairs, one of which is in the image inductor, is given by

4 (2 ) 8 3( )(2 1)(4 4 1)N n N n N n N n N− + − − − − − . (4.11)

Therefore, the total number of negative mutual-inductance terms is

84 (4 2 1) ( )(2 1)(4 4 1) 43

N n N n N n N n N n− − + − − − − − + . (4.12)

Thus, the positive mutual-inductance generated only by the wire segments in the real inductor


92

is calculated by

( )[(4 ) 4]4( 1)

, 4 4 ,1 1

n in

R i i j i j ii j

M M M−−

+ + += =

= +∑ ∑[(4 ) 4]4( 1)

, 41 1

2n in

i i ji j

M−−

+= =

= ∑ ∑ (4.13)

where [ ]• gives the integer part of the expression in bracket. The distance between the

wire segment pair is obtained by

( )Rd j w s+ = ⋅ + . (4.14)

The positive mutual-inductance generated between one wire segment in the real inductor

and the other in the image inductor is determined by

( )[(4 2) 4]4 2

, 4 2 4 2,1 1

n in

I i i j i j ii j

M M M− +−

+ + − + −= =

= +∑ ∑[(4 2) 4]4 2

, 4 21 1

2n in

i i ji j

M− +−

+ −= =

= ∑ ∑ (4.15)

where the first subscript number i of M stands for the i-th wire segment in the real inductor,

and the second one i+4j-2 accounts for the (i+4j-2)-th wire segment in the image inductor.

The distance between them is

22

I Rd D d+ −= + (4.16)

where 2 oxD h d= + and Rd − is defined in (4.18). Similarly, the negative

mutual-inductance raised only between the wire segments in the real inductor is given by

[(4 2) 4]4 2

, 4 21 1

2n in

R i i ji j

M M− +−

− + −= =

= ∑ ∑ . (4.17)

The distance between the wire segment pair is

2

1

2 3 ( ), is odd;2

2 4 ( ), is even.2

R

i jl w s id

i jl w s i−

+ −⎧ − +⎪⎪= ⎨ + −⎪ − +⎪⎩

(4.18)


93

The negative mutual-inductance between one segment in the real inductor and the other

wire segment in the image one is calculated by

[(4 ) 4]4( 1) 4

, 4 ,1 1 1

2 2n in n

I i i j i ii j i

M M M−−

− += = =

= +∑ ∑ ∑ . (4.19)

The distance between the wire segments pair is

22

I Rd D d− += + (4.20)

where 2 oxD h d= + and Rd + is defined in (4.14). Thus, the total frequency-dependent

complex inductance of an n-turn square spiral inductor on silicon substrate can be computed

by

( )complex s R I R IL f L M M M M+ + − −= + + − − . (4.21)

Considering the complex equivalent inductance [9]

( ) ( ) IldAIjRL ∫ ⋅=Ψ=+ ωωω , (4.22)

we can obtain the frequency-dependent inductance of the on-chip inductor and the

equivalent resistance accounting for the substrate losses due to the eddy current as follows,

( ) Re[ ( )]complexL f L f= (4.23)

and ( ) 2 Im[ ( )]complexR f f L fπ= − . (4.24)

4.3 Temperature-Dependent Substrate Conductivity

For the tested inductor in this study, the substrate is p-type bulk silicon. The hole-mobility


94

at room temperature (300 )p Kμ is a function of dopant impurity concentration [95], and given

by equation (3.5). We assume that the silicon is extrinsic and the mobility is limited by the

lattice scattering at all temperatures of interest. Thus, the hole-mobility is determined by [96,

97]

3/ 2

( ) (300 ) 300p T p KTμ μ

−⎛ ⎞= ⋅⎜ ⎟⎝ ⎠

. (4.25)

As a result, the temperature-dependent silicon conductivity is given by [96]:

( ) ( )100T p TqNσ μ= (4.26)

where q =1.602×10-19C. This conductivity is used in the calculation of substrate skin depth

in (4.2).

4.4 Eleven-Element Equivalent Circuit Model of On-chip Inductors

In order to accurately characterize on-chip inductors, a frequency-dependent

eleven-element equivalent-circuit model is proposed, as shown in Fig. 4.2.

Fig. 4.2 Frequency-dependent eleven-element equivalent-circuit model of on-chip spiral inductors.


95

In Fig. 4.2, ( , )EL f T , ( , )ER f T and ( , )M f T represent frequency- and

temperature-dependent inductance, resistance and mutual inductance due to eddy currents in

the silicon substrate. Values of these three elements as well as ( )SL f accounting for the total

inductance of the spiral itself can be calculated by the method described above. ( )SR f

accounts for the resistance of an inductor and SC represents for the inter-wire and underpass

capacitance, whose values are obtained by using conventional formulas, e.g. in [85].

Capacitive losses due to the substrate are modeled by oxC , SiC and SiR . SiC can be calculated

by closed-form formulas in [45] and SiR is given by 0 SiSi

Si Si

RC

ε εσ

=⋅

, where Siε and Siσ are

the permittivity and conductivity of the silicon substrate. To accurately model oxC , a

semi-empirical formula accounting for fringing and proximity effects is introduced,

1.1601 ox

oxox

w lsCs w h

ε ε⎡ ⎤ ⋅ ⋅⎛ ⎞= −⎢ ⎥⎜ ⎟+⎝ ⎠⎢ ⎥⎣ ⎦ (4.27)

where s, w, and l denote spacing, width and total wire length of an inductor, and oxε and

oxh are the permittivity and the thickness of the oxide layer between the inductor and the

substrate.

4.5 Results and Discussions

4.5.1 Square Spiral Inductor

To verify the proposed model, a group of square spiral inductors were designed,

fabricated using a standard 0.18 μm RF CMOS technology with six metal layers, and

measured. The inductors were fabricated in metal layer M6 with a thickness of 2 μm. The

spiral trace width and spacing are equal to 6 μm and 2 μm, respectively. The top view is

shown in Fig. 4.3. The underpass line goes through the metal M5. The outer dimensions of


96

all inductors are fixed to be 140 μm × 140 μm. The on-wafer two-port S-parameters are

measured using an HP-8510C network analyzer and Cascade ground- signal- ground

(G-S-G) infinity probes.

0.1 1 100

5

10

Q

Frequency (GHz)

Measured n=4.5 Measured n=5.5 Model

Fig. 4.3 Quality factors for the fabricated inductors and the model with a die photograph of a 4.5-turn inductor fabricated in 0.18um CMOS technology.

Fig. 4.3 shows the measured and modeled quality factors Q=Im(Z11)/Re(Z11). To

demonstrate the scalability of our model, simulated quality factors for 4.5-turn and 5.5-turn

inductors are compared with measured results. A good agreement is found as shown in Fig.

4.3

In the π-type-based model of a single inductor, as shown in Fig. 4.2, the series branch

impedance can be extracted from measured S-parameters by [98]


97

12

1( ) 2 ( )( )eff effR f j fL f

Y fπ+ = − (4.28)

and

12 12( ) ( )m SY f Y f j Cω= + (4.29)

where 12 ( )mY f is converted from the de-embedded measured S-parameters. On the other

hand, the effective series resistance and inductance in our model can be easily calculated by

2 2

2 2 2( )eff S EE E

MR f R RR L

ωω

= ++

(4.30)

2 2

2 2 2( )eff S EE E

ML f L LR L

ωω

= −+

. (4.31)

The simulated effective inductances are compared with the measurement data, as shown in

Fig. 4.4, and a good agreement is obtained.

1 100.0

0.5

1.0

1.5

2.0

2.5

3.0

n=1.5

n=2.5

n=3.5

Indu

ctan

ce (n

H)

Frequency (GHz)

model measurement

Fig. 4.4 Simulated results compared with the measurement data. The thickness and conductivity of the silicon substrate is 500um and 10S/m, respectively.

As the substrate is relatively lightly doped in our case, the mutual coupling inductance


98

between the inductor and the substrate due to eddy currents only changes slightly with

frequency; therefore, the total inductance decreases slightly as well. In other words, due to

the small substrate conductivity, the complex distance does not vary significantly with

frequency, which makes all extracted inductances decrease marginally with frequency.

4.5.1.1 Variations in the Substrate Conductivity

To further illustrate the effect of eddy currents on the inductance, we calculated the

inductance of inductors with n= 2.5 and 5.5 fabricated on substrates with different

conductivities. As shown in Fig. 4.5, when σ=1,000 S/m, the inductances of both inductors

decrease slightly compared to those of σ=10 S/m, whereas inductances decrease considerably

with frequency when σ=10,000 S/m. This is because eddy currents in highly conductive

substrate flow much closer to the interface between the silicon and the oxide layer at high

frequencies and cause the larger mutual inductive coupling. In other words, the complex

distance reduces significantly with frequency in the case of highly conductive silicon

substrate enhancing the mutual coupling between the real and image inductors.

Mutual inductances between the inductor and the substrate due to eddy currents are

plotted as a function of frequency in Fig. 4.6, respectively, with σ=10,000 S/m assumed. The

high silicon conductivity will cause the magnetic field to concentrate to the top surface of the

substrate at higher frequencies, which further results in the reduction in the equivalent

complex distance. The mutual inductances, therefore, increase dramatically with frequency.

For example, the mutual inductance increases from nearly zero at very low frequency up

to 0.9 nH at 25 GHz for an inductor with n = 5.5, as shown in Fig. 4.6. This explains the

decrease of the total inductance with frequency shown in Fig. 4.5.


99

0 5 10 15 20 25

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

n=2.5

n=5.5In

duct

ance

(nH

)

Frequency (GHz)

σ=10S/m σ=1,000S/m σ=10,000S/m

Fig. 4.5 Inductances of the inductors on silicon substrates with different conductivities as a function of frequency.

0 5 10 15 20 250.0

0.2

0.4

0.6

0.8

1.0

Mut

ual I

nduc

tanc

e (n

H)

Frequency (GHz)

n=1.5 n=2.5 n=3.5 n=4.5 n=5.5

Fig. 4.6 The mutual inductance between the real and image inductors, with the substrate conductivity of 10,000 S/m. The spiral inductors have turns from 1.5-turn to 5.5-turn.


100

0 5 10 15 20 25

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Res

ista

nce

(Ω)

Frequency (GHz)

n=1.5 n=2.5 n=3.5 n=4.5 n=5.5

Fig. 4.7 The substrate resistances due to eddy currents of a group of inductors ( =σ 10 S/m).

Besides the negative mutual inductance coupling, the eddy currents add to the substrate

loss. The equivalent resistance RE, as shown in Fig. 4.2, is used to account for the substrate

loss due to eddy currents. Fig. 4.7 shows that the substrate loss increases with frequency. At

higher frequencies, the induced magnetic field will be concentrated closer to the top surface

of the substrate, leading to an increase in RE.

0 5 10 15 20 25

0

20

40

60

80

100

120

Res

ista

nce

(Ω)

Frequency (GHz)

σ=10S/m σ=1,000S/m σ=10,000S/m

Hollowed symbles: n=2.5Solid symbles: n=5.5

Fig. 4.8 The substrate resistance due to eddy currents with different substrate conductivities for n= 2.5 and 5.5, respectively.


101

The effect of substrate conductivity on substrate resistance due to eddy currents as well as

substrate losses is shown in Fig. 4.8. Our model correctly predicts that for different values of

σ , the 5.5-turn inductor always suffers heavier substrate loss than 2.5-turn inductor due to

eddy currents.

4.5.1.2 Temperature Effects

0 5 10 15 20 252.41007

2.41008

2.41009

2.41010

2.41011

2.41012

2.41013

2.41014

2.41015

2.41016

2.41017

2.41018

Indu

ctan

ce (n

H)

Frequency (GHz)

T=373K T=300K

(a)

0 5 10 15 20 25-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

T=373K

T=300K

Res

ista

nce

(Ω)

Frequency (GHz)

n=2.5 n=3.5

(b)

Fig. 4.9 (a) The inductances of an inductor with n = 3.5 at different temperatures, and (b) the substrate resistance due to eddy currents for inductors of n= 2.5 and 3.5-turn, respectively, and with σ=10 S/m at 300 K.


102

Fig. 4.9 shows the substrate resistances due to eddy currents of two inductors as a function

of frequency at temperatures T= 300 and 373 K, respectively. Since the value of σ decreases

with temperature, high temperature has a positive effect on inductor performance, i.e., as

temperature increases the inductance also increases and the eddy current loss in the substrate

decreases. Evidently, the inductance at 373 K in Fig. 4.9 is higher than that at 300 K, while

resistances due to the eddy current loss for 2.5-turn and 3.5-turn inductors at 373 K are

smaller than at 300 K, respectively, although these differences in both inductance and

resistance are small. On the other hand, for the heavily doped substrate, temperature variation

significantly affects the inductor performance, as shown in Fig. 4.10, where the substrate

dopant impurity concentration is 1.11×1019 cm-3, and σ=10,000 S/m at 300 K.

300 350 400 450 5001.85

1.90

1.95

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

Indu

ctan

ce (n

H)

Temperature (K)

f=1GHz f=10GHz f=20GHz

(a)

300 350 400 450 500-5

0

5

10

15

20

25

30

35

40

45

50

55

60

Temperature (K)


Res

ista

nce

(Ω)

(b)


103

300 350 400 450 500

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60


Mut

ual I

nduc

tanc

e (n

H)

Temperature (K)

(c)

Fig. 4.10 (a) The inductances, (b) the substrate resistance due to eddy currents, and (c) the mutual inductances between the inductor and substrate eddy currents for a 3.5-turn inductor as a function of

temperature at different frequencies, with 10, 000 /S mσ = at 300K.

4.5.2 Differential Inductor

Based on the CIM technique, the proposed modified Greenhouse algorithm can be easily

extended to differential inductors [99, 100]. To verify our method, an 8-turn symmetric

inductor was simulated, as shown in Fig. 4.11. The metal trace width and spacing are equal to

10 μm and 1.5 μm, respectively. The outer and inner dimensions are 240 μm × 240 μm and 60

μm × 60 μm, respectively.

Fig. 4.11 Layout of an 8-turn symmetric inductor.


104

For differential excitation of a symmetric inductor, the differential inductance can be

determined by [99, 100]

( ) Im( ) /diff diffL Zω ω= (4.32)

where diffZ is the differential impedance, defined as

11 22 12 21( ) ( ) ( ) ( ) ( )diffZ Z Z Z Zω ω ω ω ω= + − − ; (4.33)

and ijZ denotes the two-port impedances.

0 5 10 15 20 25

6

7

8

9

10

11

12

0 10 20

11.2050

11.2052

11.2054

11.2056

Indu

ctan

ce (n

H)

Freqency (GHz)

Diff

eren

tial I

nduc

tanc

e (n

H)

Frequency (GHz)

σ=10S/m σ=1,000S/m σ=10,000S/m

Fig. 4.12 Simulated inductances of an 8-turn differential inductor.

Fig. 4.12 shows the modeled differential inductance of the 8-turn differential inductor

with the different silicon substrate conductivities. The silicon conductivity also has a strong

effect on the differential inductance of the differential inductor, as well as on the substrate loss

due to eddy currents, which is shown in Fig. 4.13. For small values of σ, such as σ=10 and

σ=1000 S/m, the differential inductance decreases slightly with frequency; however, when

σ=1000 S/m it decreases dramatically. The loss due to the eddy current for substrates with a

high conductivity is much more serious than for substrates with a low conductivity. These


105

phenomena are caused by the decrease in complex depth versus frequency, which strengthens

the negative magnetic coupling between the real and image inductors. At the same time, the

decrease in the complex depth also concentrates the eddy at the top surface of the substrate.

0 5 10 15 20 250

50

100

150

200

250

300

350

400

450

0 10 200

2

4

6

Res

ista

nce

(Ω)

Frequency (GHz)

σ=10S/m σ=1000S/m σ=10000S/m

Fig. 4.13 The substrate resistance due to eddy currents of an 8-turn differential inductor with different substrate conductivities.

4.6 Design of A Vertical Tapered Solenoidal Inductor

Advanced CMOS process technologies cater for the applications of radio frequency

integrated circuits (RFICs) in the multi-tens of Gigahertz regime. Since these high operating

frequencies have made RFICs dependent on the quality of passive components, especially the

quality of inductors, on-chip inductors with high quality factor (Q-factor) and fsr have

become increasingly desirable. However, the Q-factor of an inductor is degraded by the

conductor loss due to the skin- and proximity-effects and the substrate loss due to the

electrical field leakage and eddy currents induced by the magnetic field. The fsr is limited by

the inter-wire and the underpass capacitance and the oxide capacitance. A high resistivity

silicon substrate [101] and a MEMS technique [102] were applied to reduce the substrate loss.


106

However, these techniques are not compatible with standard commercial CMOS technology.

Taking advantage of the available multilevel interconnects, one can shunt several metal layers

to achieve an effectively thicker metal and to reduce the conductor loss [103], while patterned

ground shields were introduced to prevent the electrical field from penetrating into the silicon

substrate and to reduce the substrate loss [24]. However, an increase in the Q-factor of an

on-chip inductor from these techniques comes at the expense of the reduction of fsr . In this

section, we propose a vertical tapered solenoid (VTS) inductor with a high fsr for RFIC

applications at high frequencies.

4.6.1 Theory and Formulation

Fig. 4.14 Lumped physical model of a vertical tapered solenoidal inductor and its simplified circuit model.

If we neglect the substrate eddy currents, the one port inductor model is shown in Fig. 4.14.

Here, the electrical characteristics of the spiral coil itself are represented by the inductance Ls,

the series resistance Rs, and the capacitance Cs. The capacitance Cs accounts for the sum of

inter-wire capacitances between adjacent turns and overlap capacitance between spiral and

underpass. Cp is a function of the oxide capacitance Cox, the silicon resistance Rsi, and the

silicon capacitance Csi . The Q-factor of inductor can be derived as follows [24]


107

( )

22

2

( )1 ( )

1p s s ps

s s ps sp s s s

R R C CLQ L C CR LR L R R

ω ωω

⎡ ⎤+= • • − − +⎢ ⎥

⎡ ⎤ ⎢ ⎥+ + ⎣ ⎦⎣ ⎦

(4.34)

where

( )2

2 2 2

1 Si ox Sip

ox Si ox

R C CR

C R Cω+

= + (4.35)

( )( )

2 2

22 2

1

1Si Si ox Si

p oxSi ox Si

R C C CC C

R C C

ω

ω

+ +=

+ +. (4.36)

The second term in Eq. (4.34) accounts for the energy dissipated in the lossy silicon

substrate, while the last term represents the self-resonance factor describing the reduction in

Q-factor until vanishing at the self-resonance frequency [24]. Hence, the fsr can be solved by

equating the last term in Eq. (4.34) to zero and it is thus given by

( )212

s s s psr

s s p

L R C Cf

L C Cπ− +

=+

. (4.37)

From (4.37), it is apparent that the fsr increases with a decrease in Cs. Thus, an inductor with

a smaller Cs will achieve a higher fsr.

4.6.2 Layout

Fig. 4.15 shows a VTS inductor with three turns. The outer-most turn of the VTS inductor

is fabricated on the top metal layer, while the innermost turn is fabricated on the bottom metal

layer. Every inner turn is on one layer lower than its adjacent outer turn, and each metal layer

consists of only one turn. For the 0.18 μm CMOS technology used in this chapter, we thus can

have a VTS inductor with a maximum of six turns. This VTS structure can significantly


108

reduce the inter-wire capacitance as well as the underpass capacitance. This decrease in the

parasitic capacitance of the inductor can increase its fsr, as indicated in (4.37).

(a)

(b)

Fig. 4.15 The 3-D view, and (b) the top-view of a 3-turn vertical tapered solenoidal inductor. Blue, yellow and green lines represent for M6, M5 and M4 layers, respectively. The oxide layers, silicon

substrate and test pads are not included.

At the same time, because the outermost turn with the longest wire length is fabricated on

the M6 layer with the lowest resistivity, this structure can effectively prevent the total


109

resistance of the inductor from increasing significantly due to the higher sheet resistance of

lower metal layers. This, in turn, can prohibit a heavy degradation in the Q-factor.

Additionally, the spacing between adjacent turns of a VTS inductor can be minimized to zero,

as shown in Fig. 4.15. Therefore, a VTS inductor may have the same inductance compared to

a traditional planar inductor but occupy a smaller area.

4.6.3 Measurement Results and Discussions

0 5 10 15 20 250

1

2

3

4

5

6

7

traditional inductor VTS inductor

Q fa

ctor

Frequency (GHz)

Fig. 4.16 Q-factors of a 2.2 nH traditional inductor and a 2.1 nH VTS inductor against frequency

The Q-factor of a 2.1 nH VTS inductor is compared with that of a 2.2 nH traditional planar

inductor in Fig. 4.16. Both of inductors were fabricated using a standard 0.18μm RF CMOS

process and measured using an HP-8510C network analyzer and Cascade Microtech ground-

signal- ground (G-S-G) probes with a temperature-controlled chuck. The de-embedding

technique and the definition of the Q-factor are introduced elsewhere [24]. The widths and

spacings for the VTS inductor and the traditional inductor are 6 μm and 2 μm, and 8 μm and

2 μm, respectively. Fig. 4.16 clearly shows that both fsr and fQmax of the VTS inductor


110

increases as compared to the traditional inductor, whereas the Q-factor decreases slightly. The

fQmax increases by 160% from 4.05 GHz to 10.55 GHz, while the fsr increases from 21.3 GHz

to far beyond 25 GHz. These improvements in fsr and fQmax make VTS inductors suitable for

application in RFIC blocks operating in the multi-tens of GHz regime.

0 5 10 15 20 250

1

2

3

4

5

6

7

Q F

acto

r

Frequency (GHz)

Unshielded Horseshoe Ladder

Fig. 4.17 Q-factors of 3-turn VTS inductors without the floating shielding, with the horseshoe

patterned shielding and with the ladder shielding against frequency

As mentioned earlier, the spacing of this 3-turn VTS inductor can be minimized to zero,

which increases the inductance by 7% at the cost of a 12% degradation in the Q-factor. This is

because the zero spacing can increase the mutual inductance between adjacent turns and the

self-inductance of an inductor with the fixed outer dimension, which in turn increases the

total inductance. However, it simultaneously increases the inter-wire capacitance and the

resistance, which degrades the Q-factor. Further, two 3-turn VTS inductors with horseshoe

and ladder floating shields [104] were fabricated and measured. Their Q-factors are compared

with a 3-turn VTS inductor without any floating shields in Fig. 4.17. Due to the VTS structure,

as seen in Fig. 4.15, the VTS inductor coil on each metal layer electrically shields the coil


111

above it from the coil below it. The bottom coil shields the whole inductor from the substrate.

As shown in Fig. 4.17, both floating shields do not improve the Q-factor of the VTS inductors.

Thus, it is no longer worthwhile for a VTS inductor to include floating shields. The electrical

performances of VTS inductors are also examined at different temperatures. As shown in Fig.

4.18, the Q-factors of both the 3-turn and 4-turn VTS inductors degrade at high temperatures

due to the increase in the series resistance of the inductors

0 5 10 15 20 250

1

2

3

4

5

6

7

n=3

n=4

T=20 oC T=60 oC

Qua

lity

Fact

or

Frequency (GHz)

Fig. 4.18 Q-factors of a 3-turn and a 4-turn VTS inductor under different temperatures against frequency

4.7 Summary

In the first part of this Chapter, the complex image method has been successfully adopted to

analyze inductive coupling between the conducting substrate and the spiral inductor as well as

the substrate loss of inductors due to eddy currents in the silicon substrate. Taking advantage of

the CIM technique, a set of closed-form formulas has been derived and used to establish a

frequency-dependent eleven-element equivalent circuit model. This model is fully scalable


112

since all the elements can be obtained from an analytic method or semi-empirical equations.

The simulated results using our model agree well with the measured data. It is demonstrated

that our model can accurately characterize eddy current effects on the performance of on-chip

spiral inductors. The eddy current due to the conductive substrate will cause a decrease in the

inductance and an increase in the substrate loss versuss frequency. Based on our simulated and

measured results, the eddy current effects can be safely treated as temperature-independent in

case of a lightly doped substrate, whereas the effects should be taken into account when the

substrate is highly doped, i.e. for a large value of σ. Using the same algorithm described in the

previous sections, except for the Grover’s formulas adopted here, other equations can be also

used to calculate self- and mutual-inductances of normal metal interconnects, such as those

presented in [36, 105]. In our study, this method has been applied to the differential inductors as

well.

In the second part of this Chapter, the VTS inductors have been designed, fabricated and

characterized experimentally. As compared to the traditional planar inductors, the VTS

inductor can increase fQmax by 160% from 4.05 GHz to 10.55 GHz, and fsr from 21.3 GHz to

far beyond 25 GHz, while the Q-factor only degrades slightly. Further, the self-shielding

effect of the VTS structure can avoid the requirements of floating shields underneath the

inductors and simplify the design. The temperature-dependent performance of the VTS

inductors was also investigated. Due to its high fQmax and fsr, the VTS inductor can be used at

multi-tens of Gigahertz or in broadband RF applications.

Chapter 5 Characterization of On-Chip Transformers with PGS

113

Chapter 5. Frequency-Thermal Characterization of On-Chip Transformers

With Patterned Ground Shields

Extensive studies on the performance of on-chip CMOS transformers with and without

patterned ground shields (PGS) at different temperatures are carried out in this chapter. These

transformers are fabricated using 0.18 μm RF CMOS processes and designed to have either

interleaved or center-tapped interleaved geometries, but with the same inner dimensions,

metal track widths, track spacings and silicon substrate. Based on the two-port S-parameters

measured at different temperatures, all performance parameters of these transformers, such as

frequency- and temperature-dependent maximum available gain ( maxG ), minimum noise

figure ( minNF ), quality factor ( 1Q ) of the primary or secondary coil, and power loss ( lossP ) are

characterized and compared. It is found that (a) the values of maxG and 1Q -factor usually

decrease with the temperature, however, there may be reverse temperature effects on both

maxG and 1Q -factor beyond certain frequency; (b) with the same geometric parameters,


114

interleaved transformers exhibit better low-frequency performance than center-tapped

interleaved transformers, whereas the center-tapped configurations possess lower values of

minNF at higher frequencies; and (c) with temperature rising, the degradation in performance

of the interleaved transformers can be effectively compensated by the implementation of a

PGS, while for center-tapped geometry, the shielding effectiveness of PGS on the

performance improvement is ineffective.

5.1 Introduction

Silicon monolithic transformers have been widely used in designs of on-chip impedance

matching, balun, low-noise amplifier feedback and other microwave and millimeter wave

components, for instance, those introduced in [106-109]. Based on different layouts, several

types of on-chip silicon transformers, and their modeling and optimization were studied in the

past a few years [86, 110-115]. Simburger et al. proposed two analytical transformer models

for both tapped and stacked geometries [107], and Niknejad and Meyer presented a

lumped-element equivalent circuit model for interleaved planar transformers [86]. More

recently, some significant progresses in the development of novel CMOS transformers have

been achieved, and among these, the optimized design of distributed active transformer [116],

30-100 GHz transformers fabricated using SiGe BiCMOS technology for millimeter-wave

integrated circuits [117], and a new compact model for monolithic transformers in

silicon-based RFICs [118] are good examples. Similar to silicon-based spiral inductors,

silicon-based transformers also suffer from serious power losses at high frequency. The loss

mechanisms can be summarized into five categories: (1) skin-effects, (2) proximity-effects,

(3) eddy-currents in the substrate, (4) shunt conduction current flowing in the substrate, and


115

(5) lateral conduction currents flowing in the substrate between the primary and secondary

coils. The first three mechanisms are due to time-varying magnetic fields whereas the

remaining two are caused by time-varying electric fields. The losses due to time-varying

magnetic fields can be efficiently reduced by increasing the electric conductivity of metals

and using slightly doping substrate with higher resistivity or implementing patterned

magnetic shields.

In order to reduce losses in silicon substrate due to time-varying electric field at a high

frequency, one practical way is to employ an appropriate patterned ground shield (PGS),

which provides a short terminal to the electric field leaking into the substrate. In some

previous studies [119-122] it was demonstrated that metal grid shields can be used to

effectively reduce mode attenuation of microstrip or coplanar interconnects. For

silicon-based spiral inductors, Yue and Wong first presented a PGS spiral inductor model in

1998 [24]. In 2002, Yim et al. further examined the effects of a PGS on the performance of

spiral inductors [123]. In particular, novel patterned trench isolation with a floating p/n

junction and floating metal poles were also implemented underneath reference spiral

inductors [32]. For spiral inductor cases, although the implementation of PGS may increase

the parasitic capacitance, it makes the design more independent of substrate dopant

concentrations and can reduce noise coupling into substrate. Therefore, an appropriate choice

of the embedding depth of PGS is very important in the effective implementation of PGS.

However, accurately characterizing frequency- and temperature-dependent PGS transformers

has not been well conducted yet. In the design of a transformer, there are multiple choices in

its configurations, such as interleaved, center-tapped interleaved, and even stacked

geometries. The performance parameters of a transformer, such as maximum available gain


116

( maxG ), self-resonance frequency, minimum noise figure ( minNF ), and power losses ( Ploss )

are directly related to its given configuration.

In this chapter, extensive studies are carried out to investigate on-chip (non) PGS

interleaved and center-tapped interleaved transformers at different temperatures, including

their frequency- and temperature-dependent maximum available gain ( maxG ), minimum noise

figure ( minNF ), power loss (Ploss), and quality factor ( 1Q ) of the primary or secondary coil.

5.2 Geometries of On-Chip PGS Transformers

(a) Interleaved PGS transformer: Design 1 (b) Center-taped interleaved PGS transformer: Design 2

(c) Cross-section view

Fig. 5.1 Top and cross-sectional views of on-chip interleaved (Design 1) and center-tapped interleaved

(Design 2) PGS transformers ( 1t = 2 µm, 2t =0.54 µm, 1D = 0.9 µm, H = 6.7 µm, and siD = 500 µm).


117

Fig. 5.1 (a) and (b) show the top view of an interleaved PGS transformer (Design 1) and a

center-tapped interleaved PGS transformer (Design 2) fabricated on a silicon substrate using

0.18 µm RFCMOS processes, with the same internal dimension of D = 60 µm, metal track

width of W = 10 µm, track spacing of S = 1.5 µm, and the same PGS implemented, as shown

Fig. 5.1(c) (where the width and spacing of the PGS metal bar are p pW S= = 0.4 µm). The

turn numbers of the primary and secondary coils are designed to be N = 3 and 4, respectively.

For comparison, a group of non-PGS transformers with the same geometric parameters D ,

W, S, N as its counterpart was also designed, fabricated and examined.

5.3 Modified Temperature-Dependent Equivalent-Circuit Models

5.3.1 Equivalent Circuit Model for an Interleaved Transformer

For an interleaved transformer with or without a PGS, its temperature-dependent small

signal equivalent circuit model can be obtained based on the circuit model given in [124], as

shown in Fig. 5.2. In Fig. 5.2(a), the capacitances 1oxC and 2oxC can be well treated as

temperature-independent elements, due to the constitutive characteristics of silicon oxide,

whereas the series self-resistances 1, 2 ( )m mR T of the primary and secondary coils, the silicon

substrate resistances 1, 2 ( )b bR T and shunt capacitances 1, 2 ( )b bC T are all sensitive to the

variation of temperature. For example, 1( )bC T and 2 ( )bC T decrease with temperature,

while 1( )bR T and 2 ( )bR T increase with temperature.

At a low frequency, the series equivalent self-inductances ( 1( )mL T and 2 ( )mL T ) and series

resistances ( 1( )mR T and 2 ( )mR T ) in Fig. 5.2(a) can be calculated based on the Z-parameters


118

converted from the measured S-parameters, i.e.,

1 11( ) Re[ ( )]mR T Z T= (5.1)

2 22( ) Re[ ( )]mR T Z T= (5.2)

111

Im[ ( )]( )mZ TL Tω

= (5.3)

222

Im[ ( )]( )mZ TL Tω

= . (5.4)

The coupling coefficient is defined as ( ) ( ) ( )r mT T j Tκ κ κ= + , and the mutual resistive ( )rκ

and reactive ( mκ ) coupling factors are calculated by [112]:

2

12

11 22

Re[ ( )]( )

Re[ ( )] Re[ ( )]r

Z TT

Z T Z Tκ =

⋅ (5.5)

212

11 22

Im[ ( )]( )

Im[ ( )] Im[ ( )]m

Z TT

Z T Z Tκ =

⋅ (5.6)

where Re( )⋅ and Im( )⋅ represent real and imaginary parts of the Z-parameters, respectively.

12C

1oxC 2oxC

2 ( )bC T2 ( )bR T1 ( )bC T 1 ( )bR T

1sC 2sC

κ

1 ( )mR T

1 ( )mL T 2 ( )mL T

2 ( )mR T

(a) Circuit model for an interleaved non-PGS transformer


119

κ

1 ( )eR T 2 ( )eR T

2 ( )eL T1 ( )eL T

(b) Simplified circuit model

Fig. 5.2 The small-signal circuit models for interleaved non-PGS transformer (Design 1)

As pointed out in [112], the mutual resistive factor rκ mainly accounts for the hybrid

effects of parasitic capacitances and eddy currents in the silicon substrate. The Q-factor for

primary and secondary coils can be evaluated by

11,221,2

11,22

Im ( )( )

Re ( )Z T

Q TZ T

⎡ ⎤⎣ ⎦=⎡ ⎤⎣ ⎦

(5.7)

while the self-resonance frequency of the transformer is defined at which 11Z or 22Z of the

device first becomes purely resistive. Especially, it is known that one of the important

performance indicators of a transformer is its maximum available gain, which is defined

[124] by:

( )221max

12

( )( ) 1( )

S TG T n nS T

= − − (5.8)

where

2 2 211 22

12 21

1 | ( ) | | ( ) | | |2 | ( ) ( ) |

S T S TnS T S T

− − + Δ= (5.9)

and

11 22 12 21( ) ( ) ( ) ( )S T S T S T S TΔ = − ; (5.10)


120

or [32] by

2max 1 2( )G x x x= + − + (5.11)

where

( ) ( ) ( )( ) ( )

211 22 12

2 212 12

Re ( ) Re ( ) Re ( )

Re ( ) Im ( )

Z T Z T Z Tx

Z T Z T

⋅ − ⎡ ⎤⎣ ⎦=+⎡ ⎤ ⎡ ⎤⎣ ⎦ ⎣ ⎦

. (5.12)

The minimum noise figure minNF of a transformer is defined [124] by

min max10log(1/ )NF G= . (5.13)

The circuit model of an interleaved non-PGS transformer (Design 1) is plotted in Fig.

5.2(a). At high frequencies, it can be further simplified as the form shown in Fig. 5.2(b),

where 1, 2 ( )e eR T , 1, 2 ( )e eL T , ( )MR T and ( )ML T represent the equivalent primary and

secondary resistances, inductances, and mutual resistances, inductances between them,

respectively (where i =1 and 2), and

2

22 2 2

[ ( )] ( )( )1 ( ) ( ) ( ) [ ( )]

i iei

i i i i

L T R TR TL T C T R T L T

ω

ω ω=

⎡ ⎤− +⎣ ⎦ (5.14)

2 2

22 2 2

( ) ( ) 1 ( ) ( )( )

1 ( ) ( ) ( ) [ ( )]i i i i

ei

i i i i

R T L T L T C TL T

L T C T R T L T

ω

ω ω

⎡ ⎤−⎣ ⎦=⎡ ⎤− +⎣ ⎦

(5.15)

where

1

2 2

( ) 1( )[ ( )] ( )

mii

mi mi sub

R TR TL T R T Rω

−⎡ ⎤

= +⎢ ⎥+⎣ ⎦ (5.16)

2 2 2

2

( ) ( )( )( )

mi mli

mi

R T L TL TL T

ωω

+= (5.17)

2 2

2 2 2 2

1 ( ) ( )( ) ( )

1 ( ) ( )oxi bi bi bi

i si oxioxi bi bi

C C T C R TC T C T C

C C R Tω

ω

⎡ ⎤+ +⎣ ⎦= ++ +

(5.18)


121

2

2 2 2

( )[ ( ) ( )]1( )( )

bi oxi bisub

bi oxi oxi

R T C T C TR TR T C Cω

+= + (5.19)

From Fig. 5.2, it can be found that the Q-factors of primary and secondary coils can be

determined by

( )( )

eii

ei

L TQR T

ω=

( )2

( ) ( )( ) ( ) ( ) ( ) 1 ( )

mi sub

mi sub mi mi mi

L T R TR T R T L T R T R T

ω

ω= ⋅

⎡ ⎤+ +⎣ ⎦

2 ( ) ( )1 ( ) ( )( )

mi imi i

mi

R T C T L T C TL T

ω⎛ ⎞

⋅ − −⎜ ⎟⎝ ⎠

=( )

( ) ⋅⋅ factorlosssubstrateTRTL

mi

miωself-resonance factor. (5.20)

(5.20) indicates that the substrate loss factor will approach unity as ( )subR T increases

infinitely. In other words, infinite value of ( )subR T may result in a high Q-factor of the

primary or secondary coil, and ( )subR T is determined by (5.19). As ( )biR T goes to zero or

infinitely, the ( )subR T will become infinite. This means that making the substrate either short

or open circuited can enhance the Q-factor. In this chapter, our methodology is to short the

substrate by inserting a PGS between the transformer and substrate so as to block electrical

fields from penetrating into the silicon substrate.

Fig. 5.3 The small-signal circuit models for an interleaved PGS transformer (Design 1)


122

For an interleaved PGS transformer (Design 1), its circuit model is plotted in Fig. 5.3.

In Fig. 5.3, there are two paths to the ground, i.e., through the PGS and the silicon substrate,

respectively. We can change the interconnects of ( )21 oxox CC , ( )21 bb CC , and ( )21 bb RR into a

shunt branch of a capacitance and a resistance. Similarly, we can also change ( )21 PGSPGS CC

and ( )21 PGSPGS RR into a similar shunt branch. Thus, a simplified circuit model will be

obtained, which can be easily compared to that in the non-PGS case. The element 1 2( )ox oxC C′ ′

in Fig. 5.3 is derived from the ( )21 PGSPGS CC , ( )21 oxox CC , ( )21 bb CC , ( )21 bb RR and ( )21 PGSPGS RR .

The 1 2( )b bR R′ ′ and 1 2( )b bC C′ ′ are obtained from the silicon substrate, so they include the

effects of PGSR and PGSC . Hence, the temperature coefficients of these elements for a PGS

transformer will not completely follow the characteristics of silicon substrate.

5.3.2 Equivalent Circuit Model for a Center-tapped Interleaved Transformer

For a non-PGS transformer of Design 2, its lumped-element equivalent circuit model is

shown in Fig. 5.4. The elements 1( )mR T ( 2 ( )mR T ) and 1( )mL T ( 2 ( )mL T ) represent the

series resistance and inductance of the primary (secondary) coil, respectively; three

capacitances 12C , 13C , and 23C are utilized to describe capacitive coupling effect between

primary and secondary coils; 3( )mR T and 3( )mL T are the series resistance and inductance

of the center-tapped metal track; ( )21 oxox CC , ( )21 bb CC and ( )21 bb RR have the same

meanings as indicated above. Following the similar procedure shown Fig. 5.3, the circuit

model for a PGS transformer of Design 2 can be also obtained but suppressed here. The center

T portion represents the low frequency model, while the remaining part represents the high

frequency model.


123

12C

1oxC 2oxC

2 ( )bC T2 ( )bR T1 ( )bC T 1 ( )bR T

κ1 ( )mR T 1 ( )mL T 2 ( )mL T 2 ( )mR T

3 ( )mL T

3 ( )mR T13C 23C

Fig. 5.4 The equivalent circuit model for a center-tapped interleaved non-PGS transformer (Design 2).

At low frequencies, the elements in Fig. 5.4 satisfy a set of equations as follows:

( ) ( ) ( )1 1 11 12m mR T j L T M T Z Zω+ + = −⎡ ⎤⎣ ⎦ (5.21)

( ) ( ) ( )2 2 22 12m mR T j L T M T Z Zω+ + = −⎡ ⎤⎣ ⎦ (5.22)

( ) ( )3 3 12m mR T j L T Zω+ = . (5.23)

Therefore, we have

( ) [ ]1 11 12RemR T Z Z= − , ( ) [ ]2 22 12RemR T Z Z= − (5.24)

( ) [ ]3 12RemR T Z= , ( ) [ ]3 12Im /mL T Z ω= (5.25)

Since the inductance and resistance depend on both physical and geometric parameters of the

structure, and due to the symmetry between the primary and the secondary windings, we can

assume that

( )( )

( )( )

1 1

2 2

m m

m m

L T R TL T R T

β= (5.26)

where the parameter β was given in [125] and its value can be determined using the curve

fitting technique based on the measured data. Then, we obtain


124

( ) [ ][ ] [ ]

[ ]11 12 11 121

11 12 22 12

Re ImRe Rem

Z Z Z ZL T

Z Z Z Zβ

β ω− −

=− − −

(5.27)

( ) [ ][ ] [ ]

[ ]22 12 11 122

11 12 22 12

Re ImRe Rem

Z Z Z ZL T

Z Z Z Zβ

β ω− −

=− − −

(5.28)

( ) [ ] ( )11 121

Imm

Z ZM T L T

ω−

= − . (5.29)

At high frequencies, the two-port Y-parameters of the model in Fig. 5.4 can be obtained from

the extrinsic Z-parameters, and

ex m sZ Z Z= − (5.30)

where mZ represents the Z-parameter obtained experimentally, and sZ is derived using Eqs.

(5.21)-(5.23). Then, the coupling capacitance C12 between Port 1 and Port 2 can be calculated

by

[ ]12 12Im /exC Y ω= . (5.31)

5.3.3 Temperature Effects

The temperature–dependent ( )miR T introduced in the previous section is due to the

change in electric conductivity ( )Tσ of metal coils with temperature rising. Over a

temperature range from 200 to 900 K, ( )Tσ of aluminum, gold and copper etc. can be

determined [69] by:

37

0( ) 10 n

nn

T a Tσ=

= ×∑ (S/m) (5.32)

with the coefficients, na (n = 0, …, 4), obtained using the curve fitting technique, and

summarized in Table 5.1. When the metal trace is made of an alloy, the coefficients vary for

different weight ratios of two or three types of pure metals. For example, if the alloy is made


125

of 95% aluminum and 5% copper in weight ratio, 0a = 8.90848, 1a = -0.02731, and

52 3 10a −= × (298 K 500T≤ ≤ K), based on (5.32), we can easily evaluate the total

temperature-dependent series resistances of the primary and secondary metal coils by

Table 5.1 Coefficients for Different Metals over a Temperature Range of 200 to 900 K

Metals a0 a1 a2 a3 a4

Aluminum 19.69998 -0.10727 0.00025 -2.5913×10-7 1.0016×10-10

Copper 29.1115 -0.15643 0.00037 -3.9347×10-7 1.5644×10-10

Gold 18.08394 -0.0872 0.00019 -1.9114×10-7 7.2377×10-11

Nickel 9.40567 -0.05317 0.00012 -1.2483×10-7 4.7908×10-11

Silver 26.56717 -0.13164 0.00029 -2.9549×10-7 1.1257×10-10

Tungsten 9.59998 -0.05123 0.00012 -1.2046×10-7 4.6332×10-11

, ,( ) ( ) ( )m i underpass coil iR T R T R T= + (5.33)

where

1 / ( )( )( ) ( )(1 )

underpassunderpass t T

LR T

T W T e δσ δ −≈−

(5.34)

2

,, / ( )( )

( ) ( )(1 )coil i

coil i t T

LR T

T W T e δσ δ −≈−

(5.35)

0

1( )( )

TT f

δπσ μ

= ; (5.36)

while underpassL and ,coil iL ( i =1 and 2) are the underpass lengths at the metal layer M5 and

the primary and secondary coils at the metal layer M6, respectively. Fig. 5.5 shows the

calculated ,m iR of the primary and secondary coils of transformers of Designs 1 and 2 at

temperatures of T = 298, 333 and 373 K, respectively. It is shown that the rising effect of

temperature on ( )miR T is easily observable, which will further increase the power loss of

metal coils. When the same inner empty dimension, metal track width, track spacing and turn

number are assumed, the total metal track length of the primary or secondary coil in Design 1


126

is slightly shorter than that in Design 2. Correspondingly, at a given frequency and a known

temperature the former series resistance of the primary coil is slightly smaller than that in

Design 2.

Fig. 5.5 The series resistances of the primary and secondary coils versus frequency for N = 4 of transformers of Design 1 and Design 2, respectively.

Obviously, the miR increases with temperature, and it can be described by a linear equation

as follows:

, 0 ,0 0 0 ,0 0( ) ( ) 1 ( )mp ms mp ms mp msR T R T C T T⎡ ⎤= + ⋅ −⎣ ⎦ (5.37)

where 0mpC and 0msC are two temperature coefficients of the primary and second coils,

respectively, and are determined by

,

0 ,0 00 ,0

0

( )1

( )mp ms

mp msmp ms

R TR T

CT T

⎡ ⎤−⎢ ⎥

⎢ ⎥⎣ ⎦=−

. (5.38)

From Fig. 5.5, it can be evaluated that the 0 ,0mp msC ≈ 0.0031/K at f = 1 GHz, while

0 ,0mp msC ≈ 0.0022/K at f = 10 GHz. If the above transformers are made of copper, 0 ,0mp msC ≈


127

0.0029/K at f = 1 GHz; while 0 ,0mp msC ≈ 0.0020/K at f = 10 GHz. Hence, 0 ,0mp msC is

also frequency-dependent, such a property has been usually neglected in most literature.

Fig. 5.6 Series inductances of the primary and secondary coils versus frequency for a transformer of N = 4.

Fig. 5.6 shows the extracted series inductances 1(333 )mL K and 2 (333 )mL K of Design 1

with N = 4 using (5.3) and (5.4), where the simulated result is also plotted for comparison

purpose.

Similar to (5.37), , ( )b iR T (where i = 1 and 2) can also be approximately described by

, , 0 0( ) ( ) 1 ( )b i b i osiR T R T C T T⎡ ⎤= + ⋅ −⎣ ⎦ (5.39)

where ,os iC is the temperature-coefficient of substrate resistance of silicon, and it was

experimentally demonstrated in [126] that the sheet resistance per square of the silicon

substrate increases linearly with temperature from a room temperature to as high as 250 o C .

Based on the Arora’s model, the temperature-dependent densities of carrier and mobility in

silicon substrate can be described [70] by:


128

exp fa i

qp N n

kTϕ⎛ ⎞

= = ⎜ ⎟⎝ ⎠

(5.40)

( ) ( ) ( )00

0 0 0

11.5ln2

g gf f

E T E TT kT TTT q T k T T

ϕ ϕ⎡ ⎤⎛ ⎞⎛ ⎞ ⎛ ⎞

= − + −⎢ ⎥⎜ ⎟⎜ ⎟ ⎜ ⎟⎢ ⎥⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎣ ⎦

(5.41)

( ) 41.206 2.73 10gE T T−= − × (5.42)

( )( )max min

0 min0

3001 /dN N α

μ μμ μ −= +

+ (5.43)

( ) ( )

3/ 2

300 300p T p KTμ μ

−⎛ ⎞= ⋅⎜ ⎟⎝ ⎠

(5.44)

where k is the Boltzmann constant, q is the unit electron charge in Coulomb, Nd is the total

dopant concentration in silicon, the parameters maxμ , minμ , dltμ , 0N , and α have

different values for different types of impurities [70], and the resistivity (1/ )si siρ σ= of

silicon is given by

0

1si qN

ρμ

= . (5.45)

The coefficient osiC in (5.39) is obtained by

1 siosi

si

dRCR dT

= . (5.46)

Therefore, the temperature-dependent resistivity of silicon is calculated and summarized

in Table 5.2, which is very sensitive to the change of temperature. Also,

Table 5.3Table 5.3 and Table 5.4 further summarize the extracted equivalent circuit

parameters shown in Fig. 5.2 and Fig. 5.3, for a transformer with N = 4 at different

temperatures. The following observations can be made. With respect to non-PGS transformer

of Design 1, the implementation of a PGS will result in increasing of 1bR′ and 2bR′ by a


129

factor of 1.4-2.5, while 1oxC′ and 2oxC′ will changed slightly. Thus, the increase of 1bR′ and

2bR′ can be useful for the enhancement of Q-factors of the primary and secondary coils.

Table 5.2 Silicon Resistivity Values at Different Temperatures

Temp(K) 250K 300K 350K 400K

ρsi=1 Ω·cm 0.645643 0.936659 1.27445 1.653792

ρsi=10 Ω·cm 7.034618 10.20539 13.8858 18.01893

ρsi=100 Ω·cm 70.8751 102.8212 139.902 181.5441

Table 5.3 Extracted Circuit Parameters of (non)PGS Transformer of Desgin 1 with N = 4

Temp(K) Rm1(Ω) Lm1(nH) Cs1(fF) C12(fF) Cox(fF) Cb1(fF) Rb1(Ω)

253 5.3 2.63 6.0 140 110 120 280

298 6.0 2.63 6.0 140 110 90 350

333 6.7 2.63 6.0 140 110 70 470

373 7.3 2.63 6.0 140 110 52 630

423 7.9 2.63 6.0 140 110 35 860

P G S

253 5.2 2.63 7.0 155 140 190 550

298 6.0 2.63 7.0 155 140 180 600

333 6.7 2.63 7.0 155 140 170 650

373 7.4 2.63 7.0 155 140 160 680

423 8.0 2.63 7.0 155 142 147 720

Table 5.4 Extracted Equivalent Circuit Parameters of Transformer of Design 2 with N = 4

Temp(K) Rm1(Ω) Lm1(nH) C12(fF) Cox1(fF) Cb1(fF) Rb1(Ω) Rm3(Ω) Lm3(nH)

253 5.5 2.7 85 110 130 130 0.54 0.12

298 6.1 2.7 85 110 95 180 0.60 0.12

333 6.8 2.7 85 110 74 230 0.67 0.12

373 7.5 2.7 85 110 55 300 0.76 0.12

423 8.1 2.7 85 110 40 400 0.82 0.13

The reactive coupling factor ( )m Tκ is not sensitive to the variation of temperature, and it


130

is about 0.75 for the transformers of Design 1 with or without PGS. It is found that ( )m Tκ ≈

0.73 in Design 2 with N = 4, which is slight smaller than its counterpart in Design 1

The corresponding temperature coefficients C0mp and C0ms in (5.38) for Design 1 are equal

to 33.4 10 / K−× approximately, which is close to that given as above at low frequencies.

The shunt substrate resistances Rb1 and Rb2 (where 1 2b bR R= ) increase with temperature,

and their temperature coefficient Cosi, as defined by (5.46), is equal to 1.01 210−× / K

approximately for silicon substrate, and for 1bR′ or 2bR′ its temperature coefficient is

extracted to be 1.08 310−× / K.

Fig. 5.7 shows the comparison of the real and imaginary parts of Z-parameters for PGS

and NPGS transformers (Design 1) with N = 4 at room temperature, respectively. An

Excellent agreement is obtained between the extracted and simulated Z-parameters for either

PGS or NPGS transformer over a wide frequency rang. It is interesting to note that as

frequency is below 3 GHz, the value of either Z11 or Z12 of the PGS transformer are almost

the same as its NPGS counterpart, due to negligible effect of PGS at low frequencies.

However, as frequency further increases, the values of both Z11 and Z12 of PGS transformer

increases much faster than those of NPGS case, due to strong capacitive effect resulted from

the PGS. The frequency corresponding to the peak value of Z11 12( )Z moves from 10 GHz

for the NPGS transformer to 8 GHz for the PGS case approximately.


131

0 5 10 15

0

200

400

600

800

1000

1200

NPGS

PGS

Frequency (GHz)

Real

(Z11

) and

Rea

l(Z12

)

Real(Z11_NPGS_E) Real(Z11_NPGS_M) Real(Z12_NPGS_E) Real(Z12_NPGS_M) Real(Z11_PGS_E) Real(Z11_PGS_M) Real(Z12_PGS_E) Real(Z12_PGS_M)

0 1 2 3 4 5

0

5

10

15

20

(a) Comparison of the real part of Z-parameters

0 5 10 15-15

-10

-5

0

5

10

15

NPGS

PGS

Imag

(Z11

) and

Imag

(Z12

)

Frequency (GHz)

Imag(Z11_NPGS_E) Imag(Z11_NPGS_M) Imag(Z12_NPGS_E) Imag(Z12_NPGS_M) Imag(Z11_PGS_E) Imag(Z11_PGS_M) Imag(Z12_PGS_E) Imag(Z12_PGS_M)

0 1 2 3 4 5

2

3

4

(b) Comparison of the imaginary part of Z-parameters (normalized by 1e-9)

Fig. 5.7 Comparison of the extracted and simulated Z-parameters.


132

0 2 4 6 8 10

0.0

0.3

0.6

0.9

Kr_NPGS T=298K Kr_PGS T=298K Kr_NPGS T=373K Kr_PGS T=373K Km_NPGS T=298K Km_PGS T=298K

Frequency (GHz)

Kr

0.0

0.4

0.8

1.2

1.6

Km

Fig. 5.8 Extracted rκ and mκ for transformer (Design 1) of N=4.

Fig. 5.8 shows the extracted mutual resistive and reactive coupling factors rκ and mκ for

transformer (Design 1) of N =4 at room temperature and 373 K. It is noted that mκ does not

change significantly at low frequencies, because it mainly accounts for the effect of magnetic

coupling. On the other hand, the resistive coupling factor rκ is much more sensitive to the

variation of frequency than that of mκ . Over the interested frequency range below 6 GHz, the

value of rκ of a PGS transformer is smaller than that of its non-PGS counterpart.

5.4 Fabrication and Measurements

To globally capture the electromagnetic-thermal characteristics of the above transformers

Design 1 and Design 2, four sets of samples are designed to have W = 10 µm, D = 60 µm, and

S = 1.5 µm, fabricated on a 10 cmΩ⋅ silicon substrate using 0.18 mμ RFCMOS processes,

including (1) non-PGS interleaved transformers, (2) non-PGS center-tapped transformers, (3)

interleaved transformers with a PGS at M1, and (4) center-tapped transformers with a PGS at

M1. The frequency- and temperature-dependent on-wafer two-port S-parameters are


133

respectively measured using an HP-8510C network analyzer, and Cascade Microtech ground-

signal- ground (G-S-G) probes with a temperature- controlled chuck. The chuck temperature

can be increased from 223K to as high as 473K. In order to reduce the effect of increasing

temperature on the probe station during measurements for different temperatures, two-time

calibrations at room- and higher-temperatures are done, respectively. For non-PGS

transformer, the open pad structure has been used for de-embedding; while for PGS

transformers, the open pad together with PGS was de-embedded. The maximum available

gain, minimum noise figure, power loss, and Q-factor of the primary or secondary coil of

transformers are further extracted and compared subsequently.

5.5 Extraction of Performance Parameters and Discussion

5.5.1 Maximum Available Gain (Gmax)

Fig. 5.9 shows the maxG of the interleaved transformers versus frequency at temperatures

T = 253, 298, 333, and 373 K, respectively. In Fig. 5.9, the temperature is increased from

253 to 298, 333 and 373 K gradually, and the following is shown.

1) As frequency increases, the value of maxG does not change monotonously, and at a

certain frequency represented by srf , maxG reaches its minimum;

2) Over the frequency range from 0.5 MHz to srf ≈ 8.4 GHz approximately in Fig. 5.9(a),

the maxG decreases with temperature. However, as frequency increases higher than

8.4 GHz, there is significant temperature reverse effect and maxG increases with

temperature;

3) Although the implementation of a PGS at M1 metal layer has little effect on the


134

maxima of maxG (N = 4), the curves of maxG in the PGS case at different temperatures

become much flat, as shown in Fig. 5.9(b). The decrease of maxG is mainly

contributed by the increase of the conductive losses due to imperfect metal coils.

Because the silicon conductivity decreases with temperature, the substrate losses will

be reduced at a higher temperature, which has a positive effect on maxG .

(a) Design 1 without a PGS

(b) Design 1 with a PGS at M1

Fig. 5.9 The maxG values of transformer (Design 1) with and without a PGS versus frequency at

different temperatures, respectively.

A comparison of the implementation of PGS on maxG is further demonstrated in Fig. 5.10


135

for a transformer (Design 2) with N = 4. In Fig. 5.10(a), similar reverse temperature effect is

observed, as shown in Fig. 5.9(a). As the frequency exceeds rsf ≈ 16.4 GHz, maxG increases

with temperature. On the other hand, it should be noted that the reverse frequency ( rsf ) for

Design 2 is much higher than that of Design 1.

(a) Design 2 without a PGS

(b) Design 2 with a PGS

Fig. 5.10 The maxG values of PGS and non-PGS transformers (Design 2) versus frequency at different

temperatures, respectively.

Since the transformers of Designs 1 and 2 are designed to have the same geometrical

parameters, i .e. D = 60 µm, W = 10 µm, and S = 1.5 µm, it is worthwhile to find out the

difference in terms of maxG versus frequency. Fig. 5.10 shows the maxG values of Designs 1

and 2 with N = 3 at T= 253 and 333K, respectively. As seen in Fig. 5.10, when the operating


136

frequency is lower than the cross-point frequency crf ≈ 5.25 GHz at T = 253 K, the maxG of

Design 1 is larger than that of Design 2. When the operating frequency further increases,

however, a reverse effect is observed and the maxG of Design 2 becomes larger than that of

Design 1. When T = 333K, crf ≈ 5.65 GHz. Hence, it can be concluded that at a high frequency,

stronger electromagnetic coupling between the primary and second coils in Design 2 will be

expected than that in Design 1; and for Design 2 without PGSs, similar phenomena can be

observed.

0 5 10 15 200

2

4

6

8

10

12empty dot: NPGS

solid dot: PGS

PGSinterleaved

N=3

NFm

in(d

B)

Frequency(GHz)

253K298K333K373K253K298K333K373K

Fig. 5.11 The minNF of a (non) PGS transformers of Design 1 versus frequency at different

temperatures

Since maxG and minNF can be derived from each other, we only give one example, as shown

in Fig. 5.11, to demonstrate the frequency-dependent characteristics of minNF of a (non)

PGS transformer Design 1 at different temperatures. It is obvious that minNF does not change

monotonously with frequency, which is different from that shown in [124]. This is because a

frequency range up to 20 GHz is considered here. The implementation of a PGS can improve

minNF , for example, minNF increases by 18-33% for N = 4 interleave case between 4 GHz to 6


137

GHz, which is not plotted here.

5.5.2 Q Factor

Based on Eq. (5.7), the frequency- and temperature-dependent 1Q -factor of the primary

coil of Design 1 with a PGS is extracted with N = 4, and the 1Q -factor of its non-PGS

counterpart is also given for comparison, as shown in Fig. 5.12 and Fig. 5.13.

For Design 1, it is observed that

1) Although the temperature rise from T = 253 to 333 K causes a significant decrease in

1maxQ , such negative temperature effects can be compensated, to some extent, using a

PGS with an appropriate embedding depth. It is seen that for PGS Design 1, the 1maxQ

at T = 373 K is still larger than that of 1maxQ at T = 298 K of non-PGS Design 1;

2) As indicated in [124], there are also reverse temperature effects, that is, as frequency

exceeds a certain frequency corresponding to the zero temperature-coefficient of

silicon resistances 1bR and 2bR , the 1Q factor increases with temperature. This is

because at higher frequencies the 1Q factor is dominated by the silicon substrate

resistances 1bR and 1bR , which exhibits positive temperature coefficient.

The relative enhancement in 1Q -factor is defined by:

( 1) ( )( ) 1max 1max1 ( )

1max

( ) ( )( )( )

M noren no

Q T Q TQ TQ T

−Δ = (5.47)

and in the case of N = 4, ( )1

renQΔ (T) = 33.3%, 26.2%, and 20.7% at T = 298, 333, and 373 K,

respectively. It is apparent that the decrease in 1Q -factor of Design 1 can be compensated,

due to the shielding effectiveness of PGS embedded at the metal layer of M1. However, in the

case of Design 2, there is only a slight increase in the curves of 1Q factor starts beyond the

frequency f=2.5 GHz approximately when the substrate resistance becomes more dominant.


138

Fig. 5.12 The 1Q -factors of the primary coil of a (non) PGS transformer of Design 1 versus frequency

at different temperatures

Fig. 5.13 The 1Q -factors of (non) PGS transformers of Designs 2 versus frequency at different

temperatures.


139

5.5.3 Power Loss

Fig. 5.14 shows the power loss Ploss of (non) PGS transformer of Design 1 versus

frequency at different temperatures, and Ploss is defined as:

2 211 221lossP S S= − − . (5.48)

Fig. 5.14 Power losses versus frequency for (non)PGS transformer of Design 1 at different temperatures

0 2 4 6 8 100.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

N=3

solid dot: NPGSempty dot: PGS

Plos

s

Frequency(GHz)

:253K:298K:333K:373K:253K:298K:333K:373K

Fig. 5.15 Power loss versus frequency for (non)PGS transformers of Design 2 at different temperatures


140

It is obvious that the implementation of PGS can reduce the power loss of transformer of

Design 1 because of its shielding effectiveness. For comparison, Fig. 5.15 shows the power

losses of (non)PGS transformer of Design 2 with N = 3 versus frequency at temperatures of T

= 253, 298, 333, and 373 K, respectively. It is observed that for transformers of Design 2, the

implementation of a PGS has little effect on the reduction of power loss.

5.6 Summary

Frequency-thermal characterization of on-chip transformers with and without patterned

ground shields (PGS) has been carried out in this chapter. These transformers are fabricated

using 0.18 mμ RFCMOS processes, where the same inner dimension, metal track width, track

spacing and silicon substrate are used. The above results demonstrate that there exist

significant differences in the performance parameters between interleaved and center-tapped

interleaved configurations. The maximum available gains of interleaved transformers at low

frequencies are higher than those of their center-tapped counterparts. But at higher

frequencies the situation will be reversed. In an environment of relatively high temperature,

the thermal effects on the performance degradation of transformers and even other passive

devices must be considered carefully. It should be also emphasized that in order to enhance

the shielding effectiveness of a PGS, its embedding depth must be chosen appropriately.

Chapter 6 Conclusions

Chapter 6. Conclusions

This research has focused on the modeling of on-chip interconnects, inductors and

transformers. Equivalent circuit models for these on-chip passive components have been

successfully established and validated in this thesis by comparing them with the experimental

results. This chapter first concludes this thesis and then points out possible directions for

future work.

6.1 Summary

Modeling of on-chip interconnects has been carried out in Chapters 2 and 3, while

methodologies of characterization of on-chip inductors and transformers have been

introduced and discussed in chapter 4 and 5.

In Chapter 2, a fully scalable and SPICE-compatible model for on-chip interconnects is

introduced. A frequency independent lumped element ladder network has been applied in this

model to approximate the frequency dependent behavior of on-chip interconnects. The values

of lumped elements in the series branch of the model are determined by only using the loop

impedance at very low and extremely high frequencies, respectively. The loop impedance of

on-chip interconnects is calculated by using modified loop based method. All the loss

Chapter 6 Conclusion

142

mechanisms, i.e., skin, proximity and substrate skin effects, are correctly treated in this model.

For the sake of simplicity, the complex image method (CIM) has been applied to characterize

the substrate skin effect caused by the induced eddy currents in the lossy silicon substrate.

Other elements are obtained by using analytical closed-form formulas. In addition, this model

also has the capability of estimating the impact of the metal dummy fills. Simulation results

by using this model are compared with the measuremental data. Good agreement is obtained

over a wide frequency range from DC up to 110 GHz. This indicates that this model can be

potentially used for the future nano scale CMOS technologies and millimeter wave CMOS

designs.

On-chip symmetrical and asymmetrical coupled interconnects have been analyzed in

Chapter 3. Their pulse waveform distortions, crosstalks and average power handling

capabilities have been investigated based on their wideband frequency- and

temperature-dependent distributed parameters. These distributed parameters can be easily

obtained from several extended closed-form formulas. Furthermore, an equivalent circuit

model for on-chip coupled interconnects is established. The validity of this model has been

examined by comparison of simulation results against measured S-parameters in frequency

domain and measured crosstalk noise in time domain. Good agreements are found in both

domains.

In Chapter 4, the CIM technique combined with the traditional Greenhouse approach has

been successfully applied to characterize substrate skin effect of on-chip inductors, and a set

of closed-form formulas has been derived based on this technique. With the help of this set of

formulas together with several other analytical equations, an eleven-element equivalent

circuit model has been introduced. Again, good agreements are found between the simulation


143

results and measured data. This inductor model shows the capability to model the substrate

skin effects at different temperatures. In the second part of this Chapter, the vertical tapered

solenoidal (VTS) inductors have been introduced and discussed. As compared to the

traditional planar inductors, the VTS inductor can increase fQmax by 160% from 4.05 GHz to

10.55 GHz, and fsr from 21.3 GHz to far beyond 25 GHz, while the Q-factor only degrades

slightly. Further, the self-shielding effect introduced by the VTS structure can avoid the

requirements of floating shields underneath the inductors and simplify the design. Due to its

high fQmax and fsr, the VTS inductor can be used at multi-tens of Gigahertz or in broadband

RF applications.

Interleaved and center-tapped interleaved transformer with and without patterned ground

shields (PGS) have been extensively studied in Chapter 5. The results show that interleaved

transformers exhibit better low-frequency performance but the center-tapped interleaved

transformers posses lower values of NFmin at higher frequencies. An appropriately embedding

depth of PGS is required for enhancement in the shielding effectiveness of a PGS.

Interestingly, the values of maxG and 1Q -factor increase with the temperature beyond a

certain frequency, though both maxG and 1Q -factor usually decrease with the temperature.

In today’s semiconductor industries, accurate modeling of circuit behaviors, including

parasitics, is crucial for first-time-right designs, because the mask cost increases dramatically,

which makes the cost of a re-design more expensive. Since the quality of on-chip passive

components limits the performance of mixed-signal and RF ICs, accurate and

SPICE-compatible models for on-chip passive component becomes increasingly important

for successful circuit designs. Thus, models of on-chip interconnects, inductors and

transformers provided in this thesis can be used in present and future mixed-signal IC and


144

RFIC designs.

6.2 Future Work

As transistors continue to scale to higher operating frequencies, the importance of

interconnects will also continue to escalate. Future active areas of research include i) accurate

layout parameter extraction tools, ii) hierarchy methodologies and models for full-chip

interconnects simulations, and iii) novel test structures to mimic real high speed digital and

mixed-signal ICs and to characterize the long range mutual inductive coupling and substrate

noise coupling.

Over the past decades, on-chip inductors and transformers have established themselves as

the standard components in mixed-signal and RFICs. They will continue to determine the

overall quality of circuits in the future. Promising areas of research include i)

inductors/transformers with novel structures fabricated by CMOS processes to achieve a high

quality factor as well as a high self-resonance frequency, ii) wideband, scalable and

SPICE-compatible models for on-chip inductors and transformers, iii) fixed models by using

fast and accurate extraction approaches to directly obtain models from experiment results,

and iv) new test structures and de-embedding technique, such as a four-port transformer test

structure and its corresponding de-embedding method.

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