modeling preemphasis using ibis

Modeling Gigabit Pre-Emphasis UsingIBIS [Driver Schedule]: Application Note

Product Version 16.0June 2007

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Modeling Gigabit Pre-Emphasis Using IBIS [Driver Schedule] Application Note

ContentsOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Modeling Gigabit Pre-emphasis using IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . 4Task 1: Understand IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Modeling Gigabit Pre-emphasis using IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . 4Task 1: Understand IBIS [Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Task 2: Schedule Main and Boost Drivers Using[Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Task 3: Test it in Allegro PCB SI/SigXplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

a. IBIS Model ds-2tap.ibs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12b. Translate to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143. Simulate in SigXp (DS_2tap.top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Task 2: Schedule Main and Boost Drivers Using[Driver Schedule] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Task 3: Test it in Allegro PCB SI/SigXplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

a. IBIS Model ds-2tap.ibs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12b. Translate to DML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143. Simulate in SigXp (DS_2tap.top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

June 2007 1 Product Version 16.0




Modeling Gigabit Pre-Emphasis UsingIBIS [Driver Schedule]: Application Note

The purpose of this application note is to describe how you use the IBIS [Driver Schedule]feature for pre-emphasis differential models, then simulate them in Allegro PCB SI.

You will benefit from this application note if you are a user of Allegro platform high-speedproducts, specifically Allegro PCB SI and SigXplorer, and are familiar with the I/O BufferInformation Specification (IBIS), Cadence Device Modeling Language (DML), and AllegroPCB SI ESPICE syntax.

___________________________________________________.

For additional information on the technology used in this application note, see:

“Modeling Pre-/de-emphasis Buffers with [Driver Schedule]” by Arpad Muranyi:www.eda.org/ibis/summits/jan05/muranyi.pdf

“IBIS can help model gigabit pre-emphasis” by Arpad Muranyi and Michael Mirmak:www.eet.com/news/latest/showArticle.jhtml?articleID=60300186

IBIS Specificationwww.eda.org/ibis

“How to build fast and accurate multi-gigabit transceiver models”www.cadence.com/webinars/webinars.aspx?xml=pcbmacromodeling

___________________________________________________



Overview

Serial differential buffers are increasingly used in today’s high-speed system designs. Tocombat interconnect losses and ISI effects, serial differential interface technologies such asSerial ATA and PCI Express typically use pre-emphasis to selectively boost their buffer outputand to increase margins. System designers need fast, accurate pre-emphasis modeling isneeded to analyze performance and prevent signal integrity problems before production.

IBIS—the I/O Buffer Information Specification— is commonly used in PCB system EDA tools.However, many view IBIS models as either too difficult to use or not up to the task of accuratepre-emphasis modeling.

This application note outlines how to use the IBIS [Driver Schedule] keyword to create simple,modular and accurate models of serial-differential buffer designs featuring the most commonform of pre-emphasis. Within the Cadence Allegro PCB SI environment, it will be simplytranslated into a DML MacroModel section and seamlessly used in the simulation.

Important

The files referred to in this application note are available for your use. You canaccess them at the following location in your installation hierarchy:

<install_dir>/doc/IBIS_DS_AN/examples

Modeling Gigabit Pre-emphasis using IBIS [DriverSchedule]

The [Driver Schedule] is designed for scheduling multi-driver efforts in IBIS. It is often usedin multi-stage drivers with such limitations as fixed delay schedules, pre-defined initial states,etc.

Pre-emphasis is a multi-stage driver effort. It often uses one main driver and one or moreboost drivers with delays. So, before starting work on [driver schedule], you must properlyprepare the main driver and boost drivers in IBIS, as depicted in Figure 1.



Figure -1 Prepare the Main Driver and Boost Drivers

The three major tasks associated with are:

1. Understand IBIS [Driver Schedule]

2. Schedule main and boost drivers using IBIS [Driver Schedule]

3. Test it in Allegro PCB SI/Signal Explorer

The balance of this application note covers each of these tasks in detail.

Task 1: Understand IBIS [Driver Schedule]

The [Driver Schedule] keyword description in the IBIS 4.1 Specification is:

Keyword: [Driver Schedule]

Required: No



Description: Describes the relative model switching sequencefor referenced models to produce a multi-stageddriver.

Usage Rules: The [Driver schedule] keyword establishes ahierarchical order between models and should beplaced under the [Model] which acts as the top-level model. The scheduled models are thenreferenced from the top-level model by the[Driver Schedule] keyword.

When a multi-staged buffer is modeled using the[Driver Schedule] keyword, all of its stages(including the first stage, or normal driver)have to be modeled as scheduled models.

If there is support for this feature in a EDAtool, the [Driver Schedule] keyword will causeit to use the [Pulldown], [Pulldown Reference],[Pullup], [Pullup Reference], [Voltage Range],[Ramp], [Rising Waveform] and [Falling Waveform]keywords from the scheduled models instead ofthe top-level model, according to the timingrelationships described in the [Driver Schedule]keyword. Consequently, the keywords in the abovelist will be ignored in the top-level model.Also, all other keywords not shown in the abovelist will be ignored in the scheduled model(s).

However, both the top-level and the scheduledmodel(s) have to be complete models, i.e., allof the required keywords must be present andfollow the syntactical rules.

For backwards compatibility reasons and for EDAtools which do not support multi-stagedswitching, the keywords in the above list can beused in the top-level [Model] to describe theoverall characteristics of the buffer as if itwas a composite model. It is not guaranteed,however, that such a top-level model will yieldthe same simulation results as a full multi-stage model. It is recommended that a “golden



waveform” for the device consisting of a [RisingWaveform] table and a [Falling Waveform] tablebe supplied in the top-level model to serve asa reference for validation.

Even though some of the keywords are ignored inthe scheduled model, it may still make sense insome cases to supply correct data with them. Onesuch situation would arise when a [Model] isused both as a regular top-level model as wellas a scheduled model.

The [Driver Schedule] table consists of fivecolumns. The first column contains the modelnames of other models that exists in the.isfile. The remaining four columns describedelays: Resoundingly, Rise_off_dly,Fall_on_dly, and Fall_off_dly. The t=0 time ofeach delay is the event when the EDA tool’sinternal pulse initiates a rising or fallingtransition. All specified delay values must beequal to or greater than 0. There are only fivevalid combinations in which these delay valuescan be defined:

1) Rise_on_dly with Fall_on_dly

2) Rise_off_dly with Fall_off_dly

3) Rise_on_dly with Rise_off_dly

4) Fall_on_dly with Fall_off_dly

5) All four delays defined(be careful about correct sequencing)

The four delay parameters have the meaning asdescribed below. (Note that this descriptionapplies to buffer types which have both pullupand pulldown structures. For those buffer typeswhich have only a pullup or pulldown structure,the description for the missing structure can beomitted.)



Rise_on_dly is the amount of time that elapsesfrom the internal simulator pulse initiating aRISING edge to the t = 0 time of the waveform orramp that turns the I-V table of the PULLUPdevice ON, and the t = 0 time of the waveform orramp that turns the I-V table of the PULLDOWNdevice OFF (if they were not already turned ONand OFF, respectively, by another event).

Rise_off_dly is the amount of time that elapsesfrom the internal simulator pulse initiating aRISING edge to the t = 0 time of the waveform orramp that turns the I-V table of the PULLUPdevice OFF, and the t = 0 time of the waveformor ramp that turns the I-V table of the PULLDOWNdevice ON (if they were not already turned ONand OFF, respectively, by another event).

Fall_on_dly is the amount of time that elapsesfrom the internal simulator pulse initiating aFALLING edge to the t = 0 time of the waveformor ramp that turns the I-V table of the PULLDOWNdevice ON, and the t = 0 time of the waveform orramp that turns the I-V table of the PULLUPdevice OFF (if they were not already turned ONand OFF, respectively, by another event).

Fall_off_dly is the amount of time that elapsesfrom the internal simulator pulse initiating aFALLING edge to the t = 0 time of the waveformor ramp that turns the I-V table of the PULLDOWNdevice OFF, and the t = 0 time of the waveformor ramp that turns the I-V table of the PULLUPdevice ON (if they were not already turned ONand OFF, respectively, by another event).

Note that some timing combinations may only bepossible if the two halves of a complementarybuffer are modeled separately as two open_*models.

Use ‘NA’ when no delay value is applicable. Foreach scheduled model the transition sequence



must be complete, i.e., the scheduled model mustreturn to its initial state.

No [Driver Schedule] table may reference a modelwhich itself has within it a [Driver Schedule]keyword.

To use the [Driver Schedule] keyword correctly, you must understand that [Driver Schedule]:

■ Works for a single instance of a cycle (Rising and Falling)

Example of a Full Cycle for a [Driver schedule]:

Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dlyX1 or NA X2 or NA X3 or NA X4 or NAFull cycle: down-up, up-down down-up-down-up, up-down-up-downsequencing for slow clock. (There is no over-clocking.)

■ Follows top-level [Model] Polarity Non-Inverting and Inverting modes (phasing in atransparent manner)

■ Relates to Rise or Fall edges of a Master Clock

■ Knows the initial state (High or Low) of the signal

■ Allows a single switch and one cycle simulation

The [Driver schedule] is based on knowing the initial state, as shown in Table 1.

Table -1 Initial State

DriverSchedule

States

Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dly Non-Invert Inverting

Xr NA Xf NA Low High

NA Xr NA Xf High Low

X1 X2 NA NA Low Low

X2 X1 NA NA High High

NA NA X1 X2 High High

NA NA X2 X1 Low Low

Xr1 Xr2 Xf2 Xf1 Low Low



Some examples of bad sequences in [Driver Schedule] are shown in Table 2:

Table -2 Bad Sequences in [Driver Schedule]

Note: You must use a complete cycle to create a correct model.

Task 2: Schedule Main and Boost Drivers Using[Driver Schedule]

a. Use the IBIS [Driver Schedule] keyword to tie together the elements of your pre-emphasis driver. [Driver Schedule] can activate or de activate IBIS models usingfixed values of delays from rising and/or falling edges in the buffer input stimuluspattern. Without [Driver Schedule], model users can only connect buffer models ina cumbersome wired-or fashion.

Do not use the same delay values for all buffer speeds or designs. For example, aSerial ATA Generation I buffer has a nominal eye width of 666.66 ps. The delay touse for the boost in a two-tap design is therefore 666.66 ps. Serial ATA GenerationII has a nominal eye width of 333.33 ps. To simulate a buffer running at Generation

Xr2 Xr1 Xf1 Xf2 High High

Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dly Reason

NA NA NA NA Unknown initialstate

Xr NA NA Xf rising-risingsequencing

NA Xr Xf NA falling-fallingsequencing

Xr1 Xr2 Xf1 Xf2 rising-falling-falling-risingsequencing

Xr2 Xr1 Xf2 Xf1 falling-rising-rising-fallingsequencing

DriverSchedule

States



II data rates requires you to edit the IBIS model [Driver Schedule] delay values. Also,make sure your main and boost IBIS [Model] V-T tables are shorter than theminimum target eye width to ensure that your buffer settles completely after eachtransition in simulation.

b. Model your buffer as multiple [Model] sections. In most of today’s two-tap bufferdesigns, a boost driver adds current to the output of a main driver after eachtransition of the input stimulus (the boost output is often some fraction of the mainoutput). Collect separate I-V and V-T table data for the main and boost sections ofyour design and generate an IBIS model for each one. Create a third top-level modeland add a [Driver Schedule] keyword section to it, referencing the main and boostbuffers.

Do not neglect buffer capacitance effects. Models using [Driver Schedule], per theIBIS specification, are only required to have valid C_comp (buffer capacitance) datain the top-level model.

Properly separate your main and boost stages when making their IBIS equivalents.It may be necessary to manually disable portions of the silicon buffers netlist ifcontrol bits do not allow this to be done externally.

c. Use [Driver Schedule] to provide logical control over your driveroutput. The [Driver Schedule] delay parameters control how buffer pullups andpulldowns turn on and off. You can therefore use [Driver Schedule] to invert youroutput relative to the input stimulus pattern by filling in only the turn off delays afterinput edges. For example, this syntax describes a simple inverter with no actualdelay added to the input stimulus.

[Driver Schedule]Model_name Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dlyinverter NA 0.0ns NA 0.0ns

d. Fill in the [Driver Schedule] delays based upon the bit duration of your interface. Toimplement two-tap pre-emphasis, we assume the boost buffer turns on in responseto the input stimulus pattern inverted and delayed by one bits duration. By combiningthe logical control capability of [Driver Schedule] with bit duration information, youcan achieve complex pre-emphasis switching effects. For example, here is thesyntax for a two-tap buffer with an eye width of 400 ps.

[Driver Schedule]Model_name Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dlymain 0.0ns NA 0.0ns NAboost NA 0.400ns NA 0.400ns



This buffers main section switches immediately after an input rising edge. Tools willinterpret the boost section delay format as inversion, while the 400 ps value providesthe one bit delay component. The same technique could be used to model additionaltaps, as needed.

e. Follow the specification rules in adding [Driver Schedule] to your IBIS files. [DriverSchedule] is used in a top-level buffer model containing C_comp (buffercapacitance) and clamp information for use by the tool. Other parts of the top-levelmodel are ignored in favor of the tables in the scheduled buffer.

f. Use the [Diff Pin] keyword to link the inverting and non-inverting parts of your buffer.Many EDA tools that support IBIS will permit you to use a single input pattern tostimulate serial-differential buffer designs if [Diff Pin] is present.

Task 3: Test it in Allegro PCB SI/SigXplorer

It is very important to test the results of tasks 1 and 2 in SI and/or SigXplorer and correlatewith the real device before you distribute or use it.

The following steps use an IBIS 2-tap pre-emphasis model (ds_2tap) as an example to showhow to test it in SigXplorer.

a. IBIS Model ds-2tap.ibsComponent Pin List:

[Component] Test

[Manufacturer] Cadence

[Package]

| typ min max

R_pkg 0.10Ohm 0.10Ohm 0.10Ohm

L_pkg 1.00nH 1.00nH 1.00nH

C_pkg 1.00pF 1.00pF 1.00pF

|**************************************************************************

[PIN] signal_name model_name R_pin L_pin C_pin

|

1 Vcc Power

2 GND GND

3 TX_P 2tap

4 TX_N 2tap

Differential Pairs:

[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max



3 4 NA 0 0 0

Model 2tap and Driver Schedule:

[Model] 2tap

Model_type Open_drain

|

Vmeas = 1.2

Vref = 1.5

Rref = 50

Cref = 0.0

|

| typ min max

|

C_comp 1pF 1pF 1pF

[Voltage Range] 1.500V 1.50V 1.5V

[Temperature Range] 60.0 110.0 -10.0

|

[Driver Schedule]

|

| Model_name Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dly

main 0.0ns NA 0.0ns NA

boost NA 0.400ns NA 0.400ns

|

Main Driver:

|***************************************************************************

[Model] main


|

Vmeas = 0.9

Vref = 1.5

Rref = 50

Cref = 0.0

|

| typ min max

|

C_comp 0pF 0pF 0pF



|

Boost Driver:

|***************************************************************************

|



[Model] boost


|

Vmeas = 1.4

Vref = 1.5

Rref = 50

Cref = 0.0

|

| typ min max

|

C_comp 0pF 0pF 0pF



|

b. Translate to DML

Use ibis2signoise to translate ds_2tap.ibs to DML. (ds_2tap.dml)

The following is the DML MacroModel section following translation:

(IbisIOCell

(“DS_2TAP_2tap”

(DelayMeasurementFixture

(C 0)

(R 50)

(Threshold

(maximum 1.200000e+000)

(minimum 1.200000e+000)

(typical 1.200000e+000))

(V 1.5))

(MacroModel

(NumberOfTerminals 7)

(Parameters

(Buffers

(DS_2TAP_2tap_BUFF “DS_2TAP_2tap”)

(T001_BUFF “DS_2TAP_main”)

(T002_BUFF “DS_2TAP_boost”))

(MinTypMaxParams

(MTMSUBCKT

(ftstype “PullDownVIC”)



(maximum “maximum”)

(minimum “minimum”)

(typical “typical”))))

(SubCircuits “.subckt DS_2TAP_2tap 1 2 3 4 5 6 7 ibis_file=TBD

+DS_2TAP_2tap_BUFF=TBD

+T001_BUFF=TBD

+T002_BUFF=TBD

+MTMSUBCKT=typical

* Sources for enabling/disabling the individual bdrvr IV/VT curves

von ON 0 1

voff OFF 0 0

* The main bdrvr, with PullUp and PullDown disabled.

* Output drive is supplied by the Driver Schedule bdrvrs below.

bdrvr_DS_2TAP_2tap 1 2 3 4 5 6 7 OFF OFF ON OFF file=ibis_filemodel=DS_2TAP_2tap_BUFF

* This will call the correct typical, minimum, or maximum subckt.

X_mintypmax 1 2 3 4 5 6 7 MTMSUBCKT

+DS_2TAP_2tap_BUFF=DS_2TAP_2tap_BUFF

+T001_BUFF=T001_BUFF

+T002_BUFF=T002_BUFF

+MTMSUBCKT=MTMSUBCKT

* Definition of the typical mode subckt.

.subckt typical 1 2 3 4 5 6 7 file=ibis_file

+DS_2TAP_2tap_BUFF=TBD

+T001_BUFF=TBD

+T002_BUFF=TBD

+MTMSUBCKT=typical

* Sources for enabling/disabling the individual bdrvr IV/VT curves

von ON 0 1

voff OFF 0 0

* [Driver Schedule] DS_2TAP_main 0.0ns NA 0.0ns NA

* No pullup required



* pulldown driver

bdrvr_T001_PD 1 2 3 T001_PD_in 5 6 7 OFF ON OFF OFF file=ibis_file model=T001_BUFFc_compX=0

.node_param T001_PD_in NAME=(name(2) T001_PD_in) PRINT

e_T001_PD_in T001_PD_in 3 pwl 4 3 delay=0.0000n

datapoints vv

1 1

0 0

end vv

* [Driver Schedule] DS_2TAP_boost NA 0.400ns NA 0.400ns

* No pullup required

* pulldown driver

bdrvr_T002_PD 1 2 3 T002_PD_in 5 6 7 OFF ON OFF OFF file=ibis_file model=T002_BUFFc_compX=0

.node_param T002_PD_in NAME=(name(2) T002_PD_in) PRINT

e_T002_PD_in T002_PD_in 3 pwl 4 3 delay=0.4000n

datapoints vv

1 0

0 1

end vv

.ends typical

3. Simulate in SigXp (DS_2tap.top)

Figures 2 through 4 illustrate the results of this process in SigXplorer and SigWave.



Figure -2



Figure -3



Figure -4

Summary

Gigabit pre-emphasis can be modeled using IBIS. Given an understanding of IBIS [DriverSchedule], a main driver and boost drivers can be scheduled correctly for pre-emphasisefforts.

Allegro PCB SI supports these IBIS models. It can perform analysis for pre-emphasis throughtopologies, nets, and boards.



Contributors

Donald Telian Technologist, Cadence Design System, IBIS Founder

Arpad Muranyi Sr. SI Engineer, Intel, IBIS Founder

Michael Mirmak Sr. SI Engineer, Intel, IBIS Chair 2003-2005

Lance Wang Sr. Member Technical Staff, Cadence Design Systems


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