MOSIS Chip Test Reportkxc104/class/cmpen411/13s/pj/... · MOSIS Chip Test Report John Zielinski...

MOSIS Chip Test Report

John Zielinski File: 'ReportV37P-CS89532JohnZielinski.doc'

CMPEN 411, Spring 2013, Homework Project 9 chip, 'Tiny Chip' fabricated through MOSIS program

Technology: 0.5um CMOS, ON Semiconductor

Project: 8bit RISC microcontroller, 32 word program, 8 data registers, 6 instructions, one 8 bit input port, one 8 bit output port, 32X16 RAM program memory - reprogrammable

MOSIS V37P-CS CHIP

Die size: 1584 X 1685 um

Package: Ceramic DIP40

Summary of Design Parameters:

Number of transistors: total = 8720 pmos = 3848 nmos = 4872

Layout size: total area = 427003.47 um2 X= 693.3 um Y = 615. 9um

Worst case delay time: Td = 17.5 nsec. Maximum clock cycle: Freq. = 112.612 MHz

AT2 design efficiency = 130769812.6875 um

2 * nsec

2 Hspice minimum time step (.hsp file): CLK = 2.22ns

Complete schematic design: completion = yes Complete schematic design verified with simulation: yes

Complete layout design: completion = yes Complete layout design verified with simulation: yes

Layout DRC error check passed: yes LVS check passed: yes

Top cell name: aaamicrotop

Final Project Report 1. Objective: Place the core of your RISC microcontroller into the PAD frame, and verify by simulating 2. Tasks: -Build pad frame schematic -Connect microcontroller core to pad frame -DRC/LVS check -Simulate microcontroller 3. Circuit/Block Diagrams: Package Diagram

Microcontroller core

Pad Frame Diagram

4. Schematic Designs and Simulations: Schematic of controller core and frame

Schematic Simulation

Program: 00000: MV 0,0 00001: MV# 8,3 00010: OUT 3 00011: MV# 7,6 00100: OUT 6 00101: MV 3,5 00110: ADD 6,5 00111: OUT 5 01000: IN 2 INPUT SET AT -1 01001: OUT 2

Program Running Program Loading

5. Layout Designs and Simulations: Pad Frame Layout

Layout Simulation

Program: 00000: MV 0,0 00001: MV# 8,3 00010: OUT 3 00011: MV# 7,6 00100: OUT 6 00101: MV 3,5 00110: ADD 6,5 00111: OUT 5 01000: IN 2 INPUT SET AT -1 01001: OUT 2

Program Running

Program Loading

7. Data Sheet/User's Guide:

Pin Name Pin Type Pin Description

output<7:0> output 7-bits output of data-path RAM

adat7 output output of adat7 for testing

sdat0 output output sdat0 for testing

idat0 output output idat0 for testing

pc0 output output pc0

pc4 Output output pc4

iaw<4:0> input 5-bits 5-bit address for program RAM

widat2<4:0> input 5-bits 5-bit opcode written to Program RAM

widat1<7:0> input 7-bits data written to program RAM. Also used as external

input

widat0<2:0> input 3-bits 3-bit address for dual-port RAM written to Program

RAM

wr input Write signal for program RAM

rb input reset ACTIVE LOW for PC

ckin input ck for PC and Control unit

ckbout output output for ckbout for testing

vdd! input POWER

gnd! input GROUND

8. Answers to Questions: For your microprocessor simulation, explain the instruction execution time. How do you measure the instruction execution time from the simulation result? Please explain. Instruction execution time starts at the address coming out of the PC and ends when the instruction completes. What is the worst case instruction execution time of your microprocessor? Please explain the worst case instruction execution time. The worst case execution time is the add/subtract instruction, where the carry has to propagate all the way to the end.

How fast can you repeat the clock signal CK while the program properly executing? 8.88ns. From the instruction execution simulation, list the delay times of each sub operations, which will be added to make up the one instruction execution cycle. Do for all 7 instructions. Which instruction is the fastest? Which instruction is the slowest? Why?

Input delay: between pc0(orange) and sdat0(top-blue) 9.56ns

Move delay: between pc0(orange) and sdat0(top-blue) 11.3ns

Move Immediate delay: between pc0(orange-top) ddat0(orange-bottom) 16.4ns

Output dealy: between pc0(orange) and output(green) 14.5ns

Subtract Delay: between pc0(orange-top) and ddat0(orange-bottom) 17.5ns

Add Delay: between pc0(orange-top) and ddat0(blue-bottom) 16.9ns

Fastest: Input Slowest: subtraction

Which component is the slowest?

The datapath is the slowest component . Why does it take so long? The largest signal delay is from the inputs of the add/sub unit to the carry out output. How can we make it faster? We can make the all the transistors in the carry out path bigger. What limits the maximum speed of operation? The carry out propagation limits maximum speed.

How many transistors are used in your microprocessor chip design? 8720.

Did you use static, dynamic, or pass transistor logic? Static in mostly everything, but the Progam RAM uses pass transistor logic

Are there any errors in schematic? No.

Is there an error in layout? No. Does your layout pass the DRC checking without errors? Yes.

Is there a miss match on the schematic versus layout? No. Does your design pass the LVS checking without errors? Yes.

What is the worst case output signal rise time, fall time, and delay time? All rise and fall times are going to be out the same because each pad is buffered with the same size inverters.

Rise Time : @1pF

Fall Time: @1pF

The worst case delay time is from which input to which output? From pc<4:0> to ddat Explain the signal path for the worst case delay time (this is called critical signal path)? Worst case delay time: T =17.5 nSec

What is the total layout height and width? X= 693.3 um Y=615.9 um What is the total layout area measured in um

2?

Area: A =427003.47 um

2

What is the AT

2 measure of your design?

AT

2 = 130769812.6875 um

2 nSec

2

9. Design Report Conclusion: After completing the 8-bit microcontroller, I have realized that I have a lot of extra room to expand and add several components. I would redesign the decoders so to improve rise time, enlarge the carry-out transistors to improve add/ sub speed. I would add a multiplier, jump instruction, and possibly a serial port for the 16-bit data input. Continue reporting the fabricated chip testing follows.

10. Testing Fabricated Chip: The testing environment chosen to test this chip can be broken up into physical and programmable layers. There are some factors that exist within each layer that may limit the accuracy and performance of the chip. Physical Layer: This chip was tested on a JAMECO breadboard seen below. This breadboard will suffice for functional level tests; however, breadboards can limit the speed and signal integrity and hinder true speed benchmarks of the chip. As part of next year’s improvement on the physical layer testing environment a PCB is being built for future chips that will improve the quality and reliability of both speed and signal integrity related tests. Also part of the physical layer are the LEDs. All LEDs on the board are tied to power through 220Ω-1kΩ resistors and are sinking though the chip outputs. This means that a binary ‘1’ at the output will result in turning the LED off, and a binary’0’ will result in the LED turning on.

The testing environment for the chip

Basically breadboard, LEDs, resistors, and

the HCS12 module.

Functional Test environment where

the first 3 sample programs were

tested

clkb

pc<0>

pc<4>

Idat1

0

sdat0

adat7

output

LEDs on input

The chip is hooked up to an APS12SLK module with a MC9S12C128 microprocessor through the J1 60 pin header on the module. Overall inputs of the chip are set and defined through ports a, b, and t. The connection is shown below.

Speed Test environment with

function generator and high speed

scope.

widat0<0>

widat0<1>

widat0<2> widat1<0>

widat1<1>

widat1<2>

widat1<3> widat1<4>

widat1<5>

widat1<6> widat1<7>

widat2<0>

widat2<1> widat2<2>

widat2<3> widat2<4>

iaw<0>

wr

iaw<1>

iaw<2> iaw<3>

iaw<4>

clock-in resetb

GND

VDD

ON TOP

ON BOTTOM

The first physical test functional test was to verify that the clock bar output would toggle on and off as the clock input was toggled. This was verified by applying 5V and 0V repeatedly to the clock in and observing an LED sinking to the inverted clock output.

RED is clock bar out YELLOW is clock in.

Notice how they are inverted as expected.

Test was run at 6 kHz signal is clean

Same test as above but at 510 kHz notice

the slight dispersion in the RED clock bar

out.

Same test as above but at 1 MHz notice the

slightly more dispersion on the LOWER clock

bar out.

This is the clock in on top of the clock out bar at 1MHz. When they are on top of each other shows a delay from

clock in to clock out of 12 µs.

Programmable Layer: This chip was programmed using the HCS12 assembly language. The main function of these assembly programs is to write the program to the chip. To make the chip code easily readable within the main loop of the HCS12 assembly code each instruction was written as a subroutine in the main loop, and every sample program is shown as the main loop of the HCS12 assembly. Below shows an assembly sample of what each instruction subroutine did: ;Programing subroutines

wrInstr

BSET PTT,%00000001;write bit high

BCLR PTT,%00000001;write bit low

RTS

incrPC

LDAA PTT

ABA ;incrementing PTT by 2 increments PC by 1 since PC address =

PTT<5:1>

STAA PTT

RTS

;Instructions subroutines

mv0t0 ;OP source

LDAA #%00000000 ;mv 000

STAA PORTB ;source dest

LDAA #%00000000 ;00000 000

STAA PORTA

JSR print_bin2ascii ;Print out each port to hyper terminal for every

instruction

JSR wrInstr

JSR incrPC

RTS

This is the setup when it was first verified

running sample program 1.

wr01t1 ;OP source

LDAA #%00100000 ;wr 000

STAA PORTB ;source dest

LDAA #%00001001 ;00001 001

STAA PORTA ;

JSR print_bin2ascii

JSR wrInstr

JSR incrPC

RTS

For debugging purposes, all the binary for every instruction is printed to the Hyper Terminal. Also clock and reset are available to toggle through Hyper Terminal after the HCS12 writes the program to the chip. The clock also has the additional option of either stepping with ‘space bar’, or running continuously at 510kHz with the ‘g’/’G’ key.

Sample Programs: Sample Program 1:

The first program was designed to verify that the chip was functional. The program wrote 0x00 to register 0 and 0xFF to register 1 and then preceded to alternate to output between register 0 and register 1. The goal was to see all 8 LEDs on the output flash. This goal was tough to reach, but eventually was met after the program was revised and the chip socket was put back into place after being slightly dislodged. This goal was met with the sample assembly below: *Note this is just the main loop not all code. mainLoop LDX #msgStart

JSR printmsg

ldaa #CR ; move the cursor to beginning of the line

jsr putchar ;Cariage Return/Enter key

ldaa #LF ; move the cursor to next line, Line Feed

jsr putchar

Here is a screenshot of the dev tool that was

running on the HCS12 to program and debug

the chip. The top displays the binary values

of all the output ports used on the HCS12 to

the hyper terminal while the program is

writing. After the DONE… to indicate the

program finished loading, you can input

values from the key board that control clock

and reset.

Port A holds lower 8 bits of 16 bit data Port B holds upper 8 bits of 16 bit data Port T holds 5 bit PROM Address

Toggle Reset high

Toggle Reset low

Step Clock

Clock started then halted

LDAA #%00000000 ; Load and set PC = 0

STAA PTT ;

JSR mv0t0 ; NOP for first instruction

JSR wr00t0 ; write 0x00 to reg[0]

JSR wrFFt1 ; write 0xFF to reg[1]

LDY out_cnt ;Points to loop constant ‘out_cnt’ in our case 0x0E

out_seq JSR out0 ;out register 0

JSR out1 ;out register 1

DEY

BNE out_seq

JSR out0 ;out register last instruction at PROM Address: 0x1F.

LDX #msgDone

JSR printmsg

Sample 1 Results To verify that this program ran correctly, the program was initially stepped through and the on/off sequence was observed on the LEDs. After LEDs were verified the clock was run continuously and the output below was observed.

Sample Program 2:

This second program verifies all 8 registers of the DPRAM by first writing incremental ‘1’s to each of the 8 registers then outputting each of the 8 registers. To verify this program is working the LEDs on the output should turn on one by one then turn off one by one. Here is the main loop of the HCS12 that writes the program.

;Start with NOP

JSR mv0t0 ;PROM Address:00

This is the some output from this program captured on the oscilloscope. Here the clock is in RED and one bit from the output is in YELLOW. It clearly takes two clock cycles to execute one instruction here being “out register 0” and “out register 1” with a value of 0x00 in register 0 and 0xFF in register 1.

;write to DPRAM

JSR wr01t0 ;PROM Address:01



JSR wr0Ft3 ;PROM Address:04




JSR wrFFt7 ;PROM Address:08

;turn on LED going up bits

out_seq JSR out0 ;PROM Address:09

JSR out1 ;PROM Address:0A

JSR out2 ;PROM Address:0B

JSR out3 ;PROM Address:0C

JSR out4 ;PROM Address:0D

JSR out5 ;PROM Address:0E

JSR out6 ;PROM Address:0F

JSR out7 ;PROM Address:10

;turn off LED going down bits








;turn on LED going up bits









Sample 2 Results As the second program ran the LEDs started blinking up and down as expected. Points of the sequence were not skipped therefore all 8 registers work. Sample 3 Program: This program turns on and off LEDs sequentially like Sample program two; however this time register 1 is the only register being output. This program verifies that the subtract and branch on carry functions work on the chip. The subtract and branch on carry in this program should work together as an unconditional branch. The main loop of the HCS12 assembly code used to write this program is as follows. ;WRITE1 and OUT1 with branch

;Start with NOP

JSR mv0t0 ;PROM Address:00

;write control branch regs


JSR wr07t7 ;PROM Address:02 ;branch back here

;Writing 1, outputing 1









JSR wr1Ft1 ;PROM Address:0B


JSR wr3Ft1 ;PROM Address:0D


JSR wr7Ft1 ;PROM Address:0F


JSR wrFFt1 ;PROM Address:11


;subtract generate carry, branch back neg 18

JSR sub6f7 ;PROM Address:13

JSR bcn18 ;PROM Address:14

;output reg 6 on error












Sample 3 Results This program ran as expected, the output was never 0x08 which was in register 6 so it appeared that the branch works. I also stepped through the program and used the PC output lights to verify the branch went to the right location. Sample Program 4 This program is the PWM program that was programmed through the HCS12. It was designed to test the standalone programming of the microcontroller this program will be used in the speed test, since the output can be performance can be deduced even at high speeds. This is the main loop of HCS12 assembly code. JSR mv0t0 ;PROM Address:00 ; NOP

JSR wr00t0 ;PROM Address:01 ; Write OFF register

JSR wrFFt2 ;PROM Address:02 ; Write ON register

JSR wr08t6 ;PROM Address:03 ; Main Loop

JSR out2 ;PROM Address:04 ; OUT 0xFF

JSR in4 ;PROM Address:05 ; Take Input

JSR wr08t3 ;PROM Address:06 ; Set PWM period =8

JSR sub4f3 ;PROM Address:07 ; Set PWM to input

JSR mv0t0 ;PROM Address:08 ;high cycle

JSR mv0t0 ;PROM Address:09 ;NOP

JSR mv0t0 ;PROM Address:0A ;NOP

JSR mv0t0 ;PROM Address:0B ;NOP

JSR mv0t0 ;PROM Address:0C ;NOP

JSR mv0t0 ;PROM Address:0D ;NOP

JSR mv0t0 ;PROM Address:0E ;NOP

JSR mv0t0 ;PROM Address:0F ;NOP









JSR add2t4 ;PROM Address:18 ;add neg1 to input

JSR bcn17 ;PROM Address:19 ;branch high cycle

JSR out0 ;PROM Address:1A ;out 0x00

JSR add2t3 ;PROM Address:1B ;low cycle

JSR bcn1 ;PROM Address:1C ;branch low cycle

JSR wr07t7 ;PROM Address:1D ;Set branch control reg

JSR sub6f7 ;PROM Address:1E ;Set carry bit

JSR bc4 ;PROM Address:1F ;branch Main Loop

Sample 4 Results This program was verified at 510kHz- 30MHz. To verify that the program was working at 510kHz, this program was fed a 3-bit input number to register 4 and it was observed that the lights dimmed when the 3-bit number was incremented, and also one output was hooked up to the oscilloscope and the output signal changed in pulse width as the number increased. Below is the full dim setting of our PWM.

After the program was verified at 510KHz, the PWM output was set to a 50% duty cycle and the clock was hooked up to a function generator. The clock signal was swept from 100kHz to 30MHz. It was observed that under 500kHz visible blinking occurred. As the frequency increased to the function generator max of 30MHz, a 50% duty cycle square wave was still observed on our oscilloscope.

Full dim PWM seen in YELLOW.

This test was run at 510 kHz.

Speed test set up running at

30MHz

30MHz Function Generator

100MHz Oscilloscope

Closer look at the board set up

BLACK BNC is O-scope and RED

BNC is the FCN generator

Test Conclusion Four out of the five chips ran the sample programs successfully. The one chip got damaged during testing and the power wire melted:

I am really glad that my chip worked. Building all these debugging tools was really difficult, but it really paid off in the end. Every year Dr. Choi is optimizing the debugging process so that the chips will become easier to debug and check. I hope my debugging tool will be used in future years to help future students debug their chips. I am happy that Dr. Choi is developing a PCB design just to test this chip. Students that have this could not only debug their chips faster, but also perform more accurate speed tests. My fellow undergrad David Schor has also built a working assembler that is now on github for the PSU Chip Lab microprocessor. This will allow students to write direct assembly for the microprocessors. Also David is developing a simulator environment for the microprocessor. You can follow his project here: https://github.com/PSU-ChipLab. Here are some pictures of the silicon courtesy of Kaige Sun from the Jackson's Electronics Research Group here at Penn State.

PWM keeping 50% duty cycle at

30MHz.

This is a close up of wires connected

the pads to the pin. Here you can

see the power wire is melted.

https://github.com/PSU-ChipLab

This is the whole die. You can

clearly see the PROM on the left,

DPRAM on the right, PC above

PROM, and output register above

the DPRAM.

Here is a closer picture of the

microprocessor core. You can see

the vertical bit slices of the DPRAM

to the right since metal 3 was not

used on the DPRAM.

PC output register

DPRAM PROM

Here is a close up of the DPRAM. In

addition to see the outline of the

transistors you can see individual

metal 2 lines running vertically and

metal 1 lines running horizontally.

Here is a close up of the PROM.

Since metal 3 was used extensively

in this component you cannot see

the lower layers well.

All chips received passed the full microcontroller operation, running PWM program, test except one chip which was damaged during the testing. We tested the chips up to 30MHz clock signal. We expect the chips will operate over 110MHz clocking. Maximum Speed Microcontroller Operation Test With full PWM program running, we plan to increase the clock frequency until the PWM program fails. We have not carried out this testing yet.

Conclusion This project was very successful, all except one of the received chips passed the test, fully functional. The maximum chip operation speed was not measured yet. We express our gratitude to MOSIS for the course chip fabrication.

Here is a close up of the PC and

output register. On the upper left of

the PC you can just make out the

gates of the transistors running

vertically.

PC output register

DPRAM

PROM

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