RRI Internal Technical Report – Library ref no.
MWA Digital Receiver: Backplane circuit and PCB lay-out
Authors: S. Madhavi, D. Anish RoshiAffiliation: Raman Research Institute, Sadashivanagar, Bangalore, India 560080
Date: September 11, 2008, (v1.0)Class: MWA: Digital Receiver
Abstract
This report gives the circuit schematic and PCB layout of the Backplane designed for the MWADigital Receiver.
1 Backplane Description
The digital receiver consists of two ADFB (analog to digital converter filter bank) boards and anAgFo (Data aggregation and formatting) board. These three boards are plugged into a backplane(see Fig. 1), which provides the interconnection between the ADFB and AgFo boards.
The Backplane is an 8 layer PCB of size 263 mm x 285 mm. The data and the clock signals fromthe ADFB cards are in the form of LVDS. The high speed routing constraints such as (a) similarlengths for the LVDS (the LVDS 2.5 V is used for the design) PCB trace pairs, (b) separation andtrace thickness adjusted for 100 ohms differential impedance and (c) smooth bending of the tracesare considered during the design. The Backplane also distributes the 165 MHz FPGA clock and thesynchronization signal SCTN, both in LVDS format. A jumper selection is provided to select thesource of the FPGA clock and SCTN – they can either be connected from the AgFo card or froman external LVDS source through dual SMA connectors. For the interim software correlator forthe 32T operations, the AgFo output data is provided at the Backplane, which can be connectedto the VSIB data acquisition system. This feature is also useful for the initial testing of the digitalreceiver at the lab.
The circuit schematic of the Backplane is given in Appendix A. Appendix B gives the PCBlayout files.
Acknowledgement
We thank Kamini, Gopala Krishna, Srivani and Deepak for going through the circuit before thePCB layout was finalized and Wences Laus for helping in the initial testing of the backplane. Wealso thank other RAL staff members who helped us during the design of the backplane PCB. Weacknowledge Prabu’s effort in making a decision in the absence of DAR for populating the prototypeboard, which was made with wrong hole tolerance for the press-fit connector. DAR acknowledgesA. A. Deshpande’s help in overseeing the MWA lab activities during his absence.
1
Figure 1: (Left) Picture of the Digital Receiver under test at the Radio Astronomy Laboratory,RRI, Bangalore. The two ADFB boards and an AgFo board are marked on the picture. (Right)The three boards are plugged in to a Backplane. The Backplane provides the interconnectionbetween the boards as well as the distribution of the clock and synchronization signal.
Reference
Briggs, F., 2007, February 25, MWA Knowledge TreeRoshi, D. A., 2007, June 5, MWA Knowledge Tree
2
Appendix A : Backplane Circuit Schematic
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LV30_PLV30_N
LV39_PLV39_N
LV27_PLV27_N
LV25_PLV25_N
LV21_PLV21_N
LV28_PLV28_N
LV26_PLV26_N
LV22_PLV22_N
LV13_PLV13_N
LV10_PLV10_N
LV5_PLV5_N
LV2_PLV2_N
LV14_PLV14_N
LV9_PLV9_N
LV1_PLV1_N
LV52_PLV52_N
LV54_PLV54_N
LV56_PLV56_N
LV58_PLV58_N
LV51_PLV51_N
LV53_PLV53_N
LV55_PLV55_N
LV47_PLV47_N
LV24_PLV24_N
LV20_PLV20_N
LV18_PLV18_N
LV16_PLV16_N
LV38_PLV38_N
LV23_PLV23_N
LV19_PLV19_N
LV45_PLV45_N
LV41_PLV41_N
LV40_PLV40_N
LV48_PLV48_N
LV43_PLV43_N
LV12_PLV12_N
LV8_PLV8_N
LV7_PLV7_N
LV3_PLV3_N
LV15_PLV15_N
LV11_PLV11_N
LV4_PLV4_N
LV42_PLV42_N
LV62_PLV62_N
LV70_PLV70_N
LV72_PLV72_N
LV57_PLV57_N
LV66_PLV66_N
LV68_PLV68_N
LV71_PLV71_N
D1_B_DACLKPD1_B_DACLKN
C1_B_DACLKPC1_B_DACLKN
B1_B_DACLKPB1_B_DACLKN
A1_B_DACLKPA1_B_DACLKN
D2_B_DACLKPD2_B_DACLKN
C2_B_DACLKPC2_B_DACLKN
B2_B_DACLKPB2_B_DACLKN
A2_B_DACLKPA2_B_DACLKN
LV67_PLV67_N
D1_B_SCTN_P
D2_B_SCTN_N
C2_B_SCTN_PC2_B_SCTN_N
B2_B_SCTN_PB2_B_SCTN_N
C1_B_SCTN_P
A2_B_SCTN_P
C1_B_SCTN_N
A2_B_SCTN_N
B1_B_SCTN_P
LV69_P
B1_B_SCTN_N
A1_B_SCTN_N
D1_B_SCTN_N
D2_B_SCTN_P
LV78_N
LV78_P
C_SEL
LV29_NLV29_P LV30_P
LV30_N
LV27_PLV27_N
LV25_PLV25_N
LV21_PLV21_N
LV13_NLV13_P
LV76_PLV76_N
LV14_NLV14_P
LV18_NLV18_P
LV22_PLV22_N
LV26_PLV26_N
LV28_NLV28_P
LV17_NLV17_P
LV19_NLV19_P
LV23_NLV23_P
LV15_NLV15_P
LV37_PLV37_N
LV38_P
LV16_PLV16_N
LV42_PLV42_N
LV20_NLV20_P
LV40_PLV40_N
LV24_NLV24_P
LV47_NLV47_P
LV48_NLV48_P
LV45_NLV45_P
LV43_NLV43_P
LV41_NLV41_P
LV39_PLV39_N
LV38_N
LV5_PLV5_N
LV80_P
LV1_NLV1_P
LV50_NLV50_P
LV60_NLV60_P
LV54_NLV54_P
LV56_NLV56_P
LV52_NLV52_P
LV9_PLV9_N
LV58_NLV58_P
LV2_PLV2_N
LV59_PLV59_N
LV49_NLV49_P
LV57_NLV57_P
LV51_NLV51_P
LV55_NLV55_P
LV53_NLV53_P
LV10_NLV10_P
LV6_PLV6_N
LV79_P
LV68_PLV68_N
LV70_NLV70_P
LV11_NLV11_P
LV64_PLV64_N
LV7_PLV7_N
LV62_NLV62_P
LV78_NLV78_P
LV3_PLV3_N
LV66_PLV66_N
LV72_PLV72_N
LV63_PLV63_N
LV8_PLV8_N
LV65_PLV65_N
LV77_PLV77_N
LV4_PLV4_N
LV61_PLV61_N
LV71_PLV71_N
LV67_PLV67_N
LV69_PLV69_N
LV12_PLV12_N
A1_B_SCTN_P
LV79_NLV80_N
/SPCLKSPCLK
LV77_N
LV77_P
LV69_N
/SPSCTNSPSCTN
EXT_SCTN_P
LV36_PLV36_N
LV34_PLV34_N
LV32_PLV32_N
LV35_PLV35_N
LV33_PLV33_N
LV31_PLV31_N
LV35_PLV35_N
LV33_PLV33_N
LV31_PLV31_N
LV36_NLV36_P
LV34_NLV34_P
LV32_NLV32_P
EXT_SCTN_N
EXT_CLK_P
EXT_CLK_N
D2_B_DACLKN
D2_B_DACLKP
D2_B_SCTN_P
D2_B_SCTN_N
C2_B_DACLKN
C2_B_DACLKP
B2_B_DACLKP
B2_B_DACLKN
A2_B_DACLKN
A2_B_DACLKP
C2_B_SCTN_P
C2_B_SCTN_N
B2_B_SCTN_P
B2_B_SCTN_N
A2_B_SCTN_N
A2_B_SCTN_P
D1_B_DACLKN
D1_B_SCTN_P
D1_B_SCTN_N
C1_B_DACLKN
C1_B_DACLKP
D1_B_DACLKP
C1_B_SCTN_P
C1_B_SCTN_N
B1_B_DACLKN
B1_B_DACLKP
B1_B_SCTN_P
B1_B_SCTN_N
A1_B_SCTN_P
A1_B_SCTN_N
A1_B_DACLKN
A1_B_DACLKP
S_SEL
LV17_NLV17_P
LV29_NLV29_P
LV37_PLV37_N
LV63_PLV63_N
LV65_PLV65_N
LV61_PLV61_N
LV64_PLV64_N
LV59_PLV59_N
LV49_NLV49_P
LV6_PLV6_N
LV50_NLV50_P
LV79_PLV79_N
LV80_PLV80_N
LV76_PLV76_N LV60_N
LV60_P
C_2.5V
C_2.5V
C_2.5V
C_2.5V
S_2.5V
S_2.5V
S_2.5V
S_2.5V
Title
Size Document Number Rev
Date: Sheet of
MWA_8T-BACKPLANE 1
KE-2257 VER1.1
D
1 1Friday, May 23, 2008
G:\MWA_8T_BACKPLANE\OUTSOURCING\HI_Q_ELECTRONICS\VER1.1_BKPLN_EDITED@HIQ\MAY_23_SCM_UPDATED_TO_HIQ_CORRECTIONS\MWA_8T_BP_V1.1_23MAY.DSN
Title
Size Document Number Rev
Date: Sheet of
MWA_8T-BACKPLANE 1
KE-2257 VER1.1
D
1 1Friday, May 23, 2008
G:\MWA_8T_BACKPLANE\OUTSOURCING\HI_Q_ELECTRONICS\VER1.1_BKPLN_EDITED@HIQ\MAY_23_SCM_UPDATED_TO_HIQ_CORRECTIONS\MWA_8T_BP_V1.1_23MAY.DSN
Title
Size Document Number Rev
Date: Sheet of
MWA_8T-BACKPLANE 1
KE-2257 VER1.1
D
1 1Friday, May 23, 2008
G:\MWA_8T_BACKPLANE\OUTSOURCING\HI_Q_ELECTRONICS\VER1.1_BKPLN_EDITED@HIQ\MAY_23_SCM_UPDATED_TO_HIQ_CORRECTIONS\MWA_8T_BP_V1.1_23MAY.DSN
AGFO BOARDADFB BOARD 1
FPGA4
FPGA4
ADFB BOARD 2
GCLK
GCLK to ADFB BRD1
GCLK to ADFB BRD2
CLK DIST CKT
SCTN to ADFB BOARD1
-���RQ�$*)2�%RDUG
TEMP MONITOR CARD CON ?
A1,/A1
from AGFO
TERMINATIONS ?
DECOUPLING CAPS
-���RQ�$*)2�%RDUGD1_B_DAP9D1_B_DAN9
D1_B_DAP8D1_B_DAN8
D1_B_DAP11D1_B_DAN11
D1_B_DAP13D1_B_DAN13
D1_B_DAP10D1_B_DAN10
D1_B_DAP12D1_B_DAN12
From J103D on adfb card
'�
&�
%�
$�
'�
&�
%�
$�
&&
Bank 15
D1_B_DAP12D1_B_DAN12
D1_B_DAP14D1_B_DAN14
D1_B_DAP10D1_B_DAN10
D1_B_DAP13D1_B_DAN13
D1_B_DAP8D1_B_DAN8
D1_B_DAP11D1_B_DAN11
D1_B_DAP9D1_B_DAN9
Bank 15
&&
'�
'�
FPGA3
FPGA2
FPGA1
D2_B_DAP12D2_B_DAN12
D2_B_DAP14D2_B_DAN14
D2_B_DAP10D2_B_DAN10
D2_B_DAP8D2_B_DAN8
Bank 15
Bank 15
D2_B_DAP9D2_B_DAN9
D2_B_DAP13D2_B_DAN13
D2_B_DAP11D2_B_DAN11
&&
'� '�
&&
C1_B_DAP12C1_B_DAN12
C1_B_DAP14C1_B_DAN14
C1_B_DAP10C1_B_DAN10
C1_B_DAP8C1_B_DAN8
Bank 11
Bank 11
C1_B_DAP9C1_B_DAN9
C1_B_DAP13C1_B_DAN13
C1_B_DAP11C1_B_DAN11
&&Bank 15
C1_B_DAP12C1_B_DAN12
C1_B_DAP14C1_B_DAN14
C1_B_DAP10C1_B_DAN10
C1_B_DAP9C1_B_DAN9
C1_B_DAP13C1_B_DAN13
C1_B_DAP11C1_B_DAN11
C1_B_DAP8C1_B_DAN8
Bank 15
FPGA3
&�
&�D2_B_DAN14D2_B_DAP14
C2_B_DAP12C2_B_DAN12
C2_B_DAP14C2_B_DAN14
C2_B_DAP10C2_B_DAN10
C2_B_DAP8C2_B_DAN8
Bank 11
Bank 11
C2_B_DAP9C2_B_DAN9
C2_B_DAP13C2_B_DAN13
C2_B_DAP11C2_B_DAN11
&&
&&
C2_B_DAP12C2_B_DAN12
B2_B_DAP9B2_B_DAN9
C2_B_DAP11C2_B_DAN11
Bank 11
Bank 11
C2_B_DAP9C2_B_DAN9
C2_B_DAP10C2_B_DAN10
C2_B_DAP8C2_B_DAN8
Bank 15
Bank 15
&� &�
FPGA2
FPGA1
B1_B_DAP12B1_B_DAN12
B1_B_DAP14B1_B_DAN14
B1_B_DAP10B1_B_DAN10
B1_B_DAP8B1_B_DAN8
Bank 13
Bank 13
B1_B_DAP9B1_B_DAN9
B1_B_DAP13B1_B_DAN13
B1_B_DAP11B1_B_DAN11
&&
B2_B_DAP8B2_B_DAN8
B2_B_DAP11B2_B_DAN11B1_B_DAP10
B1_B_DAN10B1_B_DAN11B1_B_DAP11
&&B1_B_DAP12B1_B_DAN12
B1_B_DAP13B1_B_DAN13 B1_B_DAN14
B1_B_DAP14
%�
%�%� %�
B2_B_DAP12B2_B_DAN12
B2_B_DAP14B2_B_DAN14
B2_B_DAP10B2_B_DAN10
B2_B_DAP8B2_B_DAN8
Bank 13
Bank 13
B2_B_DAP9B2_B_DAN9
B2_B_DAP13B2_B_DAN13
B2_B_DAP11B2_B_DAN11
%�
&�C2_B_DAP13C2_B_DAN13
C2_B_DAP14C2_B_DAN14%�
%�%�
B1_B_DAP9B1_B_DAN9
B1_B_DAP8B1_B_DAN8
B2_B_DAP10B2_B_DAN10 %�
&&B2_B_DAP12B2_B_DAN12
B2_B_DAN13B2_B_DAP13
B2_B_DAN14B2_B_DAP14
A1_B_DAP12A1_B_DAN12
A1_B_DAP14A1_B_DAN14
A1_B_DAP10A1_B_DAN10
A1_B_DAP8A1_B_DAN8
Bank 17
Bank 17
A1_B_DAP9A1_B_DAN9
A1_B_DAP13A1_B_DAN13
A1_B_DAP11A1_B_DAN11
&&
&&
A1_B_DAP12A1_B_DAN12
A1_B_DAP14A1_B_DAN14
A1_B_DAP10A1_B_DAN10
A1_B_DAP8A1_B_DAN8
A1_B_DAP9A1_B_DAN9
A1_B_DAP13A1_B_DAN13
A1_B_DAP11A1_B_DAN11
$�$�
A2_B_DAP12A2_B_DAN12
A2_B_DAP14A2_B_DAN14
A2_B_DAP10A2_B_DAN10
A2_B_DAP8A2_B_DAN8
Bank 17
Bank 17
A2_B_DAP9A2_B_DAN9
A2_B_DAP13A2_B_DAN13
A2_B_DAP11A2_B_DAN11
&&
$�$�A2_B_DAP12
A2_B_DAN12
A2_B_DAP14A2_B_DAN14
A2_B_DAP10A2_B_DAN10
A2_B_DAP8A2_B_DAN8
A2_B_DAP9A2_B_DAN9
A2_B_DAP13A2_B_DAN13
A2_B_DAP11A2_B_DAN11
$�
GCLK INPUT
SCTN INPUT
GCLK OUTPUT SCTN OUTPUT
DAS_1DAS_2
DAS_3
DAS_4
DAS_5DAS_6
DAS_8
DAS_10
DAS_11
DAS_12
DAS_13
DAS_14
*&*&
*&
*&
&&
&&
TO AGFO
2.5LVDS 1:10 GLITCHLESS CLK BUF
2.5LVDS 1:10 GLITCHLESS CLK BUF
DECOUPLING CAPS
SCTN DIST CKT
A1,/A1
from AGFO
SCTNTO AGFO
SPARESPARE
D2_B_DAP9D2_B_DAN9
D2_B_DAP13D2_B_DAN13
D2_B_DAP11D2_B_DAN11
D2_B_DAP10D2_B_DAN10
D2_B_DAP8
D2_B_DAP12D2_B_DAN12
D2_B_DAN8
1&�9����
1&�9����
1&�9����
1&�9����
�9����
�9���� D1_B_DAP14D1_B_DAN14
�9����
�9����
�9����
8GT�����5EJGOCVKE 2%$�)GTDGT�HKNGU�GFKVGF�"�*K3�'NGEVTQPKEU
R12R12
C500.01uFC500.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J5B
Erni _973056
J5B
Erni _973056
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J2A
Erni _973056
J2A
Erni _973056
R10R10
R15R15
C360.1uFC360.1uF
C550.01uFC550.01uF
C280.1uFC280.1uF
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J7A
Erni _973056
J7A
Erni _973056
R23R23
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J4B
Erni _973056
J4B
Erni _973056
R30R30
C370.1uFC370.1uF
C320.1uFC320.1uF
C390.1uFC390.1uF
C300.1uFC300.1uF
123
J19
header3
J19
header3
GND13
/PD29
FSEL31
VDD312
VDD419
VDD28VDD12
A19
/A110
A222
/A221
GND220
Q1 4
Q2 6
Q3 13
Q4 15
/Q1 5
/Q2 7
/Q3 14
/Q4 16
SEL40
/G11
GL11
/G230
Q5 17
/Q5 18
/Q6 24
/Q7 26
Q6 25
Q7 27
Q8 34
/Q8 33
/Q9 35
/Q10 37
Q9 36
Q10 38
VDD523
VDD628
VDD732
VDD839
U1
IDT5T93GL10
U1
IDT5T93GL10
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J7B
Erni _973056
J7B
Erni _973056
C380.1uFC380.1uF
C610.1uFC610.1uF
C290.1uFC290.1uF
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J1A
Erni _973056
J1A
Erni _973056
C400.1uFC400.1uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J8B
Erni _973056
J8B
Erni _973056
R21R21
R31R31
C590.1uFC590.1uF
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J3A
Erni _973056
J3A
Erni _973056
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J6A
Erni _973056
J6A
Erni _973056
12
J27
HEADER 2
J27
HEADER 2
C560.01uFC560.01uF
R18R18
C510.01uFC510.01uF
12
J41
HEADER 2
J41
HEADER 2
C460.01uFC460.01uF
C340.1uFC340.1uF
12
J28
HEADER 2
J28
HEADER 2
12
J32
HEADER 2
J32
HEADER 2
R13R13
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J5A
Erni _973056
J5A
Erni _973056
R19R19
12
J42
HEADER 2
J42
HEADER 2
C310.1uFC310.1uF
C410.1uFC410.1uF
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J35A
Erni _973031
J35A
Erni _973031
R32R32
C420.01uFC420.01uF
R20R20
12
J33
HEADER 2
J33
HEADER 2
12
J29
HEADER 2
J29
HEADER 2
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J36A
Erni _973031
J36A
Erni _973031
12
J43
HEADER 2
J43
HEADER 2
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J4A
Erni _973056
J4A
Erni _973056
1
2
345
J14
SMA
J14
SMA
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J3B
Erni _973056
J3B
Erni _973056
1
2
345
J17
SMA
J17
SMA
C430.01uFC430.01uF
C470.01uFC470.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J2B
Erni _973056
J2B
Erni _973056
R14R14
12
J34
HEADER 2
J34
HEADER 2
12
J30
HEADER 2
J30
HEADER 2
12
J44
HEADER 2
J44
HEADER 2
C520.01uFC520.01uF
1
2
345
J15
SMA
J15
SMA R22R22
C350.1uFC350.1uF
123
J18
header3
J18
header3
12
J38
HEADER 2
J38
HEADER 2
C480.01uFC480.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10CD1CD2CD3CD4CD5CD6CD7CD8CD9
CD10
EF1EF2EF3EF4EF5EF6EF7EF8EF9EF10GH1GH2GH3GH4GH5GH6GH7GH8GH9GH10
J35C
Erni _973031
J35C
Erni _973031
R11R11
C570.01uFC570.01uF
12
J31
HEADER 2
J31
HEADER 2
12
J26
HEADER 2
J26
HEADER 2
C440.01uFC440.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J6B
Erni _973056
J6B
Erni _973056
C540.01uFC540.01uF
R24R24
12
J39
HEADER 2
J39
HEADER 2
C490.01uFC490.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10CD1CD2CD3CD4CD5CD6CD7CD8CD9
CD10
EF1EF2EF3EF4EF5EF6EF7EF8EF9EF10GH1GH2GH3GH4GH5GH6GH7GH8GH9GH10
J36C
Erni _973031
J36C
Erni _973031
C600.1uFC600.1uF
12
J46
HEADER 2
J46
HEADER 2
C330.1uFC330.1uF GND13
/PD29
FSEL31
VDD312
VDD419
VDD28VDD12
A19
/A110
A222
/A221
GND220
Q1 4
Q2 6
Q3 13
Q4 15
/Q1 5
/Q2 7
/Q3 14
/Q4 16
SEL40
/G11
GL11
/G230
Q5 17
/Q5 18
/Q6 24
/Q7 26
Q6 25
Q7 27
Q8 34
/Q8 33
/Q9 35
/Q10 37
Q9 36
Q10 38
VDD523
VDD628
VDD732
VDD839
U2
IDT5T93GL10
U2
IDT5T93GL10
R17R17
1
2
345
J16
SMA
J16
SMA
C450.01uFC450.01uF
12
J40
HEADER 2
J40
HEADER 2
1
4
2
3
L3
DLP11S_0504
L3
DLP11S_0504
A1B1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
J8A
Erni _973056
J8A
Erni _973056
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J35B
Erni _973031
J35B
Erni _973031
C580.1uFC580.1uF
1
4
2
3
L4
DLP11S_0504
L4
DLP11S_0504
C530.01uFC530.01uF
AB1AB2AB3AB4AB5AB6AB7AB8AB9
AB10
CD1CD2CD3CD4CD5CD6CD7CD8CD9CD10
J1B
Erni _973056
J1B
Erni _973056
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J36B
Erni _973031
J36B
Erni _973031
R9R9
Figure 2: Circuit schematic of the Digital Receiver Backplane (Page 1/2)
3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EXT5V
C_2.5V
S_2.5V
EXT5V_IN EXT5V
EXT5V
EXT5V
EXT5V EXT5V
EXT5VEXT5V_IN
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
B
1 1Friday, May 23, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
B
1 1Friday, May 23, 2008
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
B
1 1Friday, May 23, 2008
POWER
AGFO Power Conn.
BLUE
���9�IRU�&/.�',67�&.7
tan cap
RED
GREENtan cap
���9�IRU�6&71�',67�&.7
I/P TERM BLK
ADFB1 Power
EMI FILTER
TEMP SENSOR CKT
ADFB2 Power
DCAPS
?
?R4R4
124
3
J23
HEADER 2
J23
HEADER 2
C680.1uFC680.1uF
C810.01uFC810.01uF
12
D6
1N6267A
D6
1N6267A
C13
100uF
C13
100uF
C26
100uF
C26
100uF
C15
100uF
C15
100uF
11 2 2
GP1
Erni-214363
GP1
Erni-214363
R5R5
C690.1uFC690.1uF
R33R33
R6
100K
R6
100K
C16
100uF
C16
100uF
C850.1uFC850.1uF
C27
100uF
C27
100uF
C700.1uFC700.1uF
L2
ferrite-220
L2
ferrite-220
TP9
TP
TP9
TP
12
D2
LED
D2
LED
TP2
TP
TP2
TPC860.1uFC860.1uF
C17
100uF
C17
100uF
12
D4
1N6267A
D4
1N6267A
C930.1uFC930.1uF
C710.1uFC710.1uF
C82
0.1uF
C82
0.1uF
G2
I1 O 3
U13U13
TP10
TP
TP10
TP
C12
100uF
C12
100uF
Vin2
Inhibit1
Vout 4
VoAdj 5
GN
D3
gn
d6
gn
d7
gn
d8
gn
d9
U10 PT5402U10 PT5402
C18
100uF
C18
100uF
C870.1uFC870.1uF
TP11
TP
TP11
TP
C940.01uFC940.01uF
C720.1uFC720.1uF
11 2 2
GP2
Erni_214363
GP2
Erni_214363
C880.1uFC880.1uF
C19
100uF
C19
100uF
TP3
TP
TP3
TP
TP12
TP
TP12
TP
C730.01uFC730.01uF
12
D5
1N6267A
D5
1N6267A
VS+1 VOUT 2U12
LM35/TO
U12
LM35/TO
R34R34
C20
100uF
C20
100uF
C890.01uFC890.01uF
TP4
TP
TP4
TP
C740.01uFC740.01uF
R3R3
C21
100uF
C21
100uF
C900.01uFC900.01uF
C750.01uFC750.01uF
C630.1uFC630.1uF
C410uF
C410uF
C62
0.1uF
C62
0.1uF
C22
100uF
C22
100uF
C910.01uFC910.01uF
A1 A1
A2 A2
A3 A3
A4 A4
B1 B1
B2 B2
B3 B3
B4 B4
C1 C1
C2 C2
C3 C3
C4 C4
J12
Erni _114404
J12
Erni _114404
124
3
J24
HEADER 2
J24
HEADER 2
C760.01uFC760.01uF
11 2 2
GP3
Erni_214363
GP3
Erni_214363
12
D1
LED
D1
LED
C640.1uFC640.1uF
C920.01uFC920.01uF
TP1
TP
TP1
TP
TP5
TP
TP5
TP
C770.01uFC770.01uF
C650.1uFC650.1uF
TP6
TP
TP6
TP
C780.01uFC780.01uF
124
3
J25
HEADER 2
J25
HEADER 2
C23
100uF
C23
100uF
G2
I1 O 3
U11U11
C10
100uF
C10
100uF
C660.1uFC660.1uF
C5
10uF
C5
10uF
TP7
TP
TP7
TP
C790.01uFC790.01uF
12
J22
HEADER 2
J22
HEADER 2
C24
100uF
C24
100uF
C84
0.1uF
C84
0.1uF
12
D3
LED
D3
LED
C83
0.1uF
C83
0.1uF
TP8
TP
TP8
TP
C11
100uF
C11
100uF
C670.1uFC670.1uF
A1A1
A2A2
A3A3
A4A4
B1B1
B2B2
B3B3
B4B4
C1C1
C2C2
C3C3
C4C4
J13
Erni_114404
J13
Erni_114404
C800.01uFC800.01uF
C14
100uF
C14
100uF
L1
ferrite-220
L1
ferrite-220
C25
100uF
C25
100uF
Figure 3: Circuit schematic of the Digital Receiver Backplane (Page 2/2)
4
Appendix B : PCB Layout and related plots
Figure 4: Mechanical and PCB parameters of Backplane
5
Figure 5: Component side PCB layout
6
Figure 6: PCB layout of layer 2: Ground layer
7
Figure 7: PCB layout of layer 3: Interconnection between ADFB and AgFo
8
Figure 8: PCB layout of layer 4: Ground layer
9
Figure 9: PCB layout of layer 5: power layer
10
Figure 10: PCB layout of layer 6: SCTN, clock and VSIB data connection
11
Figure 11: PCB layout of layer 7: power layer
12
Figure 12: Solder side PCB layout
13