On-chip inductance and coupling

Zeynep Dilli, Neil Goldsman

Thanks to Todd Firestone and John Rodgers for providing the laboratory equipment and expertise for measurements.

EM-sensitive components on semiconductor chips

Modern RF circuits often feature on-chip inductors required by circuit designOperating frequencies are high enough to

make this feasibleIncreasing circuit complexity also creates

other inductive componentsLong transmission (bus) lines; signal/clock

distribution networks…

Motivation for modeling

Investigating parasitic effectsVulnerability to external EM interferencePotential to create on-chip interference

RadiationSubstrate current

System-on-a-chip RF circuits require on-chip inductors with high L, small area and high QAutomated design and speedy evaluation of

geometrical tradeoffs.

Issues in modeling

Semiconductor substrates are conductive unable to treat system as metal/dielectric/ground planeNew processes feature higher doping, higher

conductivityDevice circuits underneath metal structures

display variable dopingNon-uniform substrate: n+ and p+ active

regions, n-wells, p-wells, lightly doped chip substrate…

Inductor modeling---theory

Modeling Approach: Divide a spiral inductor into segments and treat each current segment separately.

11 ,12 ,11

,21 22 ,12

, 1 , 2

m m N

m m N

m N m N NNN

L L LV I

L L LV Is

L L LV I

Lkk=self-inductance (external+internal) of segment k Sources: Frequency-dependent current distribution within the segment and the magnetic flux linkage to the loop formed by the segment and its return current. Lkl=mutual inductance between segments k and l Sources: Magnetic flux linkage of the current in the first segment to the loop formed by the second segment and its return current.Lossy substrate effect: The return current has an effective distance into the substrate; this is frequency-dependent and can be modeled as a complex distance to account for the losses.

Other frequency dependency: Skin effect in the metal; current crowding in the metal

Internal self-inductance

Frequency-dependent current distribution creates an internal self-impedance

JjJ 22

)()( int,

.

0 self

cond

LRdsJ

EZ

Solve Helmholtz Eqn. for current distribution:

Obtain resistance and inductance from J:

Internal self-inductance

Physical current in cylindrical conductor, f=5GHz

J

center r edge

External self-inductance

Flux of magnetic field linked to surface between interconnect and its return current

IL selfext

,

;

sdB

Need to define the return current path to determine the flux linkage area. If the frequency is low enough or substrate has low conductivity, the physical ground plane below the substrate is used for this purpose.

But silicon substrates are not dielectric: With higher doping levels in modernprocess technologies to optimize the active devices on chips, the substrate conductivities rise.

And our operating frequencies of interest are high.

Skin depth of semiconductor substrate

Within our frequency range the skin depth will fall below our substrate thickness

(around 5 GHz for p-type sub.,around 2 GHz for n-well, lower for active regions)

External self-inductance

;

Weisshaar et.al. showed in 2002 that an image current with a complex distance can be defined for the metal-oxide-lossy substrate system.

11 tanh sub

eff ox

j hh h j

D

Insulatoroxh

Metal Plate

subh Substrate

Signal Current

Image Current

Effective virtual ground plane distancefrom the signal current

Return current depth

Mutual inductance

,

14

i j

i i j j

j

c c j i ji ja b a b

i ijm ij

j j

a

J dl dlda da

a RL

J da

������������� �

Mutual inductance: The magnetic flux created by the current on one loop linking to the area of other loop

ijij

j

LI

Calculate from the magnetic vector potential and I from the current distribution; the mutual inductance between two current segments is then

Frequency dependency: The signal current of a current segment and its image current both induce voltages on the “target” current segment; the distribution of the image current varies with frequency on a semiconductor substrate.

xpx

qx

2pW

2

pW

2qW

2

qW

qxJ

qxJ

'qqh

yz

Virtual Ground Plane

qp

'q (image)

1py

2py

1qy

2qy

pqh

Inductor modeling---Design issues

Variations in layout:Metal layerLengthNumber of turnsMetal trace widthMetal trace spacingSubstrate dopingShape…

Some ResultsLength Variation

Increasing the length of the inductor increases inductance, but leads to a decline in Q due to increasing serial resistance as well, this effect worsening at higher frequencies as skin effect increases the resistance faster than linearly with length.

Some ResultsNumber of Turns VariationAn inductor with the same length but with more turns has higher inductance, but the resistance does not rise quite so high so the detrimental effect to Q is less: Increasing the number of turns is a better way to increase inductance.

Some ResultsTrace Spacing VariationNarrower spacing yields a higher inductance, but will probably increase capacitive coupling between turns.

Some ResultsSubstrate Doping VariationOverall, higher doping reduces inductance (closer return current, smaller loops) and makes it more freq-dependent (low enough doping pushes all current to bottom). Relationship between resistance and doping is not straightforward, since conductivity of substrate affects return current distribution, composition, and its frequency dependence all at the same time and these effects interact.

Inductors--- Test Chip

Designed for RF-probe station measurements

Manufacturedthrough MOSIS

AMIS 0.5 μm3 Metal layers

Inductors--- Test Chip

Planar inductoron substrate

Planar inductoron grounded poly

Planar inductor on n-well

Transformer

Stacked inductoron substrate

RF probe tip

Inductors--- Test Chip, measurements

Cascade probes used with Hewlett-Packard Network AnalysisMeasured: S22

0 2222 0

0 22

1

1L

LL

Z Z SS Z Z

Z Z S

Inductors--- Test Chip, measurements

Inductors--- Test Chip, measurements

EM Coupling Test Chip 2

For RF-probestation measurements

Manufacturedthrough MOSIS

AMIS 0.5 μm3 Metal layers

EM Coupling Test Chip 2

Planar inductor

NMOS 1

NMOS 2

N-wells

inverter

NMOS 3

On-Chip EM Coupling

• Coupling between On-chip Inductors

Left: Results from literature and circuit model for coupled on-chip inductorsRight: Our test structure for measuring coupling between inductors on different metal layers

On-Chip EM Coupling: Inductor to inductor

On-Chip EM Coupling: N-well to n-well

P-Type Silicon Substrate

N Well N Well

Oxide

Metal Contact

Port 1 Port 2

m8.28 m8.28m45.102

Need substrate current analysis….