On Modeling and Sensitivity of Via Count in SOC Physical Implementation

Kwangok Jeong (kjeong@vlsicad.ucsd.edu)Andrew B. Kahng (abk@cs.ucsd.edu)Hailong Yao (hailong@cs.ucsd.edu)

VLSI CAD LABORATORYUCSD

Nov. 24, 2008

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Outline

Motivation

Review of Via Count Estimation

Key Parameters to Via Count

Taxonomy of Via Count Modeling Approaches

Verification of Model

Conclusion

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Motivation Via analysis and estimation are of great importance

Yield: via open, high-resistance fault = key defect types Evaluating performance of existing routers

32nm via rules Evaluating new technologies or designs 3D implementation needs (via density, …)

Previous work based on “Rent’s parameter”

In this work, we give taxonomy of via modeling and propose a new via count model for placed designs

PNkT

average pins per gate

number of terminals

number of components

Rent’s parameter

Landman et al., 1971

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Review of Via Count Estimation Uezono’s model (T. Uezono et al., ISQED, 2006.)

Heavily depends on wire length and track utilization

l : estimated wirelengthut : track utilization

Up to 19% error in the experimental results Questionable argument

Why does #via increase with decreasing Rent’s parameter?

Uezono’s model uses Davis et al.’s wirelength distribution

that has error in #net for length = 1

1 2 1 2( ) ( , )via t tn l l u u

Correlation between the Rent’s parameter pand the number of vias (Uezono et al., ISQED06)

Truncated binomial series in Davis’s model

exp ( ) [(1 ( 1)) ( ( 1)) ( ( 1)) (1 ( 1)) ]2

p p p pkI l l l l l l l l l

l

2 4exp ( ) (2 2 )

2pp

I l k p l

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Key Parameters Affecting Via Count Experimental setup

For N, k, p, U, M and Tech: use Rentian circuit generator (gnl [1])

For F: use two different clock frequency for AES from opencores.org

For k (in real design): AES SP&R with different cell sets (whole vs. restricted)

DOE Parameters Values

Number of gates (N)Average terminals per gate (k)Rent’s parameter (p)Placement Utilization (U)Number of metal layers (M)Technology (Tech)

10,000 / 20,0002 / 3 / 4 / 5 / 60.1 / 0.3 / 0.5 / 0.7 / 0.950% / 70% / 90%4 / 5 / 6 / 7 /890nm / 65nm

[1] D. Stroobandt, P. Verplaetse and J. V. Campenhout, "Generating Synthetic Benchmark Circuits for Evaluating CAD Tools", IEEE Trans. On Computer-Aided Design Of Integrated Circuits and Systems, (19)(9) (2000), pp. 1011-1022.

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Sensitivity to Design Parameters(Rentian Circuits)

Observations N #vias k #vias p #vias U #vias M #vias

0

20000

40000

60000

80000

100000

120000

140000

160000

50 70 90 50 70 90 50 70 90 50 70 90 50 70 90

4 5 6 7 8

#via

Metal Layer & Utilization (%)

90nm, N=20,000 65nm, N=20,000

90nm, N=10,000 65nm, N=10,000

#vias vs. #instance (N), technology(Tech), #metal (M), and utilization (U)

0

20000

40000

60000

80000

100000

120000

140000

160000

180000

0.1 0.3 0.5

#via

p (Rent's parameter)

k=2

k=3

k=4

k=5

k=6

#vias vs. #pins per gate (k),and Rent’s parameter (p)

Experimental results show #via increases even for small Rent’s parameters

#points to be connected

wirelength

track utilization

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Sensitivity to Design Parameters (Real Designs) AES (~15K) core from opencores.org Clock frequency (F): 50MHz and 400MHz (8X)

#pins per gate (k) Large-k: use a full set of cells in the library Small-k: use only INV, BUF, NAND2 and DFF

Wiring pitch (wp): original, half (2x tracks)

Design Freq. #inst. k #vias

Small-k 400 MHz 32008 2.7 204248

Small-k 50 MHz 31333 2.7 196410

Large-k 400 MHz 12689 3.6 142174

Large-k 50 MHz 11258 3.9 128441

Pitch WL (um) #vias

Original 5.19E+5 178190

Half 4.66E+5 145139

#via vs. wiring pitch (wp)#via vs. pins per gate (k) and frequency (F)

#vias increases by 4~11%

k increases from 2.7 to 3.6 #vias increases by 44%

#vias decreases by 17%

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Summary of Sensitivities to Design Parameters

Parameters Sensitivity

Number of gates(N)

Pins per gate (k)

Rent’s parameter (p)

Placement util. (U)

Number of metals (M)

Wiring pitch (wp)

Clock frequency (F)

Technology (Tech)

Strong positive

Strong positive

Positive

Positive

Weak

Negative

Weak positive

Weak negative

RoutingCongestion

orTrack

Utilization

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Via Count Estimation

Key ideas

#vias strongly depends on kN = total #pins

M1 layer generally not used for cell connections

all pins need V12

If no design rules, all routes can be implemented with 1-tier

(H/V) of routing layers No detours and no additional vias

baseline of #vias

Congestion increases #vias

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Taxonomy of Via Modeling Approach (1)

① Analytical method Inputs: given N, k and p Enable to estimate #vias

prior to netlist

② Netlist-based method Inputs: extracted N, k and p Parameters are extracted

from netlist better accuracy Model:

VL: baseline of #vias Vcongestion: additional vias from routing congestion

VL calculation H-BBOX model

#VIA12 = #pins ( ) #VIA23 = #pins

V-BBOX #VIA12 = #pins #VIA23 = 2 x #pins

Vcongestion calculation

Aspect ratio of net’s bounding box < 1

(H-BBOX: 2kN)

Aspect ratio of net’s bounding box > 1

(V-BBOX: 3kN)

Nk 5.2

congestionLest VVV

T

pkNWCCi ,, ;

layer metalper length track available

modelh wirelengtanalytical fromh wirelengt totalestimated ,,

iT

pKNW

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Taxonomy of Via Modeling Approach (2)

③ Placement-based method Inputs: placed design accurate wirelength estimation Baseline of #vias (VL)

Construct Steiner minimum tree (SMT) Assign SMT segments to 1-tier routing layer

Horizontal M3, Vertical segments M2 Diagonal segments converted to ‘L’ shape M2 and M3

Count #vias at each point

Average routing congestion Large congestion requires more vias

Placement-based via count model

2///2/ vvhhvhavg TSTSCCC S: Sum of SMT lengthT: Sum of available track length

avg

CVVV SLest parameters Fitting :,

ntsPoi bendingPoints,Steiner Pins,

SV

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Model Fitting using Training Designs Finding model coefficients

Initial guess: : via count increase due to via blockages ~ 4 : affects probability of via blockage

Final model coefficients ( )

Average 3.4% error

Tech. Design #Instance VL Vest Vactual Error (%)

65 AES 14,351 113,530 153,262 154,667 0.92 65 JPEG 63,932 531,512 591,788 608,105 2.76 65 X5JPEG 309,543 2,626,942 2,962,400 3,028,111 2.22 90 AES 18,078 129,651 179,439 181,449 1.12 90 AES large-K 10,999 94,532 128,441 120,231 -6.39 90 AES small-K 31,074 178,657 196,410 214,711 9.32 90 AES M5 15,468 118,601 178,190 182,681 2.52 90 AES M6 15,468 118,601 168,940 161,602 -4.34 90 AES M7 15,468 118,601 167,542 158,475 -5.41 90 AES M8 15,468 118,601 160,819 154,770 -3.76 90 AES original pitch 15,468 118,601 178,190 182,681 2.52 90 AES half pitch 15,468 118,602 145,139 139,285 -4.03 90 JPEG 77,106 588,776 688,005 695,543 1.10 90 X5JPEG 349,273 2,799,553 3,226,709 3,265,394 1.20

avg

CVVV SLest

63.1 ,64.6 %30~10C

A via blockage can increase #vias bymore than 4

Via blockage

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Model Accuracy on Industry Designs We apply proposed placement-based via count

model to designs from different technologies and different routers

Our model shows 8% error in average

Tech. Design #instance VL Vest Vactual Error (%)

45 A 39,247 301,493 354,206 375,904 -5.77 45 B 119,369 956,957 1,153,821 1,361,115 -15.23 45 C 194,679 1,597,528 1,873,391 2,193,488 -14.59 45 D 160,548 1,379,472 1,587,531 1,799,280 -11.77 45 E 145,751 1,227,911 1,648,991 1,828,896 -9.84 45 F 538,854 4,344,293 5,818,949 7,002,817 -16.91 65 G 43,629 241,402 277,201 265,913 4.25 65 H 134,157 704,894 789,101 810,307 -2.62 65 I 265,716 1,214,448 1,341,729 1,457,641 -7.95 65 J 240,169 1,334,664 1,460,128 1,491,943 -2.13 65 K 159,197 973,442 1,174,340 1,173,756 0.05 65 L 185,816 926,043 1,159,127 1,059,627 9.39 65 M 576,326 3,090,807 3,512,130 4,021,001 -12.66 65 N 463,978 2,270,045 2,587,246 2,867,351 -9.77 65 O 598,060 4,930,753 5,442,908 5,475,473 -0.59 90 P 31,132 259,726 323,594 331,979 -2.53

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Conclusion and Ongoing Work Conclusion

We evaluate the sensitivities of design and technology parameters on via count

Propose a new accurate placement-based via count estimation model

Experimental results are promising 3.4% error on training designs with various instance counts, pins

per gate, number of metal layers and wiring pitches 8% error on various industry designs from different technologies

and routers

Ongoing work Accurate wirelength estimation for analytical and netlist-

based via count modeling Feed into the development of improved routers Ability to assess impact of varying design rules and/or

different router runtime options