Optimization and implementation of a multi-level buck converter for standard CMOS on-chip integration

International Workshop on Power Supply On ChipSeptember 22nd - 24th, 2008, Cork, Ireland

Vahid Yousefzadeh, Toru Takayama

Dragan Maksimović

Colorado Power Electronics CenterECE Department, 425 UCB

University of ColoradoBoulder, CO 80309-0425maksimov@colorado.edu

Gerard VillarEduard Alarcón

Dept. of Electronic EngineeringTechnical University of CatalunyaCampus Nord UPC – Building C4

08034 Barcelona, Spainealarcon@eel.upc.edu

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

Vin

Vin/2Vin-VC Vin

g1

g3

Vin VCVSW VC

TsTs/20 t(D > 0.5)

3-Level (2-cell) Buck Converter

• 3-level (2-cell) converter has been proposed for high voltage inverters [Meynard et al., 1992]

• “g1-g2” & “g3-g4” are complementary switches

• g1 and g3 have the same duty cycle

• VC = ½ Vin • Objective:Investigate potential for lower ripple/ higher efficiency / lower reactive component size / higher bandwidth realization of DC-DC converter

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.2

0.4

0.6

0.8

1i2

i3

Duty cycle D

Indu

ctor

cur

rent

ripp

le

i

0

20

40

60

80

100

120

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Out

put v

olta

ge ri

pple

v

(mV

)4 times smaller peak inductor current ripple

8 times smaller peak capacitor voltage ripple

Ripple comparison of 3-level and buck converter with same fs, L, C

( ) 2max_3max_1

1 vn

v n ∆−

=∆( ) 2max_2max_

11 i

ni n ∆

−=∆

Switching Ripple in the 3-Level Buck Converter

Ripple results similar to two-phase converter, but with a single, smaller inductor

• For ∆vmax = 12 mV, fs_3 = 200 kHz, fs_2= 560 kHz ⇒ η2 = 0.83 and η3 = 0.92 ⇒ improved efficiency

• Same fs, ∆vo ∆iL ⇒ L3 = 0.25L2, C3 = 0.5C2 ⇒ reduced area

Comparison of 3-level and buck converter

Example application to switching power amplifier

3-Level (2-cell) Buck Converter

Two-Tone Signal Generation Using a 3-Level and a Buck Converter

A two-tone signal generated with a three-level and a buck converter.

Switching frequency, fs = 1MHz, fsig = 100kHz, fo = 550kHz, Q = 1

Experimental Envelope Tracking Waveforms

Vout

Frequency spectrumof Vout

Harmonic componentsof rectified sinusoid

Switching harmonics

Vout

Frequency spectrumof Vout

Harmonic componentsof rectified sinusoid

Switching harmonics

Standard buck converter• Standard buck and 3-level buck compared for the same open-loop

bandwidth and the same switching frequency• Modulation: rectified sine-wave at fm = 20 kHz• 30dB lower switching-frequency harmonic in the 3-level converter

3-level buck converter

Cx+

-VC

Vin

g1

g2

g3g4

VSW

+_y

+_

Vin/2 - Vq/2

Vin/2 + Vq/2

VSW

x

g3=d(t)+ dg1=d(t)

Flying capacitor voltage control

• Digital (verilog) controller implementation using FPGA

• x and y are sampled atVsw = VC orVsw = Vin - VC

VSWVin

Vin/2Vin-VC Vin-VCVC VC

g1

g3

TsTs/20 t

sample sample

Experimental waveforms for flying capacitor voltage control

Vsw

g1

g3

Vsw

g1

g3

Uncontrolled capacitor Cx

voltage

Controlled capacitor Cx

voltage

Vin-Vc Vc

D > 0.5

Vin-Vc Vc

D > 0.5

VcVin-Vc

D < 0.5

Vin-Vc Vc

D < 0.5

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

Low-Cx resonant 3-level buck converter in DCM. Self-driving transistor-level topology

Self-driving scheme to interconnect power transistors and drivers, which reduces the voltage across the power MOSFETs gate dielectric.

3-level self-driving PFM low-Cx buck converter

Driver supply voltage and vgs for all power MOSFETs, Cadence transistor-level simulations.

37 MHz switching frequency26 nH inductance

3-level self-driving PFM low-Cx buck converter

• Use of core transistors to implement the power MOSFETs• Use of core transistors to implement power drivers of P2 & N2• Reduces the power consumption of the power drivers

Representative waveforms corresponding to a DCM operated 3-level Buck converter, duty cycle below 50%

Control signal-to-output voltage transfer function comparison between the 3-level (Cxsweep) and the classical (dotted line) Buck converters.

Output voltage ripple as a function of Vo, for the 3-level (Cx sweep) and the classical (dotted line) Buck converters.

3-level self-driving PFM low-Cx buck converter

L=35nHCo=30nFfs=25MHz

Vbat=3.6VVo=1VIo=100mA

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

),,( svs

osoo fCLf

RCfDV

RCDTVv

o∆===∆

L

C RV in

iL

Vout

+ +

-

iouti in

d(t)

+

-

RW+RC

Q1

Q2

Ts=1/fs

D=Ton/Ts

Ton

),,( sLin

allQcoreLDCLLin fCLfIV

PPPIVηη =

−−−= −−−

),,(2 sareaQLC fCLfAAAArea =++=

Optimized design space exploration (II)

Circuit topology considerations

1) Model each performance index (ripple, efficiency and area) as a function of design parameters: inductor, capacitor and switching frequency

Occupied area

Efficiency

Output voltage ripple

A priori parameters and assumptions are application-oriented: topology, Vin, Vout, and the target IC technology parameters.

∏∏

=Γ

jnjj

inii

n xxf

xxfxx

j

i

)(

)()(

,...,1

,...,1

,...,1 γ

γ

β

β

),,(),,(),,(

),,( 2svsA

ss fCLffCLf

fCLffCL

o∆⋅=Γ η

LL

L L

LL

LL CC

C C

CC

CCf f

f f

f f

ff

η

∆vo

A

Γ

fs=1MHz,100MHz, L=10nH,1uH, C=10pF,10nF

Optimized design space exploration (III)

Circuit topology considerations

2) Define a merit figure encompassing the performance indexes to be maximized or minimized

generic merit figure

Boost converter case example merit figure

Occupied area

Efficiency

Output voltage ripple

Merit figure

Note that the area dependence is square-weighted so as to solve the ill-conditioned solution of ∆vo→∞ when A→0.

16.5Ω

2.5 V

i L

3.3 V

+ +

-

ioutiin 0.82 Ω 30 nH

kcore=221⋅10-11

δL=0.04 H/m2

W=3352 µm

L=0.35 µm

W=3352 µmL=0.35 µm

W=2500 µmL=2500 µm

Vout

(V)

IL

(A)

Design example for a standard 0.35 µm CMOS technology

3) Obtain optimum point within design space (L,C, fs) as regardsefficiency, occupied area, functionality

Optimized design space exploration (IV)

Circuit topology considerations

Specs: ∆vo =0.1 V iout=0.4 AOptimization result: L= 30 nH, C= , fs= 50 MHz

Design space exploration of a CMOS-compatible 3-level converter: 70% efficiency, 5mm2 silicon and fs=37 MHz

3-level converter design example for a standard 0.25 µm CMOS technology

Optimized design space exploration

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

•Area underneath inductor is usable for capacitors and power MOSFETs

Bondwire triangular spiral inductors in standard CMOS

Complete loss optimization of on-chip CMOS synchronous rectifier

Power MOSFETs

Breakdown of loss distribution, corresponding the optimized design of power MOSFETs and their associated drivers.

WP = 3092µm WN = 2913µm powerdrivers with 7.59 and 7.48 tapering factorsOverall losses 37.1mW

Additional degree of freedom: impact of Wp upon efficiency and delay

Power MOSFET gate drive design

Qi and Qe1 variation as a function of the PMOS channel width of the minimum inverter (Wn = 0.3µm)

tfri and tfre1 parameter variation

Total energy losses as a function of the number of inverters n and the minimum inverter PMOS channel width Wp. The area includes all the designs constrainted to a propagation delay lower than 1.15 ns.

iL>0 iL<0

7.7

The body diode of the NMOS power switch turns-on as a consequence of a premature cut

off of the power transistor

iL=0 detection circuit. Event detection

Inductor current charges the x-node parasitic capacitor and a positive voltage pulse appears in Vx

voltage, due to late cut off of the power transistor

iL=0 detection circuit. Circuit for time adjustment. Inductor current observer

iL>0

iL<0

N1

N2

7.9

iL=0 detection circuit Mixed-signal implementation in 0.25µm CMOS

Before adjustment After iL=0 adjustment

7.10

Time-domain performance of iL=0 detection circuit

2370 µm

P1

2630 µm

P2

N1N2 7.17

Complete integrated 3-level CMOS switching power converter

7.19

Full-transistor-level circuit results (I)

7.20

Full-transistor-level circuit results (II)

7.21

Full-transistor-level circuit results (III)

Experimental results

• Introduction and motivation• Series-connected multiphase multilevel buck converter

– Ideal topology. Amplifier and regulator operation– Self-driven low-floating-capacitor PFM-operated 3-level converter

• Design-space optimization• Mixed-signal implementation in 0.25µm TSMC CMOS

– Air-core bondingwire-based inductor, tapered buffer and transistor design– Inductor current zero-crossing detection circuit

• Conclusions

Outline

• Three-level converter results in favorable trade-offs in terms of decreasing the switching ripples, decreasing the switching frequency, reducing the size of the filter elements, increasing the converter open-loop bandwidth, or increasing the converter efficiency.

• The 3-level converter with low-Cx, self-biased drivers and operating in DCM/PFM has been presented as a candidate for DC-DC converter integration

• The use of the self-driving scheme to supply the drivers allows the use of thin-oxide transistors which increases the performance of the switches.

• Design optimization results in the 3-level converter outperforming the Buck converter.

Future research lines• Linear-assisted scheme for multilevel converters• Explore extending the approach to more intermediate levels• Use different modulations (e.g. asynchronous sigma delta)• Applying time optimal control

Conclusions