Placement

Physical Design Cycle

PartitioningPartitioning

Placement/Floorplanning

Placement/Floorplanning

RoutingRouting

Break the circuit up into

smaller segments

Place the segments on the chip

Layout thewire paths

2

Floorplanning and Placement• Partitioning:

Circuit divided into smaller modules• Floorplanning:

Block outlines are determined• Pin Assignment:

Pin locations are determined

• Placement to determine the locations of standard cells or logic

elements within each block

• Objectives: Total wire length Performance …

3

Placement Steps

• Global placement:Assigns general locations to movable objects

• Detailed placement: Incrementally improves object locations

− e.g., swapping cells

• Legalization: Before or during detailed placement:

− Align cells with rows and columns− Remove overlaps− Should minimize displacement from global placement

locations− Minimize impacts on interconnect length and circuit delay

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5

Placement Stages

Global Placement

Detailed Placement

Placement Stages

• Run time: Of the same order

• Memory: Global placement requires much more

• Parallelism: Global placement is difficult to parallelize

• Performance-driven: More accurate delay information in detailed placement

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Optimization Objectives

Total Wirelength

Wire Congestion

Signal Delay

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Consequences of Placement

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Consequences of Placement

A bad placement A good placement

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Placement Considerations

Module Shapes: Rectangular (Possibly Rectilinear) Aspect Ratio: H/W (constrained) L-Shape (complex)

Routing Considerations: Routability Routing Area Estimation

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Placement Considerations

High Performance Design: Critical Nets.

Pre-placed Modules: E.g. Clock buffer in the middle.

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Routing Length Estimation

• Interconnects: Unknown during placement Estimate

• Two-terminal nets: Euclidean distance Manhattan distance (rectilinear distance) Octilinear distance

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Wirelength estimation for a net

Objectives: Total Wirelength

Half-perimeterwirelength (HPWL)

HPWL = 9

4

5

Complete graph (clique)

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6

5

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Clique Length =(2/p)e cliquedM(e) = 14.5

Monotone chain

Chain Length = 12

63

3

Star model

Star Length = 15

83

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Objectives: Total Worelength

• Star:One pin as the sourceUseful for timing optimizationUses only p-1 edges

− advantageous for high pin count netsOverestimates wirelength

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Objectives: Total Wirelength

• Complete graph (clique): p pins

− No. of edges:

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Spanning tree:

− No. of edges:

p – 1

Normalization factor: p/2

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Objectives: Total Wirelength

Rectilinear minimumspanning tree (RMST)

RMST Length = 11

3

3

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Rectilinear Steinerminimum tree (RSMT)

RSMT Length = 10

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Rectilinear Steiner arborescence model (RSA)

RSA Length = 10

+5

3 +2

Single-trunk Steinertree (STST)

STST Length = 10

3

12

4

Wirelength estimation for a net (cont’d)

Objectives: Total Wirelength

• RSA: One pin as the source: s0

Path length from s0 to any si must be equal to s0~ si Manhattan distance

Minimum length RSA: NP-hard• STST:

Easy to construct Commonly used for estimation

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Preferred method: Half-perimeter wirelength (HPWL)

· Fast (order of magnitude faster than RSMT)

· RSMT: NP-hard

· = RSMT for 2- and 3-pin nets (70%-80% of nets in most modern designs)

· Margin of error for real circuits approx. 8% [Chu, ICCAD 04]

hwL HPWL

Objectives: Total Wirelength

RSMT Length = 10

31

6

HPWL = 9

4

5

w

h

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Objectives: Total Wirelength

Total wirelength with net weights (weighted wirelength)

• For a placement P estimated total weighted wirelength:

Pnet

netLnetwPL )()()(

31314462)()()( Pnet

netLnetwPL

a

b

d

c

f

eb1 e1

c1

a1

d1

d2 f2

f1

NetsWeights

N1 = (a1, b1, d2)w(N1) = 2

N2 = (c1, d1, f1)w(N2) = 4

N3 = (e1, f2)w(N3) = 1

w(net): weight of net

L(net): estimated wirelength of net

• Example:

Objectives: Congestion

• Two choices: Channel-based Channel segment-based

Channel

ChannelSegment

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Cost Function Using Channel For each channel i

wi: total number of nets whose bounding rectangles intersect with channel i:

w1=0

w2=2

w3=1

w4=

1

w5=

1

w6=

0Net-CrossingHistogram

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Assign a threshold value ti on the wiring capacity for each channel i.

− Cost function =

Total wire length + a Si(max{wi-ti , 0})2

Cost Function Using Channel

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Cost FunctionUsing Channel Segment

• For each net j,Rj : bounding rectangle

pj : half perimeter of Rj

lj : number of channel segments that intersected or enclosed by Rj.

• Expected occupancy of net j in each segments

pj / lj• wi of a segment i =

sum of all the expected occupancy in i23

Cost Function Using Channel Segment

Cost function = Total wirelength

+ aSi (max{wi-ti , 0})2

Expected Occupancy

= 2/4 Expected Occupancy

= 3/7

wi = 2/4+3/7

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Objectives: Delay

• Delay:Static timing analysis:

− For each path p, if delay(p) > timing budget (p)Timing is violated

- details: later

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Placement Problem Formulation

Blocks: B1, …, Bn Bi:(wi, hi)

Nets: N1, …, Nm

Net Length Estimation for Ni: Li

Rectangular Spaces for Routing: Q1, …, Qk

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Placement Problem Formulation

NP-Complete Problem

Find the position and orientation of all Bi’s such that:

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Macrocell Placement

• Different Block Sizes and Shapes.• Primary Objective Function: Area.

The main cause of area waste: non-regularity.

• Opposite to Connection Length Objective?

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Standard-Cell Placement• Equal Height Cells Easier• Placement in Rows.• Area Minimization:

Minimize Total Height Minimize Widest Width (Balance in Row Widths)

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Gate Array Placement• Mapping Components to Gates.

Inputs: − A set of blocks: {B1, …, Bn},

− A set of slots: {S1, …, Sr} (r >= n)

Objective:− Map Bi’s to Sj’s such that no two blocks map onto one slot

− And the result is routable.

• e.g. FPGA.

Customized WiringPrefabricated gates

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Placement Algorithms Classification

Constructive Iterative

Improvement

Global Placement Algorithms

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Placement Algorithms Classification

DeterministicStochastic

Global Placement Algorithms

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Placement Algorithms Classification

Simulation-Based

Analytical

Global Placement Algorithms

Partitioning-Based

.…

.…

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Placement Algorithms Classification

Simulation-Based

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Simulated annealing

Simulated evolution

Force-directed

Neural networks

….

Placement Algorithms Classification

Partitioning-Based

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Breuer Min-cut

Terminal propagation

Dragon (UCLA)

Capo (Michigan)

….

Placement Algorithms Classification

Analytical

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Quadratic placement

ILP-based

….