Embedded System Design and Synthesis Robert Dick http://ziyang.eecs.northwestern.edu/ ∼ dickrp/esds-two-week Department of Electrical Engineering and Computer Science Northwestern University Office at Tsinghua University: 9–310 East Main Building Power and temperature Dynamic power consumption Temperature Permanent faults Leakage power consumption Performance Transient faults Process variation dI/dt wear wear heat carrier concentration severe wear carrier mobility, threshold voltage heat reduced frequency dI/dt Battery depletion rate and electricity cost Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Definitions Temperature: Average kinetic energy of particle Heat: Transfer of this energy Heat always flows from regions of higher temperature to regions of lower temperature Particles move What happens to a moving particle in a lattice? 5 Robert Dick Embedded System Design and Synthesis Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Acoustic phonons Lattice structure Transverse and longitudinal waves Electron–phonon interactions Effect of carrier energy increasing beyond optic phonon energy? 6 Robert Dick Embedded System Design and Synthesis Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Optic phonons Minimum frequency, regardless of wavelength Only occur in lattices with more than one atom per unit cell Optic phonons out of phase from primitive cell to primitive cell Positive and negative ions swing against each other Low group velocity Interact with electrons Importance in nanoscale structure modeling? 7 Robert Dick Embedded System Design and Synthesis Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Nanostructure heat transfer Boundary scattering and superlattices Quantum effects when phonon spectra of materials do not match Splitting 8 Robert Dick Embedded System Design and Synthesis Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Why do wires get hot? Scattering of electrons due to destructive interference with waves in the lattice What are these waves? What happens to the energy of these electrons? What happens when wires start very, very cool? What is electrical resistance? What is thermal resistance? 9 Robert Dick Embedded System Design and Synthesis Power consumption Homework Power and temperature Power consumption modeling Embedded system power consumption optimization Why do transistors get hot? Scattering of electrons due to destructive interference with waves in the lattice Where do these waves come from? Where do the electrons come from? Intrinsic carriers Dopants What happens as the semiconductor heats up? Carrier concentration increases Carrier mobility decreases Threshold voltage decreases 10 Robert Dick Embedded System Design and Synthesis
Transcript
Embedded System Design and Synthesis
Robert Dick
http://ziyang.eecs.northwestern.edu/∼dickrp/esds-two-weekDepartment of Electrical Engineering and Computer Science
Northwestern University
Office at Tsinghua University: 9–310 East Main Building
Power and temperature
Dynamic power
consumption
Temperature
Permanent
faults
Leakage power
consumption
Performance
Transient
faultsProcess variation
dI/dt wearwear
heat
carrier
concentration
severe
wear
carrier mobility,
threshold voltage
heatreduced
frequencydI/dt
Battery depletion rate
and electricity cost
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Definitions
Temperature: Average kinetic energy of particle
Heat: Transfer of this energy
Heat always flows from regions of higher temperature to regionsof lower temperature
Particles move
What happens to a moving particle in a lattice?
5 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Acoustic phonons
Lattice structure
Transverse and longitudinal waves
Electron–phonon interactions
Effect of carrier energy increasing beyond optic phonon energy?
6 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Optic phonons
Minimum frequency, regardless of wavelength
Only occur in lattices with more than one atom per unit cell
Optic phonons out of phase from primitive cell to primitive cell
Positive and negative ions swing against each other
Low group velocity
Interact with electrons
Importance in nanoscale structure modeling?
7 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Nanostructure heat transfer
Boundary scattering and superlattices
Quantum effects when phonon spectra of materials do not match
Splitting
8 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Why do wires get hot?
Scattering of electrons due to destructive interference with wavesin the lattice
What are these waves?
What happens to the energy of these electrons?
What happens when wires start very, very cool?
What is electrical resistance?
What is thermal resistance?
9 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Why do transistors get hot?
Scattering of electrons due to destructive interference with wavesin the lattice
Where do these waves come from?
Where do the electrons come from?
Intrinsic carriersDopants
What happens as the semiconductor heats up?
Carrier concentration increasesCarrier mobility decreasesThreshold voltage decreases
10 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Cooling
conductheat to
heatsink
Heatpipes Processorgenerates
heatFan forcesair through
heatsink
Heatsinkhas highsurface
area
Heatpipesconductheat to
heatsink
Processorgenerates
heatair throughFan forces
heatsink
Heatsinkhas highsurface
area
11 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Power consumption trends
Initial optimization at transistor level
Further research-driven gains at this level difficult
Research moved to higher levels, e.g., RTL
Trade area for performance and performance for power
Clock frequency gains linear
Voltage scaling VDD2 – very important
13 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Power consumption in synchronous CMOS
P = PSWITCH + PSHORT + PLEAK
PSWITCH = C · VDD2 · f · A
† PSHORT =b
12(VDD − 2 · VT )3 · f · A · t
PLEAK = VDD · (ISUB + IGATE + IJUNCTION + IGIDL)
C : total switched capacitance VDD : operating voltage
f : switching frequency A : switching activity
b : MOS transistor gain VT : threshold voltage
t : rise/fall time of inputs
† PSHORT usually ≤ 10% of PSWITCH
Smaller as VDD → VT
14 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Adiabatic charging
Voltage step function implies E = CVCAP2/2
Instead, vary voltage to hold current constant:E = CVCAP
2 · RC/t
Lower energy if T > 2RC
Impractical when leakage significant
15 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Wiring power consumption
In the past, transistor power ≫ wiring power
Process scaling ⇒ ratio changing
Conventional CAD tools neglect wiring power
Indicate promising areas of future research
16 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Leakage
xxxxx x
B
DSG
n+ n+
Gate Leakage Subthreshold Leakage
Junction LeakageGIDL Leakage
Punchthrough Leakage
17 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Subthreshold leakage current
Isubthreshold = AsW
LvT
2
(
1 − e−VDS
vT
)
e(VGS−Vth)
nvT
where As is a technology-dependent constant,
Vth is the threshold voltage,
L and W are the device effective channel length and width,
VGS is the gate-to-source voltage,
n is the subthreshold swing coefficient for the transistor,
VDS is the drain-to-source voltage, and
vT is the thermal voltage.
A. Chandrakasan, W.J. Bowhill, and F. Fox. Design of High-Performance
Microprocessor Circuits. IEEE Press, 2001
18 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Simplified subthreshold leakage current
VDS ≫ vT and vT = kTq
. q is the charge of an electron. Therefore,equation can be simplified to
Isubthreshold = AsW
L
(
kT
q
)2
eq(VGS−Vth)
nkT (1)
19 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Exponential?
2 0 4 0 6 0 8 0 1 0 0 1 2 00 . 5
1
1 . 5
2
2 . 5
3
3 . 5
4
4 . 5
5
5 . 5
Temperature ( Co)
Norm
alize
d le
aka
ge
va
lue
C 7 5 5 2 H S P I C E
C 7 5 5 2 L inear M ode l
C 7 5 5 2 P W L 3
S R A M H S P I C E
S R A M L i nea r M ode l
S R A M P W L 3
20 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Piece-wise linear error
P W L 1 P W L 2 P W L 3 P W L 4 P W L 5 P W L 1 0 P W L 1 50
1
2
3
4
5
6
Piece−wise linear leakage model name
Le
aka
ge
mo
de
l e
rro
r (%)
C 7 5 5 2 W o r s t
2 M x 3 2 S R A M W o r s t
C 7 5 5 2 A v g .
2 M x 3 2 S R A M A v g .
21 Robert Dick Embedded System Design and Synthesis
Gate leakage
Igate = WLAJ
(
Toxr
Tox
)ntVgVaux
T 2ox
e−BTox (a−b|Vox |)(1+c|Vox |)
where AJ ,B, a, b, and c are technology-dependent constants,
nt is a fitting parameter with a default value of one,
Vox is the voltage across gate dielectric,
Tox is gate dielectric thickness,
Toxr is the reference oxide thickness,
Vaux is an auxiliary function that approximates the density oftunneling carriers and available states, and
Vg is the gate voltage.
K. M. Cao, W. C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and
C. Hu. BSIM4 gate leakage model including source-drain partition. In IEDM
Technology Dig., pages 815–818, December 2000
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Design level power savings
System level
Behavior level
Register−transfer level
Logic level
Layout level
Transistor level
Power reduction opportunities Power analysis iteration times
10−20X
2−5X
20 − 50%
seconds − minutes
minutes − hours
hours − days
Incre
asin
g p
ow
er
savin
gs
Decre
asin
g d
esig
n ite
ration tim
es
From Anand Raghunathan
23 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Power and temperaturePower consumption modelingEmbedded system power consumption optimization
Power consumption conclusions
Voltage scaling is currently the most promising low-levelpower-reduction method: V 2 dependence.
Reduce temperature or increase threshold to reduce leakage
Power/clock gating
System-level power management, prediction
28 Robert Dick Embedded System Design and Synthesis
Power consumptionHomework
Sensor networking and compression references
Lan Bai, Lei Yang, and Robert P. Dick. AutomatedCompile-Time and Run-Time Techniques to Increase UsableMemory in MMU-Less Embedded Systems. In Proc. Int. Conf.
Compilers, Architecture & Synthesis for Embedded Systems,pages 125–135, October 2006
Changyun Zhu, Zhenyu Gu, Li Shang, Robert P. Dick, andRobert Knobel. Towards an ultra-low-power architecture usingsingle-electron tunneling transistors. In Proc. Design Automation
Conf., pages 312–317, June 2007
Assignment: Write a short paragraph describing the most importantpoints in both of these articles.
30 Robert Dick Embedded System Design and Synthesis
