PPC440EPx/GRx Embedded Processor User’s...

Part Number 440EPx/GRx

Revision 1.15 September 22, 2008

440EPx/GRxPPC440EPx/GRX Embedded Processor

Preliminary Users Manual

PPC440EPx/GRx Embedded Processor

Users Manual

AMCC Proprietary 1


Preliminary Users ManualPPC440EPx/GRx Embedded Processor

Applied Micro Circuits Corporation6310 Sequence Drive, San Diego, CA 92121

Phone: (408) 450-9333 (858) 535-6517 Fax: (800) 840-6055http://www.amcc.com ([email protected])

AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice andwarrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest availabledata sheet. Please consult AMCCs Term and Conditions of Sale for its warranties and other terms, conditions andlimitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers toobtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC doesnot assume any liability arising out of the application or use of any product or circuit described herein, neither does it conveyany license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in placeof those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BESUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICALAPPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright 2007 Applied Micro Circuits Corpora-tion. All Rights Reserved.

2 AMCC Proprietary



Contents

Figures .......................................................................................................................................... 25

Tables ........................................................................................................................................... 43

About This Book .......................................................................................................................... 49

Part I. Introduction ....................................................................................................................... 53

1. Overview .................................................................................................................................. 551.1 PPC440EPx and PPC440GRx Differences ..................................................................................... 55

2. On-Chip Buses ........................................................................................................................ 572.1 Processor Local Bus ........................................................................................................................ 57

2.1.1 PLB Features ......................................................................................................................... 572.1.2 PLB Master and Slave Assignments ...................................................................................... 582.1.3 PLB Master Priority Assignment ............................................................................................ 59

2.1.3.1 Alternate PLB4 Master Priority Register 0 (SDR0_AMP0) ............................................ 602.1.3.2 Alternate PLB3 Master Priority Register 1 (SDR0_AMP1) ............................................ 622.1.3.3 PPC440 CPU Control Register (SDR0_CP440) ............................................................ 632.1.3.4 PLB4 Master Interrupt Request Registers 0 and 1 (SDR0_MIRQ0, SDR0_MIRQ1) . 642.1.3.5 PLB Slave Address Pipeline Register (SDR0_SLPIPE0) .............................................. 67

2.1.4 PLB4 Arbiter ........................................................................................................................... 682.1.4.1 PLB4 Arbiters 0 and 1 Registers .................................................................................... 692.1.4.2 PLB4 Arbiter Revision ID Register (PLB4A0_REVID) ................................................... 692.1.4.3 PLB4 Arbiter Control Register (PLB4An_ACR) .............................................................. 702.1.4.4 PLB4 Error Status Register Low (PLB4An_ESRL) ......................................................... 732.1.4.5 PLB4 Error Address Register Low (PLB4An_EARL) ...................................................... 752.1.4.6 PLB4 Error Address Register High (PLB4An_EARH) .................................................... 752.1.4.7 PLB4 Crossbar Control Register (PLB4A0_CCR) .......................................................... 75

2.1.5 PLB4 to PLB3 Bridge Registers (Bridge Out 0) ..................................................................... 762.1.5.1 PLB4 to PLB3 Bridge Error Address Register Low (P4P3BO0_BEARL) ....................... 772.1.5.2 PLB4 to PLB3 Bridge Error Address Register High (P4P3BO0_BEARH) ..................... 772.1.5.3 PLB4 to PLB3 Bridge Error Status Register 0 (P4P3BO0_BESR0) .............................. 772.1.5.4 PLB4 to PLB3 Bridge Error Status Register 1 (P4P3BO0_BESR1) ............................... 802.1.5.5 PLB4 to PLB3 Bridge Configuration Register (P4P3BO0_CFG) .................................... 822.1.5.6 PLB4 to PLB3 Bridge Priority Incrementation Counter Register (P4P3BO0_PICR) ....... 832.1.5.7 PLB4 to PLB3 Bridge Parity Error Interrupt Register (P4P3BO0_PEIR) ........................ 842.1.5.8 PLB4 to PLB3 Bridge Revision ID Register (P4P3BO0_REVID) .................................... 84

2.1.6 PLB3 to PLB4 Bridge Registers (Bridge In 0) ........................................................................ 842.1.6.1 PLB3 to PLB4 Bridge Error Address Register Low (P3P4BI0_BEARL) ......................... 852.1.6.2 PLB3 to PLB4 Bridge Error Address Register High (P3P4BI0_BEARH) ....................... 852.1.6.3 PLB3 to PLB4 Bridge Error Status Register 0 (P3P4BI0_BESR0) ................................ 852.1.6.4 PLB3 to PLB4 Bridge Error Status Register 1 (P3P43BI0_BESR1) ............................... 872.1.6.5 PLB3 to PLB4 Bridge Configuration Register (P3P4BI0_CFG) ...................................... 882.1.6.6 PLB3 to PLB4 Bridge Priority Incrementation Counter Register (P3P4BI0_PICR) ........ 892.1.6.7 PLB3 to PLB4 Bridge Parity Error Interrupt Register (P3P4BI0_PEIR) .......................... 902.1.6.8 PLB3 to PLB4 Bridge Revision ID Register (P3P4BI0_REVID) ..................................... 90

2.1.7 PLB4 to OPB Bridge Registers .............................................................................................. 902.1.7.1 PLB4 to OPB Bridge Error Status Register 0 (PLB42OPBx_BESR0) ............................ 912.1.7.2 PLB4 to OPB Bridge Error Address Register Low (PLB42OPBx_BEARL) .................... 932.1.7.3 PLB4 to OPB Bridge Error Address Register High (PLB42OPBx_BEARH) ................... 93

AMCC Proprietary 3



2.1.7.4 PLB4 to OPB Bridge Error Status Register 1(PLB42OPBx_BESR1) ............................. 942.1.7.5 PLB4 to OPB Bridge Configuration Register (PLB42OPBx_CFG) ................................. 952.1.7.6 PLB4 to OPB Bridge Burst Latency Timer (PLB42OPBx_LATENCY) ............................ 952.1.7.7 PLB4 to OPB Bridge Revision ID (PLB42OPBx_REVID) .............................................. 96

2.1.8 PLB3 Arbiter Registers ........................................................................................................... 962.1.8.1 PLB3 Arbiter Revision ID Register (PLB3A0_REVID) ................................................... 962.1.8.2 PLB3 Error Status Register (PLB3A0_BESR) ................................................................ 972.1.8.3 PLB3 Error Address Register (PLB3A0_BEAR) ............................................................. 982.1.8.4 PLB3 Arbiter 0 Control Register (PLB3A0_ACR) ........................................................... 98

2.1.9 PLB3 to OPB Bridge Registers ............................................................................................ 992.1.9.1 PLB3 to OPB Bridge Error Status Register 0 (PLB32OPB0_BESR0) .......................... 1002.1.9.2 PLB3 to OPB Bridge Error Address Register (PLB32OPB0_BEAR) ............................ 1012.1.9.3 PLB3 to OPB Bridge Revision ID Register (PLB32OPB0_REVID) .............................. 1012.1.9.4 PLB3 to OPB Bridge Error Status Register 1 (PLB32OPB0_BESR1) .......................... 102

2.2 On-Chip Peripheral Bus ................................................................................................................. 1022.2.1 OPB Features ...................................................................................................................... 1022.2.2 OPB Master Assignments .................................................................................................... 1032.2.3 OPB Arbiter Registers .......................................................................................................... 103

2.2.3.1 OPB Arbiter Priority Register (OPBAx_PR) ................................................................. 1032.2.3.2 OPB Arbiter Control Register (OPBAx_CR) ................................................................. 104

2.2.4 OPB-to-PLB4 Bridge Registers ............................................................................................ 1052.2.4.1 OPB-to-PLB4 Bridge Control Register (OPB2PLB40_BCTRL) .................................... 1052.2.4.2 OPB-to-PLB4 Bridge Status Register (OPB2PLB40_BSTAT) ..................................... 1052.2.4.3 OPB-to-PLB4 Bridge Error Address Register Low (OPB2PLB40_BEARL) .................. 1062.2.4.4 OPB-to-PLB4 Bridge Error Address Register High (OPB2PLB40_BEARH) ................ 1062.2.4.5 OPB-to-PLB4 Bridge Revision ID Register (OPB2PLB40_REVID) .............................. 106

2.3 Device Control Register (DCR) Bus .............................................................................................. 107

Part II. PPC440EPx/GRx RISC Processor ................................................................................ 109

3. Programming Model ............................................................................................................. 1113.1 Storage Addressing ....................................................................................................................... 1113.2 User and Privileged Programming Models .................................................................................... 111

3.2.1 Device Control Registers ..................................................................................................... 1153.2.2 Memory Mapped Registers .................................................................................................. 125

3.3 Instruction Classes ........................................................................................................................ 138

4. FPU Programming Model ..................................................................................................... 1394.1 Storage Addressing ....................................................................................................................... 139

4.1.1 Storage Operands ................................................................................................................ 1394.1.2 Effective Address Calculation .............................................................................................. 1404.1.3 Data Storage Addressing Modes ......................................................................................... 140

4.2 Floating-Point Exceptions .............................................................................................................. 1414.3 Floating-Point Registers ................................................................................................................ 141

4.3.1 Register Types ..................................................................................................................... 1424.3.1.1 Floating-Point Registers (FPR0:FPR31) ....................................................................... 1424.3.1.2 Floating-Point Status and Control Register (FPSCR) .................................................. 142

4.4 Floating-Point Data Formats .......................................................................................................... 1454.4.1 Value Representation ........................................................................................................... 1464.4.2 Binary Floating-Point Numbers ............................................................................................ 147

4.4.2.1 Normalized Numbers .................................................................................................... 1474.4.2.2 Denormalized Numbers ................................................................................................ 1474.4.2.3 Zero Values .................................................................................................................. 147

4 AMCC Proprietary



4.4.3 Infinities ................................................................................................................................ 1484.4.3.1 Not a Numbers .............................................................................................................. 148

4.4.4 Sign of Result ....................................................................................................................... 1494.4.5 Normalization and Denormalization ..................................................................................... 1494.4.6 Data Handling and Precision ................................................................................................ 1494.4.7 Rounding .............................................................................................................................. 150

4.5 Floating-Point Execution Models ................................................................................................... 1514.5.1 Execution Model for IEEE Operations .................................................................................. 1524.5.2 Execution Model for Multiply-Add Type Instructions ............................................................ 154

4.6 Floating-Point Instructions ............................................................................................................. 1554.6.1 Instructions By Category ...................................................................................................... 1554.6.2 Load and Store Instructions ................................................................................................. 1564.6.3 Floating-Point Store Instructions .......................................................................................... 1574.6.4 Floating-Point Move Instructions .......................................................................................... 1594.6.5 Floating-Point Arithmetic Instructions ................................................................................... 159

4.6.5.1 Floating-Point Multiply-Add Instructions ....................................................................... 1594.6.6 Floating-Point Rounding and Conversion Instructions ......................................................... 1604.6.7 Floating-Point Compare Instructions .................................................................................... 1604.6.8 Floating-Point Status and Control Register Instructions ...................................................... 161

5. Instruction and Data Caches ............................................................................................... 163

6. Memory Management ........................................................................................................... 165

Part III. PPC440EPx/GRx System Operations ......................................................................... 167

7. Reset and Initialization ......................................................................................................... 1697.1 Reset Signals ................................................................................................................................ 1697.2 Reset Types .................................................................................................................................. 169

7.2.1 CPU Reset ........................................................................................................................... 1697.2.2 Chip Reset ........................................................................................................................... 1697.2.3 System Reset ....................................................................................................................... 170

7.3 Processor Core State After Reset ................................................................................................. 1717.4 PPC440EPx/GRx Chip Initialization .............................................................................................. 175

7.4.1 Initial Configuration Register (CPR0_ICFG) ........................................................................ 1767.4.2 System Device Control Registers ........................................................................................ 176

7.4.2.1 Electronic Chip ID Register 0 (SDR0_ECID0) ............................................................. 1777.4.2.2 Electronic Chip ID Register 1 (SDR0_ECID1) ............................................................. 1777.4.2.3 Electronic Chip ID Register 2 (SDR0_ECID2) ............................................................. 1777.4.2.4 Electronic Chip ID Register 3 (SDR0_ECID3) ............................................................. 1777.4.2.5 Pin Function Control Register 0 (SDR0_PFC0) ........................................................... 1777.4.2.6 Pin Function Control Register 1 (SDR0_PFC1) ........................................................... 1787.4.2.7 GPIO Multiplexing Register (SDR0_PFC4) ................................................................. 1797.4.2.8 Slave Address Pipeline Register (SDR0_SLPIPE0) ..................................................... 1797.4.2.9 Soft Reset Registers (SDR0_SRST0 and SDR0_SRST1) .......................................... 1797.4.2.10 Miscellaneous Function Register (SDR0_MFR) ......................................................... 1817.4.2.11 DDR Configuration Register (SDR0_DDRCFG) ......................................................... 182

7.5 Initialization Software Requirements ............................................................................................. 182

8. Bootstrap Controller ............................................................................................................. 1878.1 Bootstrap Configuration ................................................................................................................. 1878.2 Bootstrap Options .......................................................................................................................... 1898.3 IIC Bootstrap Operations ............................................................................................................... 193

AMCC Proprietary 5



8.3.1 Performance ......................................................................................................................... 1948.4 IIC Bootstrap Registers ................................................................................................................. 196

8.4.1 Pin Strapping Register (SDR0_PINSTP) ............................................................................. 1978.4.2 Serial Device Controller Settings Register (SDR0_SDCS0) ................................................ 1978.4.3 Serial Device Strap Register 0 (SDR0_SDSTP0) ................................................................ 1988.4.4 Serial Device Strap Register 1 (SDR0_SDSTP1) ................................................................ 2008.4.5 Read-Only Equivalent of SDR0_CUST0 (SDR0_SDSTP2) ................................................. 2018.4.6 Read-Only Version of SDR0_CUST1 (SDR0_SDSTP3) ..................................................... 2028.4.7 Customer Configuration Register 0 (SDR0_CUST0) ........................................................... 2038.4.8 Custom Configuration Register 1 (SDR0_CUST1) .............................................................. 2048.4.9 EBC Configuration Register (SDR0_EBC0) ......................................................................... 204

9. Universal Interrupt Controller ............................................................................................. 2059.1 UIC Overview ................................................................................................................................ 2059.2 UIC Features ................................................................................................................................. 2059.3 UIC Interrupt Assignments ............................................................................................................ 2069.4 Interrupt Programmability .............................................................................................................. 2099.5 UIC Registers ................................................................................................................................ 210

9.5.1 UIC0 Status Register (UIC0_SR) ......................................................................................... 2109.5.2 UIC1 Status Register (UIC1_SR) ........................................................................................ 2129.5.3 UIC2 Status Register (UIC2_SR) ........................................................................................ 2149.5.4 UIC0 Enable Register (UIC0_ER) ....................................................................................... 2159.5.5 UIC1 Enable Register (UIC1_ER) ....................................................................................... 2189.5.6 UIC2 Enable Register (UIC2_ER) ....................................................................................... 2209.5.7 UIC0 Critical Register (UIC0_CR) ....................................................................................... 2219.5.8 UIC1 Critical Register (UIC1_CR) ....................................................................................... 2239.5.9 UIC2 Critical Register (UIC2_CR) ....................................................................................... 2259.5.10 UIC0 Polarity Register (UIC0_PR) .................................................................................... 2269.5.11 UIC1 Polarity Register (UIC1_PR) .................................................................................... 2299.5.12 UIC2 Polarity Register (UIC2_PR) .................................................................................... 2319.5.13 UIC0 Trigger Register (UIC0_TR) ..................................................................................... 2329.5.14 UIC1 Trigger Register (UIC1_TR) ..................................................................................... 2349.5.15 UIC2 Trigger Register (UIC2_TR) ..................................................................................... 2379.5.16 UIC0 Masked Status Register (UIC0_MSR) ..................................................................... 2379.5.17 UIC1 Masked Status Register (UIC1_MSR) ..................................................................... 2409.5.18 UIC2 Masked Status Register (UIC2_MSR) ..................................................................... 2429.5.19 UIC0 Vector Configuration Register (UIC0_VCR) ............................................................. 2439.5.20 UIC1 Vector Configuration Register (UIC1_VCR) ............................................................. 2439.5.21 UIC0 Vector Register (UIC0_VR) ...................................................................................... 244

9.5.21.1 Using the Value in UIC0_VR as a Vector Address or Entry Table Lookup ................. 2449.5.21.2 Vector Generation Scenarios ...................................................................................... 245

9.5.22 UIC1 Vector Register (UIC1_VR) ...................................................................................... 2459.5.22.1 Using the Value in UIC1_VR as a Vector Address or Entry Table Lookup ................. 2469.5.22.2 Vector Generation Scenarios ...................................................................................... 246

10. Interrupts and Exceptions ................................................................................................. 247

11. Floating Point Unit Interrupts and Exceptions ................................................................ 24911.1 Floating-Point Exceptions ............................................................................................................ 24911.2 Exceptions List ............................................................................................................................ 25011.3 Floating-Point Interrupts .............................................................................................................. 252

11.3.1 Floating-Point Unavailable Interrupt ................................................................................... 25211.4 Floating-Point Exception Behavior .............................................................................................. 253

6 AMCC Proprietary



11.4.1 Invalid Operation Exception ............................................................................................... 25311.4.1.1 Action .......................................................................................................................... 254

11.4.2 Zero Divide Exception ........................................................................................................ 25511.4.2.1 Action .......................................................................................................................... 255

11.4.3 Overflow Exception ............................................................................................................ 25511.4.3.1 Action .......................................................................................................................... 255

11.4.4 Underflow Exception .......................................................................................................... 25611.4.4.1 Action .......................................................................................................................... 256

11.4.5 Inexact Exception ............................................................................................................... 25711.4.5.1 Action .......................................................................................................................... 257

11.5 Exception Priorities for Floating-Point Load and Store Instructions ............................................ 25811.6 Exception Priorities for other Floating-Point Instructions ............................................................. 25811.7 QNaN ........................................................................................................................................... 25911.8 Updating FPRs on Exceptions ..................................................................................................... 25911.9 Floating-Point Status and Control Register ................................................................................. 25911.10 Updating the CR ........................................................................................................................ 260

11.10.1 CR Fields ......................................................................................................................... 26011.10.2 Updating CR Fields .......................................................................................................... 26011.10.3 Generation of QNaN Results ........................................................................................... 261

12. Timer Facilities .................................................................................................................... 263

13. General Purpose Timers .................................................................................................... 26513.1 GPT Features .............................................................................................................................. 26513.2 Time Base Counter ...................................................................................................................... 26513.3 Compare Timers .......................................................................................................................... 265

13.3.1 Compare Timer Interrupt .................................................................................................... 26613.4 GPT Registers ............................................................................................................................. 266

13.4.1 GPT Time Base Counter Register (GPT0_TBC) ............................................................... 26713.4.2 GPT Interrupt Mask Register (GPT0_IM) ........................................................................... 26813.4.3 GPT Interrupt Status Register (GPT0_ISS and GPT0_ISC) .............................................. 26813.4.4 GPT Interrupt Enable Register (GPT0_IE) ......................................................................... 26913.4.5 GPT Compare Timer Registers (GPT0_COMP0:GPT0_COMP6) ..................................... 27013.4.6 GPT Compare Mask Registers (GPT0_MASK0:GPT0_MASK6) ...................................... 27013.4.7 GPT Down Count Timer (GPT0_DCT0) ............................................................................. 27013.4.8 GPT Down Count Timer Interrupt Status (GPT0_DCIS) .................................................... 271

14. Clocking ............................................................................................................................... 27314.1 System Clocking .......................................................................................................................... 274

14.1.1 Feedback Selection ............................................................................................................ 27514.1.2 VCO Frequency and M Value for SYS PLL ...................................................................... 27514.1.3 SYS PLL TUNE Setting ...................................................................................................... 27714.1.4 IIC Bootstrap Controller Clocking ....................................................................................... 27714.1.5 Clocks For Off Chip Use .................................................................................................... 27714.1.6 SYS PLL Strapping ............................................................................................................ 27814.1.7 PLL Bypass (Emulation Mode) ........................................................................................... 27814.1.8 CPU / PLB Frequency N:1 Setting ..................................................................................... 27814.1.9 Choosing System Clock Ratios .......................................................................................... 27914.1.10 System Clock Ratio Examples ........................................................................................ 279

14.1.10.1 PLL Local Feedback Example .................................................................................. 27914.1.10.2 CPU Feedback Example .......................................................................................... 28014.1.10.3 PerClk Feedback Example ....................................................................................... 281

14.2 PCI Clocking ................................................................................................................................ 282

AMCC Proprietary 7



14.2.1 PCI Adapter Applications ................................................................................................... 28314.3 Clocking Registers ....................................................................................................................... 284

14.3.1 Clock/Power-On Reset Configuration Address Register (CPR0_CFGADDR) ................... 28414.3.2 Clock/Power-On Reset Configuration Data Register (CPR0_CFGDATA) ......................... 28414.3.3 Clocking Update Register (CPR0_CLKUPD) ..................................................................... 28514.3.4 PLL Control Register (CPR0_PLLC0) ................................................................................ 28514.3.5 PLL Divisor Register (CPR0_PLLD0) ................................................................................ 28614.3.6 Primary A Divisor Register (CPR0_PRIMAD0) .................................................................. 28714.3.7 Primary B Divisor Register (CPR0_PRIMBD0) .................................................................. 28814.3.8 OPB Clock Divisor Register (CPR0_OPBD0) .................................................................... 28814.3.9 Peripheral Clock Divisor Register (CPR0_PERD0) ........................................................... 28814.3.10 MAL Clock Divisor Register (CPR0_MALD) .................................................................... 28914.3.11 Sync PCI Clock Divisor Register (CPR0_SPCID) ............................................................ 289

15. Clock and Power Management .......................................................................................... 29115.1 Overview ...................................................................................................................................... 29115.2 CPM Registers ............................................................................................................................ 291

15.2.1 CPM Enable Registers (CPM0_ER and CPM1_ER) ...................................................... 29115.2.2 CPM Force Register (CPM0_FR and CPM1_FR) .......................................................... 29315.2.3 CPM Status Register (CPM0_SR and CPM1_SR) ......................................................... 294

16. Debug Facilities .................................................................................................................. 297

17. Security Function ............................................................................................................... 29917.1 Functional Description ................................................................................................................. 299

17.1.1 Block Diagram .................................................................................................................... 29917.1.2 PLB Interface ..................................................................................................................... 30017.1.3 Packet Engine .................................................................................................................... 301

17.1.3.1 Input/Output Buffer ..................................................................................................... 30117.1.3.2 Controller .................................................................................................................... 30117.1.3.3 Header and Trailer Processor ..................................................................................... 30117.1.3.4 Encryption/Decryption ................................................................................................. 30217.1.3.5 Hash Function ............................................................................................................. 30317.1.3.6 Command Queue and Context Registers ................................................................... 30317.1.3.7 Using the Packet Engine ............................................................................................ 303

17.1.4 DMA Controller ................................................................................................................... 30517.1.5 Public Key Accelerator and Public Key Memory ................................................................ 305

17.1.5.1 Operation .................................................................................................................... 30517.1.5.2 Functional Description ................................................................................................ 305

17.1.6 True Random Number Generator ...................................................................................... 30517.1.7 Pseudo Random Number Generator ................................................................................. 30517.1.8 Interrupt Controller ............................................................................................................. 30617.1.9 Device Controller ................................................................................................................ 306

17.2 Register Interface ........................................................................................................................ 30617.2.1 Byte Ordering ..................................................................................................................... 30617.2.2 Register Summary ............................................................................................................. 30617.2.3 CRYP0 SDR Control Register (SDR0_CRYP0) ................................................................. 31217.2.4 PE Control/Status Register (CRYP0_PE_CTLST) ............................................................. 31317.2.5 PE Source Address Register (CRYP0_PE_SOURCE) ...................................................... 31917.2.6 PE Destination Address Register (CRYP0_PE_DEST) ..................................................... 31917.2.7 PE SA Address Register (CRYP0_PE_SA) ....................................................................... 32017.2.8 PE Length Register (CRYP0_PE_LENGTH) ..................................................................... 32117.2.9 PE DMA Configuration Register (CRYP0_PE_DMA_CF) .................................................. 322

8 AMCC Proprietary



17.2.10 PE DMA Status Register (CRYP0_PE_DMA_ST) ........................................................... 32417.2.11 PE Packet Descriptor Ring Base Address Register (CRYP0_PE_PDR_BA) .................. 32617.2.12 PE Packet Result Ring Base Address Register (CRYP0_PE_RDR_BA) ........................ 32717.2.13 PE Ring Size and Offset Register (CRYP0_PE_RING_S) .............................................. 32817.2.14 PE Ring Poll Register (CRYP0_PE_RING_P) ................................................................. 32917.2.15 PE Internal Ring Status Register (CRYP0_PE_I_RING) ................................................. 33017.2.16 PE External Ring Status Register (CRYP0_PE_E_RING) ............................................... 33117.2.17 PE I/O Threshold Register (CRYP0_PE_IO_THR) .......................................................... 33117.2.18 PE Gather Particle Ring Base Address Register (CRYP0_PE_GATH) ........................... 33217.2.19 PE Scatter Particle Ring Base Address Register (CRYP0_PE_SCAT) ........................... 33217.2.20 PE Particle Ring Size Register (CRYP0_PE_PT_S) ....................................................... 33317.2.21 PE Particle Ring Configuration Register (CRYP0_PE_PT_CFG) .................................... 33317.2.22 PE Particle Descriptor Source Address Register (CRYP0_PE_PR_SCA) ...................... 33417.2.23 PE Particle Descriptor Source Control Register (CRYP0_PE_PR_SCC) ........................ 33517.2.24 PE Particle Destination Address Register (CRYP0_PE_PR_DTA) ................................. 33617.2.25 PE Particle Destination Control Register (CRYP0_PE_PR_DTC) ................................... 33717.2.26 SA Command 0 Register (CRYP0_SA_CMD_0) ............................................................. 33817.2.27 SA Command 1 Register (CRYP0_SA_CMD_1) ............................................................. 34217.2.28 SA Key x Low/High Registers (CRYP0_SA_KEYx_L/H) ................................................. 34617.2.29 SA Inner Hash Digest x Registers (CRYP0_SA_IH_Dx) ................................................. 34717.2.30 SA Inner Outer Digest x Registers (CRYP0_SA_OH_Dx) ............................................... 34817.2.31 SA IPsec SPI Register (CRYP0_SA_SPI) ....................................................................... 34917.2.32 SA IPsec Sequence Number Register (CRYP0_SA_SEQ) ............................................. 35017.2.33 SA IPsec Sequence Number Mask High/Low Registers (CRYP0_SA_SEQMKH/L) ....... 35117.2.34 SA Nonce Value Register (CRYP0_SA_NONCE) ......................................................... 35117.2.35 SA Pointer Register (CRYP0_SA_PNTR) ...................................................................... 35217.2.36 SA ARC4 i and j Pointer Register (CRYP0_SA_ARC4IJ) ............................................... 35217.2.37 SA ARC4 State Address Pointer Register (CRYP0_SA_ARC4SB) ................................ 35317.2.38 SA Initialization Vector Registers (CRYP0_SA_IV_x) ..................................................... 35317.2.39 SA Hash Byte Count Register (CRYP0_SA_HASH_B) .................................................. 35417.2.40 SA Inner Hash x (mirror of CRYP0_SA_IH_Dx) Registers (CRYP0_SA_IH_x) ........... 35417.2.41 SA ICV xHMAC Result Registers (CRYP0_SA_ICV_x) .............................................. 35517.2.42 TRNG Output Register (CRYP0_TRNG_DATA) ............................................................ 35617.2.43 TRNG Status Register (CRYP0_TRNG_STAT) ............................................................. 35617.2.44 TRNG Control Register (CRYP0_TRNG_CTRL) ............................................................ 35717.2.45 TRNG Entropy A Register (CRYP0_TRNG_ENTA) ....................................................... 35817.2.46 TRNG Entropy B Register (CRYP0_TRNG_ENTB) ........................................................ 35917.2.47 TRNG Test Seed x Registers (CRYP0_TRNG_Xx) ....................................................... 35917.2.48 TRNG Counter Register (CRYP0_TRNG_CNTR) .......................................................... 36017.2.49 TRNG Alarm Counter Register (CRYP0_TRNG_ALRM) ................................................. 36017.2.50 TRNG Configuration Register (CRYP0_TRNG_CFG) ..................................................... 36117.2.51 TRNG Test Read of LFSR 0 Low/High Registers (CRYP0_TRNG_LF0L/H) ................... 36217.2.52 TRNG Test Read of LFSR 1 Low/High Registers (CRYP0_TRNG_LF1L/H) ................... 36317.2.53 TRNG Triple DES Key 0 Low/High Registers (CRYP0_TRNG_K0_L/H) ......................... 36317.2.54 TRNG Triple DES Key 1 Low/High Registers (CRYP0_TRNG_K1_L/H) ......................... 36417.2.55 TRNG Initialization Vector Low/High Registers (CRYP0_TRNG_IV_L/H) ....................... 36417.2.56 PKA x Vector Address Register (CRYP0_PKA_x_PTR) .................................................. 36517.2.57 PKA x Vector Length Register (CRYP0_PKA_x_LEN) .................................................... 36517.2.58 PKA Shift Register (CRYP0_PKA_SHIFT) ...................................................................... 36617.2.59 PKA Function Code Register (CRYP0_PKA_FUNC) ....................................................... 36717.2.60 PKA Comparison Result Register (CRYP0_PKA_COMP) ............................................... 37017.2.61 PKA Quotient MSW Register (CRYP0_PKA_DIV) ........................................................... 37117.2.62 PKA Remainder MSW Register (CRYP0_PKA_MOD) .................................................... 372

AMCC Proprietary 9



17.2.63 Interrupt Unmasked and Masked Status Registers (CRYP0_INT_UNMSK/MSK) .... 37417.2.64 Interrupt Mask Register (CRYP0_INT_EN) ..................................................................... 37517.2.65 Interrupt Configuration Register (CRYP0_INT_CFG) ..................................................... 37617.2.66 Interrupt Force Descriptor Read Register (CRYP0_INT_DESRD) ................................. 37717.2.67 Interrupt Descriptor Count Register (CRYP0_INT_DESCT) ............................................ 37717.2.68 Device Control Register (CRYP0_DC_CTRL) ................................................................ 37817.2.69 Device ID Register (CRYP0_DC_DEVID) ....................................................................... 37817.2.70 Device Information Register (CRYP0_DC_DEVINF) ....................................................... 37917.2.71 DMA Source Address Register (CRYP0_DMA_USRC) .................................................. 38017.2.72 DMA Destination Address Register (CRYP0_DMA_UDST) ........................................... 38017.2.73 DMA Command Register (CRYP0_DMA_UCMD) ........................................................... 38117.2.74 DMA Configuration/Status Register (CRYP0_DMA_CFG) ............................................. 38217.2.75 PRNG Status Register (CRYP0_PRNG_STAT) ............................................................. 38317.2.76 PRNG Control Register (CRYP0_PRNG_CTRL) ............................................................ 38417.2.77 PRNG Seed Value L/H Registers (CRYP0_PRNG_SDL/H) ......................................... 38517.2.78 PRNG Key x Low/High Registers (CRYP0_PRNG_KxL/H) .......................................... 38517.2.79 PRNG Result x Registers (CRYP0_PRNG_RSx) ........................................................... 38617.2.80 PRNG LFSR Low/High Registers (CRYP0_PRNG_LFL/H) .......................................... 386

17.3 Buffer Interface ............................................................................................................................ 38717.3.1 ARC4 Buffer ....................................................................................................................... 38717.3.2 Input buffer ......................................................................................................................... 38717.3.3 Output Buffer ...................................................................................................................... 38717.3.4 Public Key Memory (PKM) ................................................................................................. 388

18. KASUMI Algorithm ............................................................................................................. 38918.1 Features ...................................................................................................................................... 38918.2 References .................................................................................................................................. 38918.3 Block Diagram ............................................................................................................................. 38918.4 Functional Description ................................................................................................................. 390

18.4.1 General Processing ............................................................................................................ 39018.4.1.1 KASUMI Mode ............................................................................................................ 39118.4.1.2 f8 Mode ....................................................................................................................... 39118.4.1.3 f9 Mode ....................................................................................................................... 392

18.4.2 Flow Control ....................................................................................................................... 39218.5 Register Interface ........................................................................................................................ 393

18.5.1 Byte Ordering ..................................................................................................................... 39318.5.2 Data Input/Output Register (KASU0_DATAIN0, KASU0_DATAOUT0) ......................... 39418.5.3 Data Input/Output Register (KASU0_DATAIN1, KASU0_DATAOUT1) ......................... 39418.5.4 Control/Status Register (KASU0_CTRL, KASU0_STAT) ............................................... 39518.5.5 Mode Register (KASU0_MODE) ........................................................................................ 39618.5.6 Key Registers (KASU0_KEYx) .......................................................................................... 39718.5.7 Count Register (KASU0_COUNT) .................................................................................... 39818.5.8 Configuration Register (KASU0_CONFIG) ....................................................................... 39818.5.9 Fresh Register (KASU0_FRESH) ..................................................................................... 399

18.6 Programing Examples ................................................................................................................. 39918.6.1 KASUMI Mode Example .................................................................................................... 39918.6.2 f8 Mode Example ............................................................................................................... 40018.6.3 f9 Mode Example ............................................................................................................... 401

Part IV. PPC440EPx/GRx Peripheral Functions and Interfaces ............................................. 403

19. DDR SDRAM Controller ...................................................................................................... 40519.1 Initialization Protocol ................................................................................................................... 405

10 AMCC Proprietary



19.2 Device Address Mapping ............................................................................................................. 40619.2.1 DDR SDRAM Address Fields ............................................................................................. 406

19.2.1.1 Default Address Structure ........................................................................................... 40619.2.1.2 Memory Mapping to Address Space ........................................................................... 40719.2.1.3 DDR Address Parameters for Common Organizations .............................................. 409

19.3 Register Interface ........................................................................................................................ 41019.3.1 DCR Access ....................................................................................................................... 41019.3.2 SDRAM Device Control Registers ..................................................................................... 41019.3.3 DCR Descriptions ............................................................................................................... 412

19.4 Clocking ....................................................................................................................................... 43419.5 Error Checking and Correction (ECC) ......................................................................................... 435

19.5.1 Controlling ECC ................................................................................................................. 43519.5.2 ECC Error Types ................................................................................................................ 43619.5.3 ECC and Read Operations ................................................................................................ 43719.5.4 ECC and Write Operations ................................................................................................. 43719.5.5 Syndrome Codes ............................................................................................................... 43819.5.6 Forcing an ECC Error Event .............................................................................................. 43819.5.7 Clearing a Reported ECC Event ........................................................................................ 439

19.6 Delay Compensation Circuit ........................................................................................................ 43919.7 Read Data Capture ...................................................................................................................... 44019.8 Write Data Timing ........................................................................................................................ 444

20. Internal SRAM Controller ................................................................................................... 44720.1 SRAM Controller Registers ......................................................................................................... 447

20.1.1 SRAM Bank Configuration Register (SRAM0_SB0CR) ..................................................... 44820.1.2 Bus Error Address Register (SRAM0_BEAR) .................................................................... 44820.1.3 Bus Error Status Register 0 (SRAM0_BESR0) .................................................................. 44920.1.4 Bus Error Status Register 1 (SRAM0_BESR1) .................................................................. 45020.1.5 Power Management Register (SRAM0_PMEG) ................................................................ 45220.1.6 Core ID Register (SRAM0_CID) ........................................................................................ 45220.1.7 Revision ID Register (SRAM0_REVID) .............................................................................. 45320.1.8 Data Parity Checking Register (SRAM0_DPC) .................................................................. 453

20.2 Errors ........................................................................................................................................... 45320.2.1 Protection Error .................................................................................................................. 453

20.2.1.1 BESR Field ................................................................................................................. 45320.2.2 Data Parity Error ................................................................................................................ 454

21. Peripheral Component Interconnect (PCI) Interface ....................................................... 45521.1 Features ...................................................................................................................................... 45521.2 Byte Ordering .............................................................................................................................. 45621.3 PCI Bridge Functional Blocks ...................................................................................................... 457

21.3.1 PLB-to-PCI Half-Bridge ...................................................................................................... 45721.3.2 PCI-to-PLB Half-Bridge ...................................................................................................... 45821.3.3 PCI Arbiter .......................................................................................................................... 458

21.4 PCI Bridge Address Mapping ..................................................................................................... 45921.4.1 PLB-to-PCI Address Mapping ............................................................................................ 45921.4.2 PCI-to-PLB Address Mapping ............................................................................................ 46121.4.3 PCI Target Map Configuration ........................................................................................... 462

21.5 PCI Bridge Transaction Handling ................................................................................................ 46221.5.1 PLB-to-PCI Transaction Handling ...................................................................................... 463

21.5.1.1 PCI Master Commands .............................................................................................. 46321.5.1.2 PLB Slave Read Handling .......................................................................................... 464

AMCC Proprietary 11



21.5.1.3 Prefetching .................................................................................................................. 46521.5.1.4 PLB Slave Write Handling .......................................................................................... 46521.5.1.5 Aborted PLB Requests ............................................................................................... 46521.5.1.6 Retried PCI Reads ...................................................................................................... 466

21.5.2 PCI-to-PLB Transaction Handling ...................................................................................... 46621.5.2.1 PLB Master Commands .............................................................................................. 46721.5.2.2 Handling of Reads from PCI Masters ......................................................................... 46721.5.2.3 Miscellaneous ............................................................................................................. 469

21.5.3 Completion Ordering .......................................................................................................... 46921.5.3.1 PCI Producer-Consumer Model .................................................................................. 470

21.5.4 Collision Resolution ............................................................................................................ 47021.5.5 PCI Control Register (SDR0_PCI0) ................................................................................... 470

21.6 PCI Bridge Configuration Registers ............................................................................................. 47121.6.1 PCI Bridge Register Summary ........................................................................................... 47121.6.2 PCI Bridge Local Configuration Registers .......................................................................... 473

21.6.2.1 PMM 0 Local Address Register (PCIL0_PMM0LA) .................................................... 47321.6.2.2 PMM 0 Mask/Attribute Register (PCIL0_PMM0MA) ................................................... 47321.6.2.3 PMM 0 PCI Low Address Register (PCIL0_PMM0PCILA) ......................................... 47421.6.2.4 PMM 0 PCI High Address Register (PCIL0_PMM0PCIHA) ........................................ 47421.6.2.5 PMM 1 Local Address Register (PCIL0_PMM1LA) .................................................... 47421.6.2.6 PMM 1 Mask/Attribute Register (PCIL0_PMM1MA) ................................................... 47421.6.2.7 PMM 1 PCI Low Address Register (PCIL0_PMM1PCILA) ......................................... 47521.6.2.8 PMM 1 PCI High Address Register (PCIL0_PMM1PCIHA) ........................................ 47521.6.2.9 PMM 2 Local Address Register (PCIL0_PMM2LA) .................................................... 47521.6.2.10 PMM 2 Mask/Attribute Register (PCIL0_PMM2MA) ................................................. 47521.6.2.11 PMM 2 PCI Low Address Register (PCIL0_PMM2PCILA) ....................................... 47621.6.2.12 PMM 2 PCI High Address Register (PCIL0_PMM2PCIHA) ...................................... 47621.6.2.13 PTM 1 Memory Size/Attribute Register (PCIL0_PTM1MS) ...................................... 47621.6.2.14 PTM 1 Local Address Register (PCIL0_PTM1LA) .................................................... 47621.6.2.15 PTM 2 Memory Size/Attribute Register (PCIL0_PTM2MS) ...................................... 47721.6.2.16 PTM 2 Local Address Register (PCIL0_PTM2LA) .................................................... 477

21.6.3 PCI Configuration Registers ............................................................................................... 47721.6.3.1 PCI Configuration Address Register (PCIC0_CFGADDR) ......................................... 47821.6.3.2 PCI Configuration Data Register (PCIC0_CFGDATA) ............................................... 47821.6.3.3 PCI Vendor ID Register (PCIC0_VENDID) ................................................................. 47921.6.3.4 PCI Device ID Register (PCIC0_DEVID) .................................................................... 47921.6.3.5 PCI Command Register (PCIC0_CMD) ...................................................................... 47921.6.3.6 PCI Status Register (PCIC0_STATUS) ...................................................................... 48021.6.3.7 PCI Revision ID Register (PCIC0_REVID) ................................................................. 48121.6.3.8 PCI Class Register (PCIC0_CLS) .............................................................................. 48121.6.3.9 PCI Cache Line Size Register (PCIC0_CACHELS) ................................................... 48221.6.3.10 PCI Latency Timer Register (PCIC0_LATTIM) ......................................................... 48221.6.3.11 PCI Header Type Register (PCIC0_HDTYPE) ......................................................... 48221.6.3.12 PCI Built-In Self Test (BIST) Control Register (PCIC0_BIST) .................................. 48221.6.3.13 Unused PCI Base Address Register Space ............................................................. 48321.6.3.14 PCI PTM 1 BAR (PCIC0_PTM1BAR) ....................................................................... 48321.6.3.15 PCI PTM 2 BAR (PCIC0_PTM2BAR) ....................................................................... 48321.6.3.16 PCI Subsystem Vendor ID Register (PCIC0_SBSYSVID) ....................................... 48421.6.3.17 PCI Subsystem ID Register (PCIC0_SBSYSID) ...................................................... 48421.6.3.18 PCI Capabilities Pointer (PCIC0_CAP) .................................................................... 48421.6.3.19 PCI Interrupt Line Register (PCIC0_INTLN) ............................................................. 48421.6.3.20 PCI Interrupt Pin Register (PCIC0_INTPN) .............................................................. 48521.6.3.21 PCI Minimum Grant Register (PCIC0_MINGNT) ...................................................... 485

12 AMCC Proprietary



21.6.3.22 PCI Maximum Latency Register (PCIC0_MAXLTNCY) ............................................ 48521.6.3.23 PCI Interrupt Control/Status Register (PCIC0_ICS) ................................................. 48521.6.3.24 Error Enable Register (PCIC0_ERREN) ................................................................... 48521.6.3.25 Error Status Register (PCIC0_ERRSTS) .................................................................. 48621.6.3.26 Bridge Options 1 Register (PCIC0_BRDGOPT1) ..................................................... 48721.6.3.27 PLB Slave Error Syndrome Register 0 (PCIC0_PLBBESR0) ................................... 48721.6.3.28 PLB Slave Error Syndrome Register 1 (PCIC0_PLBBESR1) ................................... 48921.6.3.29 PLB Slave Error Address Register (PCIC0_PLBBEAR) ........................................... 49021.6.3.30 Capability Identifier (PCIC0_CAPID) ........................................................................ 49021.6.3.31 Next Item Pointer (PCIC0_NEXTIPTR) .................................................................... 49021.6.3.32 Power Management Capabilities (PCIC0_PMC) ...................................................... 49121.6.3.33 Power Management Control/Status Register (PCIC0_PMCSR) .............................. 49121.6.3.34 PMCSR PCI-to-PCI Bridge Support Extensions (PCIC0_PMCSRBSE) ................... 49221.6.3.35 PCI Data Register (PCIC0_DATA) ........................................................................... 49221.6.3.36 Bridge Options 2 Register (PCIC0_BRDGOPT2) ..................................................... 49221.6.3.37 Power Management State Change Request Register (PCIC0_PMSCRR) .............. 493

21.7 Error Handling ............................................................................................................................. 49321.7.1 PLB Unsupported Transfer Type ....................................................................................... 49421.7.2 PCI Master Abort ................................................................................................................ 49421.7.3 Bridge PCI Master Receives Target Abort While PCI Bus Master ..................................... 49521.7.4 PCI Target Data Bus Parity Error Detection ....................................................................... 49521.7.5 PCI Master Data Bus Parity Error Detection ...................................................................... 49621.7.6 PCI Address Bus Parity Error While PCI Target ................................................................ 49621.7.7 PLB Master Bus Error Detection ........................................................................................ 496

21.8 PCI Power Management Interface .............................................................................................. 49721.8.1 Capabilities and Power Management Status and Control Registers ................................. 49721.8.2 Power State Control ........................................................................................................... 49721.8.3 Changing Power States ..................................................................................................... 497

21.9 PCI Bridge Reset and Initialization .............................................................................................. 49821.9.1 Address Map Initialization .................................................................................................. 49821.9.2 Other Configuration Register Initialization .......................................................................... 50021.9.3 Target Bridge Initialization .................................................................................................. 50021.9.4 Local Processor Boot from PCI Memory ............................................................................ 50121.9.5 Type 0 Configuration Cycles for Other Devices ................................................................. 501

21.10 Timing Diagrams ....................................................................................................................... 50121.10.1 PCI Timing Diagram Descriptions .................................................................................... 502

21.10.1.1 PCI Master Burst Read From SDRAM ..................................................................... 50221.10.1.2 PCI Master Burst Write To SDRAM .......................................................................... 50221.10.1.3 CPU Read From PCI Memory Slave, Nonprefetching .............................................. 50221.10.1.4 CPU Read From PCI Memory Slave, Prefetching .................................................... 50221.10.1.5 CPU Write To PCI Memory Slave ............................................................................. 50221.10.1.6 PCI Memory To SDRAM DMA Transfer ................................................................... 50321.10.1.7 SDRAM To PCI Memory DMA Transfer ................................................................... 503

21.10.2 Asynchronous .................................................................................................................. 50321.10.3 Synchronous .................................................................................................................... 524

22. External Bus Controller ...................................................................................................... 55522.1 Interface Signals .......................................................................................................................... 555

22.1.1 Interfacing to Byte, Half-Word, and Word Devices ............................................................. 55622.1.2 Driver Enables .................................................................................................................... 557

22.2 Non-Burst Peripheral Bus Transactions ...................................................................................... 55822.2.1 Single Read Transfer ......................................................................................................... 55822.2.2 Single Write Transfer ......................................................................................................... 559

AMCC Proprietary 13



22.3 Burst Transactions ....................................................................................................................... 56022.3.1 Burst Read Transfer ........................................................................................................... 56122.3.2 Burst Write Transfer ........................................................................................................... 562

22.4 Device-Paced Transfers .............................................................................................................. 56322.4.1 Device-Paced Single Read Transfer .................................................................................. 56422.4.2 Device-Paced Single Write Transfer .................................................................................. 56522.4.3 Device-Paced Burst Read Transfer ................................................................................... 56622.4.4 Device-Paced Burst Write Transfer .................................................................................... 567

22.5 External Bus Master Interface ..................................................................................................... 56822.5.1 Arbitration ........................................................................................................................... 56922.5.2 Transaction Overview ........................................................................................................ 57022.5.3 Single Read and Single Write Transfers ............................................................................ 57122.5.4 Burst Read Transfer ........................................................................................................... 57222.5.5 Burst Write Transfer ........................................................................................................... 57322.5.6 External Master Error Interrupts ......................................................................................... 574

22.6 EBC Registers ............................................................................................................................ 57422.6.1 EBC Configuration Register (EBC0_CFG) ......................................................................... 57622.6.2 Peripheral Bank Configuration Registers (EBC0_B0CR:EBC0_B5CR) ............................. 57722.6.3 Peripheral Bank Access Parameters (EBC0_B0AP:B5AP) ............................................... 578

22.7 Error Reporting ............................................................................................................................ 58022.7.1 Peripheral Bus Error Address Register (EBC0_BEAR) ..................................................... 58022.7.2 Peripheral Bus Error Status Register 0 (EBC0_BESR0) ................................................... 580

23. NAND Flash Controller ....................................................................................................... 58323.1 Overview ...................................................................................................................................... 58423.2 NDFC Signal Multiplexing ............................................................................................................ 58523.3 NDFC Interface ............................................................................................................................ 58523.4 Resetting the Controller ............................................................................................................... 58523.5 Configuring EBC to Support the NAND Flash Controller ............................................................. 585

23.5.1 EBC0_BxAP ....................................................................................................................... 58623.5.2 EBC0_CFG ....................................................................................................................... 58623.5.3 EBC0_BxCR ..................................................................................................................... 58623.5.4 Summary of EBC and NDFC Interface Configurations ...................................................... 586

23.6 Booting from NDFC ..................................................................................................................... 58723.6.1 AutoRead Mode ................................................................................................................. 58923.6.2 Accessing NAND Flash ...................................................................................................... 591

23.6.2.1 Reading NAND Flash ................................................................................................. 59123.6.2.2 Writing NAND Flash .................................................................................................... 591

23.7.1 Column Parity ..................................................................................................................... 59423.7.2 Line/Row Parity .................................................................................................................. 59423.7.3 How to generate line parity (LP00-LP15) ........................................................................... 595

23.8 External Device Cycles ................................................................................................................ 59623.8.1 Command Cycle ................................................................................................................. 59723.8.2 Address Write Cycle ........................................................................................................... 59723.8.3 Basic Nand Flash Device Read Cycle ............................................................................... 59823.8.4 Basic Nand Flash Device Write Cycle ................................................................................ 59923.9.1 Memory Map ...................................................................................................................... 60023.9.2 NDFC Address Register (NDFC0_ADDR) ......................................................................... 60123.9.3 NDFC Command Register (NDFC0_CMD) ........................................................................ 60123.9.4 NDFC Data Register (NDFC0_DATA) ............................................................................... 60123.9.5 NAND Flash ECC Calculation Registers (NDFC0_ECC0:NDFC0_ECC7) ........................ 60323.9.6 NDFC Bank Configuration Registers (NDFC0_B0CR:NDFC0_B3CR) .............................. 603

14 AMCC Proprietary



23.9.7 NDFC Configuration Register (NDFC0_CR) ...................................................................... 60423.9.8 NDFC Status Register (NDFC0_SR) ................................................................................. 60623.9.9 NAND Flash Direct Hardware Control Register (NDFC0_HWCTL) ................................... 60723.9.10 NDFC Revision ID Register (NDFC0_REVID) ................................................................. 608

24. Direct Memory Access Controllers ................................................................................... 60924.1 DMA to PLB4 Controller (DMA2P40) .......................................................................................... 609

24.1.1 DMA Transfers ................................................................................................................... 60924.1.1.1 Memory-to-Memory Transfers .................................................................................... 61024.1.1.2 Scatter/Gather Transfers ............................................................................................ 611

24.1.2 Configuration and Status Registers ................................................................................... 61124.1.2.1 DMA to PLB 4 Channel Control Registers (DMA2P40_CR0-DMA2P40_CR3) .......... 61324.1.2.2 DMA to PLB 4 Count and Control Registers (DMA2P40_CT0-DMA2P40_CT3)) ...... 61424.1.2.3 DMA to PLB 4 Source Address Registers ................................................................. 61524.1.2.4 DMA to PLB 4 Destination Address Registers ............................................................ 61624.1.2.5 DMA to PLB 4 Scatter/Gather Descriptor Address Registers ................................ 61624.1.2.6 DMA to PLB 4 Status Register (DMA2P40_SR) ......................................................... 61724.1.2.7 DMA to PLB 4 Scatter/Gather Command Register (DMA2P40_SGC) ....................... 61824.1.2.8 DMA to PLB 4 Sleep Mode Register (DMA2P40_SLP) .............................................. 61824.1.2.9 DMA to PLB 4 Polarity Configuration Register (DMA2P40_POL) .............................. 619

24.1.3 Channel Priorities ............................................................................................................... 61924.1.4 Data Parity During DMA Peripheral Transfers ................................................................... 61924.1.5 Peripheral and Device-Paced Memory Bursts ................................................................... 61924.1.6 Errors ................................................................................................................................. 620

24.1.6.1 Address Alignment Error ............................................................................................. 62024.1.6.2 Burst Count Error ........................................................................................................ 62024.1.6.3 Burst Prefetch Error .................................................................................................... 62124.1.6.4 PLB or OPB Timeout .................................................................................................. 62124.1.6.5 Slave Transfer Errors .................................................................................................. 621

24.1.7 DMA to PLB4 Interrupts ..................................................................................................... 62124.1.8 Scatter/Gather Transfers .................................................................................................... 62224.1.9 Programming the DMA2P40 Controller .............................................................................. 623

24.1.9.1 Memory-to-Memory Transfers .................................................................................... 62324.2 DMA to PLB3 Controller (DMA2P30) .......................................................................................... 625

24.2.1 External Interface Signals .................................................................................................. 62624.2.2 Functional Overview ........................................................................................................... 62724.2.3 Peripheral Mode Transfers ................................................................................................. 62724.2.4 Memory-to-Memory Transfers ............................................................................................ 62824.2.5 Scatter/Gather Transfers .................................................................................................... 62824.2.6 Configuration and Status Registers ................................................................................... 629

24.2.6.1 DMA to PLB 3 Polarity Configuration Register (DMA2P30_POL) .............................. 63024.2.6.2 DMA to PLB 3 Sleep Mode Register (DMA2P30_SLP) ............................................. 63124.2.6.3 DMA to PLB 3 Status Register (DMA2P30_SR) ......................................................... 63124.2.6.4 DMA to PLB 3 Channel Control Registers (DMA2P30_CR0DMA2P30_CR3) ......... 63224.2.6.5 DMA to PLB 3 Source Address Registers (DMA2P30_SA0DMA2P30_SA3) .......... 63424.2.6.6 DMA to PLB 3 Destination Address Registers (DMA2P30_DA0DMA2P30_DA3) ... 63424.2.6.7 DMA to PLB 3 Count Registers (DMA2P30_CT0DMA2P30_CT3) .......................... 63424.2.6.8 DMA to PLB 3 Scatter/Gather Descriptor Address Registers (DMA2P30_SG0DMA2P30_SG3) ....................................................................................................................... 63524.2.6.9 DMA to PLB 3 Scatter/Gather Command Register (DMA2P30_SGC) ....................... 63524.2.6.10 DMA to PLB 3 Subchannel ID Registers (DMA2P30_SC0DMA2P30_SC3) .......... 63624.2.6.11 DMA to PLB 3 Address Decode Register (DMA2P30_ADR) .................................... 636

24.2.7 Channel Priorities ............................................................................................................... 636

AMCC Proprietary 15



24.2.8 Data Parity During DMA Peripheral Transfers ................................................................... 63724.2.9 Errors ................................................................................................................................. 63724.2.10 Address Alignment Error .................................................................................................. 63724.2.11 PLB Timeout .................................................................................................................... 63824.2.12 Slave Errors ..................................................................................................................... 63824.2.13 DMA Interrupts ................................................................................................................. 63824.2.14 Scatter/Gather Transfers .................................................................................................. 63824.2.15 Programming the DMA to PLB3 Controller ...................................................................... 64024.2.16 Peripheral Mode Transfers ............................................................................................... 640

24.2.16.1 Peripheral-to-Memory Transfer ................................................................................. 64224.2.16.2 Memory-to-Peripheral Transfer ................................................................................. 643

24.2.17 Memory-to-Memory Transfers .......................................................................................... 64324.2.17.1 Hardware-Initiated (Device-Paced) Memory-to-Memory Transfers .......................... 64324.2.17.2 Software-Initiated Memory-to-Memory Transfers (Non-Device Paced) .................... 644

25. Memory Access Layer ........................................................................................................ 64525.1 MAL Features .............................................................................................................................. 645

25.1.1 MAL Internal Structure ....................................................................................................... 64725.1.1.1 PLB Master ................................................................................................................. 64725.1.1.2 EOPB Master .............................................................................................................. 64725.1.1.3 TX Channel Handler ................................................................................................... 64725.1.1.4 RX Channel Handler ................................................................................................... 64725.1.1.5 TX Channel Arbiter ..................................................................................................... 64825.1.1.6 RX Channel Arbiter ..................................................................................................... 64825.1.1.7 TX Common Channel Logic ........................................................................................ 64825.1.1.8 RX Common Channel Logic ....................................................................................... 64825.1.1.9

Date post:	26-Mar-2018
Category:	Documents
Upload:	lemien
View:	229 times
Download:	7 times

PPC440EPx/GRx Embedded Processor User’s...

Documents