PowerPoint Presentation

DEVELOPMENT OF SIMPLE/SUPERSCALAR PROCESSOR WITH BLUESPEC SYSTEM VERILOG (BSV) AND VERIFICATION OF THE SAME WITH SoC FRAMEWORK Presented By N. Siva Kumar 115040011 Guided ByDr. Jayanta Biswas Whats the need for designing a Synthesizable processor?

Application specific cores for system-on-chip applications An ASIP is an hardware architectural concept meant to fill the gap between ASICs (Application Specific Integrated Circuits) and DSPs (Digital Signal Processors)Flexibility: designed to support at least minor variations of the implemented algorithmSystem efficiency: it implies computational power, area and costMulticore emulation for architectural design space explorationAbstract

This project implements a pipeline processor with Bluespec System Verilog (BSV) using the concepts of concurrency, scheduling, parallelism and pipeline hazards optimization. The pipeline processor performance is compared with a sequential processor in terms of cycles per instruction (CPI) and average execution time for a single instruction. The functionality of the designed processors is verified with GTK cycle accurate simulator. Altera design flow is adopted to verify the static timing analysis and to exploit multi-corner timing issues.Bluespec System VerilogSequential ProcessorPipeline ProcessorAltera Timing AnalysisProject LayoutProblem Definition

The major problem of executing multiple instructions in a scalar program is the handling of data dependencies. If data dependencies are not effectively handled, it is difficult to achieve an execution rate of more than one instruction per clock cycle.4

Pipeline Architecture5

Opcode5-bit32 inssDestination RegisterOrWrite Register6-bit32 regsSource1 RegisterOrRead1 Register6-bit32 regsSource2 RegisterOrRead2 Register6-bit32 regsMB Ack.Instruction Format Address Fields6

Mnemonics & Opcodes Include arithmetic, logical, load-store, branching and machine control instructionsCommonly utilized instructions in a RISC processor architectureData Forwarding - analysis of dependent instructions Dependent instructions consumes more processing cycles till the availability of data in the destination address of previous instructionThis degrades the performance of the processor and increases the timing constraints

The saving of ALU result prior to write-back stage helps in forwarding data to the successive dependent instruction.

TIMING ANALYSISCompiled in Altera Quartus II version 9.1 web edition for Stratix-III platformFmax for the sequential processor is obtained at 18 MHzFor pipeline processor the value of Fmax is 168 MHzThis variation is due to resources overlapping in the sequential design along with data hurdles and timing synchronization issues4187 LUTs are utilized by the pipeline designFUTURE SCOPE : SUPERSCALAR PROCESSOR DESIGN The design is extended to execute multiple instructions in a single cycle using Bluespec System VerilogPipeline also allows several instructions executing in the same cycle, but in different stagesThe designed pipeline processor is reused as a base design for implementing superscalar architecture and carrying out performance evaluation for superscalar architecture

CONCLUSION

A Sequential processor is designed without pipeline register implementation. The design is analysed to gain the insight for hurdles and timing issues. The verilog version of the design program is obtained from Bluespec and static timing analysis is performed using Altera Quartus II tool. A Pipeline processor is designed using pipeline registers and analyzed in terms of concurrency, cycles per instruction and hazards optimization. Detailed analysis is performed with optimization protocols for maximum throughput. Scheduling analysis is throughly worked out for timing synchronization between the pipeline stages. Timing analysis is performed using the same Altera tool and is determained to work at 168 MHz for Stratix-III platform. PUBLICATION

Hazards Analysis In A Processor Using Bluespec System VerilogSiva Kumar Nagulapati, Dr. Jayanta Biswas INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH (IJAER)SCOPUS INDEXED JOURNALAccepted

References

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