Proposal For Infrastructure To Become Recipient Remote Centre of IIT Bombay’s (CDEEP) Centre For Distance Engineering Education Program on

Virtual Laboratories For VLSI & Embedded

Systems

Presented byBibhudendra Acharya

Department of Electronics and Communication EngineeringNational Institute of Technology, Raipur.

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Presentation outline

• About Virtual Laboratories For VLSI & Embedded Systems

• Basic Infrastructure Requirement

• Content Delivery For Teacher Training

• Content Delivery For Students

• Suggested Courses For Teacher Training

• About the State Chhattisgarh

• About NIT Raipur

• Financial Requirement

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About Virtual Laboratories For VLSI & Embedded Systems

• India currently only constitute about 0.5% of the electronics design business.

• The fields of VLSI design and embedded systems are converging into a common platform: the system on chip.

• Thus, an exposure to this field is critical in manpower training both at the degree and the diploma level.

• Training in these fields is incomplete without a solid practical orientation in which concepts can be applied to nontrivial case studies.

• In order to provide laboratory infrastructure for such training programmes, a virtual laboratory framework offers a cost effective solution.

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Cont..

• In this proposal, we outline the deployment of a virtual “IMAGE VLSI and Embedded Systems Laboratory” infrastructure in our institute, and the delivery of educational content through this infrastructure using distance learning facilities provided by the Centre for Distance Engineering Education Program (CDEEP), IIT Bombay.

• IIT Bombay is also using IMAGE VLSI & Embedded Lab to deliver education, both inside as well as at distant locations through Centre for Distance Engineering Education Program (CDEEP).

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Cont..

• CDEEP has been established to make IIT's courses available to the student and faculty community at large. IIT Bombay is determined to reach out to Technology and Engineering institutions in India and abroad; and disseminate the knowledge which it has in various fields of engineering and science using modern e-learning tools.

• The virtual laboratory would consist of three components:1. Basic infrastructure at each remote centre.2. Content delivery for teacher training at each remote centre (through the CDEEP facility at IIT Bombay).3. Content delivery for student training at each remote centre.

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Basic Infrastructure Requirement

BASIC INFRASTRUCTURE called “IMAGE VLSI & Embedded Lab 50” to be established & the basic infrastructure would consist of

(a) NGSPICE, NGNUTMEG (circuit simulator and result viewer).(b) GHDL (VHDL simulator).(c) Xilinx ISE (9.1 or higher) (FPGA synthesis tool set).(d) IMAGE simulation accelerator (FPGA based co simulation

environment).(e) Computing infrastructure: Thirty node IMAGE VLSI and Embedded

Systems Laboratory (five servers and forty-five high-end PC’s with all tools installed and configured).

(f) HookIN; signal visibility tool: Random internal signal visibility tool, which enables to monitor any signal or port, implements VHDL-in-VHDL-out; observing ports or signals of any level in the design hierarchy.

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Cont..

(g) IMAGE ForceIT; controllability tool: Forces any signal to any desired value i.e. stuck at “0” or stuck at “1”.Deliberately inducing a glitch by forcing a signal. It should provide a procedure by which the user can freeze a signal value, force it to some logic level and observe the changes and then release it, and retain the previous values.

(h) MiRAGE; Memory Extraction tool: The memory mapping tool for better FPGA utilization. The memory controller logic automatically maps embedded design memory into external memory bank of 24 MB on the board. There should be no design change involved.

(i) IMAGE API: Application Program Interface (API) to interface the host customized machine with the Board: for Embedded System and prototyping.

(j) IMAGE TDM: Automatic Time Division Multiplexing (TDM) for data exchange between the four FPGAs. There is a limited number of i/o for each FPGA, the signals at any, which need to be passed from one FPGA to another might be more than available, for this it should apply TDM logic.

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Cont..

(k) IMAGE ScaleUP: Software and hardware for adding more four FPGA PCB Card on the machine, to scale-up the Capacity.

(l) IMAGE FPGA Board: FPGA Board having Four FPGAs on a single PCB Board with a total capacity of 100 Million FPGA gates. Board Memory: 120 MB SRAM on Board.

(j) The board will have the interface with the host on a 32-bit, 33 MHz PCI bus, talk to it through PLX chip, PCI-9054. An API is attached to the board, which helps standard simulator as the user interface using FLI/FMI of the respective simulators.

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Cont..

(k) For Synthesis *Bottom-up software to reduce the synthesis time.*The software should have the ability to use other IMAGE nodes for Parallelizing; the IMAGE nodes in a star topology with the main IMAGE server will be provided along with the product.

(l) Software that make the FPGA Board compatible with standard simulation software. Software that make the FPGA Board compatible with Standard synthesis tool.

(j) PartIT; Design Partition tool: Automatic partition of design at RTL level; which respects the design hierarchy. Design fits into multiple smaller capacity FPGAs. Intelligent partitioner : less inter-FPGA communication between the partitions. The basic functionality remains unchanged. Each partition has approximate equal gate count.

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Cont..

(k) All Software tools will have a perpetual license.(l) Onsite support for the above tools for a period of one year.(m) For a period of one year, all new versions and upgrades of the

software will be provided free.(n) IMAGE Learning Resource (ILR)

+ IMAGE Learning Resource (ILR-Video): A set of CDs; Lab teaching and VLSI learning from eminent IIT professors via CD.+ IMAGE Learning Resource (ILR-Books): Lab Exercise Books for students so as to make best use of the laboratory. This should cover examples on simple chip design to graduating the student to making a complex chip. This is to make learning easy.

(o) Detailed training program to be conducted for the onsite faculty members after the installation.

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Cont..

(i) IMAGE ScaleUP: Software and hardware for adding more four FPGA PCB Card on the machine, to scale-up the Capacity .

(j) Black-boxes, Unsynthesizable Entities: A black-box in the system is piece of already synthesized RTL which needs to be “dropped-in” to the hardware. An unsynthesizable entity/module is a design unit which the user marks as unsynthesizable; The Software should pull this unit out of the hardware and place it on the host-side for the co-simulation process.

(k) IMAGE Signal Coding: It should use bits to encode complex user-defined types. In particular the VHDL std logic type and the Verilog wire types can be coded as multi-valued types as well as two-valued types.

(l) Mixed HDL support i.e. VHDL as well as Verilog.(m) Clocks and Timing: It should allows the source RTL to have an

arbitrary number of clocks. Clock-gating logic should also be permitted and so are asynchronous descriptions.

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Cont..

(n) Design Re-use: A design unit that is already mapped to IMAGE hard-ware may be re-used in another simulation without having to repeat the mapping process.

(o) For embedded software development: the system for which embedded software is to be developed should be mapped to hardware by the Software. The Software provides mechanisms for loading code onto the hardware mapped design together with examination/deposit debug features.

(p) IMAGE Flow Debugging: in order to track down the source of a possible mismatch between your software simulation and IMAGE accelerated simulation, the IMAGE installation includes a set of utilities which can allow you to break the IMAGE mapping flow at different points and to simulate the transformed RTL.

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Cont..

(q) Based on the IIT Bombay Professor conducting the course, at least one visit per two weeks will be conducted during the tenure of the course.

(r) One year warranty• A streaming video interface to the internet (for delivery of CDEEP

courses) or an EDUSAT terminal.• A web interface to the software tools, with adequate network

connectivity.• A series of online tutorials describing the use of the CAD tools.

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Content Delivery For Teacher Training

• To train the teachers at the remote centers, CDEEP will deliver course content in the area of VLSI design and Embedded Systems to the remote centers by means of regular onsite visits by certified personnel who will be responsible for maintaining the quality of content delivery.

• This will include the provision of training on CAD tools, assistance in course homework and assignments, and coordination between the remote centre and course instructors at IIT Bombay.

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Content Delivery For Students

• This content will consist of two parts: a series of online laboratory courses in Hardware description languages, Simulation and Synthesis, and the use of FPGAs will be provided. To support these online courses, regular onsite visits (coincident with the visits for supporting the CDEEP teacher training courses) will be conducted.

• The students who are working through the online web courses will be guided and mentored during these regular onsite visits.

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Suggested Courses For Teacher Training

The following courses which are being run at IIT Bombay will be supportedusing the virtual laboratory.

1. VLSI System Design 2. VLSI Circuit Design.3. Hardware Description Languages.4. Embedded Systems.5. Computer Systems6. VLSI Design Lab7. Modern Electronics Design Techniques8. Digital Circuit Lab9. Foundation of VLSI10. Hardware Description Language 11.Basic Electronics

More meaningful & much needed courses are being added to this list

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The State Chhattisgarh

• Chhattisgarh, a 21st century State, came into being on November 1, 2000. Larger than Tamil Nadu, it is just the right size

• Chhattisgarh is truly a land of opportunities. With all major minerals including diamonds in abundance, it is the richest State in mineral resources.

• Several hundred students from the State qualify for admissions in prestigious academic institutions every year.

• Bhilai, the knowledge capital of the State, alone sends over 50 students to the elite Indian Institutes of Technology every year.

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The State Chhattisgarh(cont..)

• Its large power surplus is attracting power-intensive industries, and the State is poised to become the power-hub of the nation.

• Its central location helps easy power transmission to any part of the country.

• The State is supplying power to Delhi ,Gujarat and Karnataka, among others.

• Chhattisgarh ranks high in terms of good industrial relations and labour productivity

• The Chhattisgarh is a new state in India and technical education facilities are not adequate.

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The State Chhattisgarh(cont..)

• The State has 49 Engineering colleges and most of them are new.

• Approximately a total of 10290 students enrolled per year in Computer, IT, Electrical &Electronics and related branches.

• The state has immense potential to graduate into the league of advanced states provided that it gets adequate planning specially

in the area of higher studies as well as technical education.

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NIT Raipur

• National Institute of Technology Raipur (Formerly Government Engineering College Raipur), situated in the capital of a newly incepted state of Chhattisgarh,

• NIT Raipur has proven to be "advent-grade' in the field of science and technology over past few decades in this region.

• With sweet memory of foundation ceremony by our president Hon'ble Dr. Rajendra Prasad on 14th September 1956.

• Later the inauguration of the Institute building was done by our Prime Minister Hon'ble Pt. Jawahar Lal Nehru on 14th March 1963.

• From 1st December 2005, the Institute has become the National Institute of Technology from Government Engineering College Raipur.

• The Institute has no VLSI & Embedded Systems Lab and as well as no skilled faculties in this area.

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Financial Requirement

• Total amount required:

Rupee Three Crore Eighty five lacs only.

• Details of funds requested for 5 years along with phasing for each year:Cost in Lacs

Rs. (1 Lac= 100,000)

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Thank You