Reduction of State and Flow Tables

8/9/2019 Reduction of State and Flow Tables

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Reduction of States and Flow Tables

• How to reduce the number of internal states in an asynchronous

sequential circuit ????

•

The algorithm, that was used in chapter 5 for state reduction of acomplete state table in synchronous sequential circuits, will be modified

to cover the state reduction of asynchronous sequential circuits.

mp ca o n a e

Merging of the Flow Table

Maximal Compatibles

40© 2010 Dr. Ashraf Armoush , An‐Najah National University

Implication Table

• Two states in a state table can be combined into one, as long as

they can be shown to be equivalent

• E uivalent States: Two states are e uivalent if for each ossible

input, they give exactly the same output and go to the same next

states or to equivalent next states.

– a and b have the same output for the same input, their next states are

c and d for x=0 and b and a for x = 1

– If we can show that (c and d) are equivalent, then (a and b) are

equivalent. [(a,b) imply (c,d)]



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Implication Table (cont.)

• The checking of each pair of states for possible equivalence in a

table with a large number of states can be done systematically by

means of an im lication table.

• It is a chart that consists of squares, one for every possible pair of

states.

– On the left side along the vertical are listed all the states defined in the

state table except the last.

– Across the bottom horizontally are listed all the states except the last.

– The states that are not equivalent are marked with (X) in the

corresponding squares.

– The states that are equivalent are marked with ( ) in the

corresponding squares.

– Some of the s uares have entries o im lied states that must be

further investigated to determine whether they are equivalent or not.



1. Place a cross in any square corresponding to a pair whose outputs are not equal2. Enter in the remaining squares the pairs of states that are implied by the pair of

states representing the squares. (Start form the top square in the left columnand going down and then proceeding with the next column to the right ).

3. Make successive passes through the table to determine whether any additional‘ ’


.4. Finally, all the squares that have no crosses are recorded with check marks.


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The equivalent states are:

(a, b), (d, e), (d, g), (e, g).

Combine airs of states into lar er rou s of

equivalent states.

(a, b), (d, e, g) The final partition consists of:

The equivalent states found from the

implication table [(a, b) (d, e, g)]

All the remaining states in the state table

that are not equivalent to any other state.

[(c) , (f)]Present

State

Next State Output

, , ,

The original flow table can be reduced from

x= x = x= x=

a d a 0 0

c d f 0 1

44© 2010 Dr. Ashraf Armoush , An‐NajahNational University

d a d 1 0

f c a 0 0

Merging of the Flow Table

• When certain combinations of inputs or input sequences may neveroccur because of external and internal constrains The state tableis incom letel s ecified.

• Incompletely specified states can be combined to reduce thenumber of states in the flow table.

• Such states cannot be called equivalent, but, instead they are saidto be compatible.

• In order to find a suitable group of compatibles for the purpose of merging a flow table, the following steps must be applied:

1. Determine all compatible pairs by using the implication table.

2. Find the maximal compatibles using a merger diagram.

3. Find a minimal collection of compatibles that covers all the statesand is closed.



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Compatible Pairs

• Compatible States: Two states are compatible if in every column of

the corresponding rows in the flow table, they are identical or

.

The compatible

pa rs are :

(a , b)

(a , c)

a ,

(b , e)

(b , f)

(c ,d)

(e , f)


Maximal Compatibles

• Maximal compatible: is a group of compatibles that contains all

the possible combinations of compatible states.

.


patterns in which states are connected to each other.


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Closed Covering Condition

• The condition that must be satisfied for row merging is that the set

of chosen compatibles must:

. .

2. Be closed: ( the closure condition is satisfied if there are no implied states or

if the

implied

states

are

included

within

the

set)

In the last example, the maximal compatibles are (a , b) (a , c , d) (b , e , f)

• if we remove (a , b), we get a set of two compatibles: (a , c , d) (b , e , f)

All the six states are included in this set.

There are no impiled states for (a,c); (a,d);(c,d);(b,e);(b,f) and (e,f) [you

can check the implication table] . the closer condition is satisfied

The original primitive flow table can be merged into two rows, one for

each of the compatibles.


Ex: (Closed Covering Condition)

• From the given implication table, we have the followingcompatible pairs:

( a , b ) ( a , d ) ( b , c ) ( c , d ) ( c , e ) ( d , e )

,compatibles:

( a , b ) ( a , d ) ( b , c ) ( c , d , e )

• I we choose the two com atibles

( a , b ) ( c , d , e )

All the 5 states are included in this set. (

)

The implied states for (a,b) are (b,c). But (b,c) are notinclude in the chosen set This set is not closed. (X)

A set of compatibles that will satisfy the closedcovering condition is ( a , d ) ( b , c ) ( c , d , e )



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3‐Row Flow ‐Table Example

• A flow table with 3 states requires an assignment of 2

variables.

•

a b , a c , b a , b c & c a

(see the transition diagram)

• If we take the following assignment:

State Value

a

b 01

c 11

• This assignment will cause a critical race during the

transition from a to c (2 changes in the binary state ),


3‐Row Flow ‐Table Example (cont.)

• A race‐free assignment can be obtained by adding an extra row to the original

flow table :

e use o an extra row w not ncrease

the number of binary state variables (2

variables), but it allows the formation of

cycles between two stable states.

The added row (d) is assigned the binary

value (10), which is adjacent to both a & c.

The transition from a to c must go

through d, thus avoiding a critical race.

The two squares with dashes in row d

represent unspecified states (don’t care).

These squares must not be assigned to 01


state being established in the 4th row.


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• The new flow table is converted to a transition table to complete the design

process.


4‐Row Flow ‐Table Example

• A flow table with 4 states requires an assignment

of two state variables.

• If there were no transitions in the diagonal

direction (from a to c or from b to d), it would be

remaining 4 transitions.

• n or er o sa s y e a acency requ remen ,

at least 3 binary variables are needed .



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• The following state assignment map is suitable for any 4‐row flow table.

– a, b, c, and d are the original states.

– , , .

– States placed in adjacent squares in the map will have adjacent assignments



• To produce cycles:

– The transition from a to d must be directed through the extra state e

– The transition from c to a must be directed through the extra state g

– The transition from d to c must be directed through the extra state f

table has 7 rows,

there are only 4

stable states.



10/19

Multiple Row Method for race‐ free assignment

• It is less efficient than the previous method (shared row method).

• Each state in the original flow table is replaced by two or more

combinations of state variables.e.g.:

a is replaced with a1 and a2 , where a1 is the logical complement of a2

• Eac sta e state as two inary assignments wit exact y t e

same output

e.g.:

The output values must be the same in a1 and a2

• t any g ven t me, on y one o t e ass gnments s n use.


Multiple Row Method (cont.)

• e.g. a1 is adjacent to b1, c2, and d1 where a2 is adjacent to c1, b2, d1

• When choosing the next state for a given present state, a state that isadjacent to the present state is selected from the map.



11/19

Hazards

• In order to ensure the proper operation in asynchronous circuits , the

circuits must be:

. .

2. Free of critical races.

3. Checked for hazards .

• Hazards are unwanted switching transients that may appear at the

output of a circuit because different paths exhibit different

propagation delay.

•

– In combination circuits, they may cause a temporarily false output value.

–

In asynchronous circuits, they may result in a transition to a wrong stable state.


Hazards in Combinational Circuits

x1 x2 x3 AND 1 AND 2 Y

1 1 1 1 0 1

•

1 0 1 0 1 1

before the output of gate 2 changes to 1.

• In that case, the output goes to 0 for short interval of time.

sums)of (product products)of (sum

))('(or' 32213221 x x x xY x x x xY ++=+=

• The first implementation may cause the output to go to 0 when it should ‐ ,

the output to go to 1 when it should remain at 0 (Static 0‐hazard) .



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Hazards in Combinational Circuits (cont.)

• The dynamic hazard causes the output to change three or four

.

• The occurrence of the hazard can be detected by inspecting themap of a particular circuit.


Hazard Free Circuit

• The change in x2 from 1 to 0 moves the circuit

from minterm 111 to minterm 101.

• The hazard exists because the change of input

results in a different product term covering the

.

• Whenever the circuit must move from one

product term to another, there is a possibility

of a momentary interval when neither term is

equal to 1, giving rise to undesirable 0 output.

• The solution is to enclose the minterms with

groupings.



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Hazard Free Circuit (cont.)

The removal of hazards requires the addition of

redundant gates to the circuit.


Hazards in Sequential Circuits

• Momentary erroneous signals are not generally troublesome in normal

combinational‐circuits associated with synchronous sequential circuit. Thus,

hazard are not of concern in these circuits.

• Conversely, if a momentary incorrect signal is fed back in an asynchronous

sequential circuit, it may cause the circuit to go to a wrong stable state.

o If the circuit is in total state yx 1 x 2 = 111 and input x 2 changes from 1 to 0 , the

next total state should be 110. However, because o the hazard, output Y

may go 0 momentarily.

o If this false signal feeds back into gate 2, the output of gate 2 will remain at

0 and the circuit will switch to the incorrect total state 010.

This problem can be eliminated by adding an extra gate.



14/19

Hazards in Sequential Circuits

‐ Implementation with SR Latches

• Another way to avoid static hazards in asynchronous sequential circuits is

to implement the circuit with SR latches.

• A momentary 0 signal applied to the S or R inputs of a NOR latch will have no

effect on the state o the latch.

• Similarly, a momentary 1 signal applied to the S or R inputs of a NAND latch

will also have no effect on the state of the latch.

Ex:

• s mp emen a on may ave a s a c ‐ azar o npu s o ga e go

to 1, changing the output from 1 to 0 momentarily.

• But if gate 3 is part of a NAND‐latch, the momentarily 1 signal will have no

e ect ecause anot er nput w come rom t at w e equa to an

thus maintain the output at 1


Ex:

• Consider a NAND SR‐latch with the following Boolean functions for S and R

S = AB + CD

=

• Since this is a NAND latch we must use the complement value for S and R

S = (AB + CD)’ =(AB)’(CD)’

R = (A’C)’



15/19

Ex (cont.):

• The Boolean function for output is

Q = (Q’S)’ = [Q’ (AB)’(CD)’]’

• The output is generated with two levels of NAND gates:

• If output Q is equal to 1, then Q′ is equal to 0. If two of the three inputs

go momentarily to 1, the NAND gate associated with output Q will remain at 1 because Q′ is maintained at 0.


Essential Hazards

• An Essential Hazard: is caused by unequal delays along two or

more paths that originate from the same input.

• Essential hazards cannot be corrected by adding redundant

.

• The

roblem can

be

corrected

b

ad ustin

the

amount

of

delay in the affected paths.



16/19

DESIGN EXAMPLE

The recommended procedural steps for the design of a completeasynchronous sequential circuit are:

. .

2. Derive a Primitive Flow Table.

3. Reduce the Flow Table by merging rows.

4. Ma e a race‐ ree inary state assignment.

5. Obtain the transition table and output map.

6. Obtain the logic diagram using SR latches.

1) Design Specification:

‐ ‐ ‐ .circuit has two inputs T (toggle) and C (clock) and one output Q.

The output state is complemented if T=1 and the clock changesfrom 1 to 0 ne ative‐ed e‐tri erin . Otherwise under all in utcondition, the output remains unchanged.


Design example (cont)

2) Primitive flow table.

Inputs Output

State T C Q Comments

a n a ou pu s

b 1 0 1 After state a

c 1 1 1 Initial output is 1

d 1 0 0 After state c

e 0 0 0 After state d or f

f 0 1 0 After state e or a

g 0 0 1 After state b or h

h 0 1 1 After State g or c



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3) Merging of the Flow Table

e max ma compat es pa rs are:

(a , f) (b , g , h) (c , h) (d , e , f)



In this particular example, the minimal collection of compatibles

is also the maximal compatibles set:

a , , g , c , , e ,



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4) State Assignment and Transition Table

From the transition diagram, it is clear that there are no diagonal lines.

Therefore, it is possible to find a suitable adjacent assignment without

the need of extra states.



5) Logic Diagram

There are two state variables Y1 and Y2, and one output Q. The

revious out ut ma shows that is e ual to 2.



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Reduction of State and Flow Tables

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