Reticle Floorplanning With Guaranteed Yield for Multi-Project Wafers

Andrew B. Kahng

ECE and CSE Dept.University of California

San Diego

Sherief Reda

CSE Dept.University of California

San Diego

Outline

Introduction to Multi-Project Wafers

Design Flow

Side-to-Side Dicing Problem

Proposed Methodology: Floorplanning with Guaranteed Yield

Experimental Results

Mask and Wafer Cost

Mask cost: $1M for 90 nm technology

Wafer cost: $4K per wafer

Introduction to Multi-Project Wafer

Share rising costs of mask tooling among multiple prototype and low production volume designs → Multi-Project Wafer

Image courtesy of CMP and EuroPractice

History of Multi-Project Wafer

Introduced in late 1970s and early 1980s

Companies: MOSIS, CMP, TSMC

Several academic approaches proposed:

1. Chen et al. give bottom-left fill algorithm, SPIE 2003

2. Xu, Tian, Wong and Reich, SPIE 2003

3. Anderson et al. propose a grid packing algorithm, WADS 2003

4. Kahng et al. propose dicing plans for generic floorplans, ISPD 2004

Commercial Tools: MaskCompose, GTMuch

Outline

Introduction to Multi-Project Wafers

Design Flow

Side-to-Side Dicing Problem

Proposed Methodology: Floorplanning with Guaranteed Yield

Experimental Results

Design Flow

Unique designs

Design Flow

Custom designs Partition between reticles

Design Flow

Custom designs Partition between shuttles Reticle placement

Design Flow

Custom designs Partition between shuttles Reticle placement Stepper shot-map

print

shot-map

Design Flow

Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design

Design Flow

Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design

Design Flow

Custom designs Partition between shuttles Reticle placement Stepper shot-map Dicing plan design Extract die

Outline

Introduction to Multi-Project Wafers

Design Flow

Side-to-Side Dicing Problem

Proposed Methodology: Floorplanning with Guaranteed Yield

Experimental Results

Why is Dicing a Problem?

Sliced out

A die is sliced out if and only if:

1. Four edges are on the cut lines

2. No cut lines pass through the die

Dicing is easy for standard wafers.

All dice will be sliced out.

Dicing is complex for MPW.Most dice will be destroyed if placement is not well aligned.

Side-to-side dicing is the prevalent wafer dicing technology

Die Conflict

Two dies are in conflict if they can not be simultaneously sliced out horizontally.

Die 1 is in conflict with entire row of Die 2.

1 2

43

12

43

12

43

12

43

Dicing Plan

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

1 1 23 4

6 66 6 5

23 4

dicing die 2

dicing die 2

dicing die 1

dicing die 1

waferreticle

die

A die copy is successfully extracted if it is successfully extracted in both horizontal and vertical dicing

MPW Floorplanning Objectives

Produce the required volumes of all dies using the minimum amount of wafers → maximize the minimium amount of die copies extracted from a wafer over all dies (Yield)

Objective:

Given:A number of die designs, each with a production volume requirement

Example: If die 1 has a 40 copies requirement, and the dicing plan yields 5 valid copies per wafer → 8 wafers are needed

Methods:1. Floorplanning the dies within the reticle2. Efficient dicing plan

Outline

Introduction to Multi-Project Wafers

Design Flow

Side-to-Side Dicing Problem and Motivation

Proposed Methodology: Floorplanning with Guaranteed Yield

Experimental Results

Motivation

Previous approaches (Kahng et al.) use regular area floorplanning and devise efficient dicing plans

Regular area floorplanners are yield oblivious

There is an inherent conflict between area minimization and yield

Observation:

1 1 2

3 46 66 6

5

2

3 4

Proposed Approach

Construct floorplans that consider specified yield bounds as constraints and minimize the area

1. Limit floorplans to grids

2. Calculate constructive lower bounds on the yield

3. Specify simple rules to characterize the yield of a given floorplan

4. Minimize the area using a branch and bround procedure taking the yield as a constraint

Main Idea:

Method:

1. Grid Floorplans

1 1 2

3 4

6 6

6 65

2

3 4

1 1 2

3 4

6 6

6 65

2

3 4

General floorplan Grid floorplan

2. Constructive Yield Lower Bounds

reticle row

reticle column

1 1 2

3 4

6 6

6 6 5

2

3 4

grid row

grid column

Given m reticle rows and n reticle columns

Let γi be the number of different height die copies residing in a grid row, e.g.,

γ1=2, γ1=1

Let μj be the number of different width die copies residing in a grid column, e.g., μ1=1, μ2=2

Lemma 1: A constructive lower bound on number of copies that can be extracted of a die residing in row i and column j is m / γ i n / μj

n

m

3. Rules for Yield Specification

reticle row

reticle column

1 1 23 4

6 6

6 6 5

23 4

grid row

grid column

Limiting the values of μj and γi guarantees a lower limit on yield

γi : number of different height die copies residing in a grid row.

μj : be the number of different width die copies residing in a grid column

μj γi γiμ

j

Yield

1 1 1 100

1 2 2 50

2 1 2 50

3 1 3 30

2 2 4 25

Example

Theorem 1: A lower bound on the yield is m2-m(γiμj)/γiμj for a wafer with m rows and m columns

4. Branch and Bound Area Packer

Why is branch and bound feasible?

1. There are typically few dies per reticle

2. Yield constraints prune large portions of the search space

branch_bound(k, yield, grid[1..w][1..h])• if all dies are placed then

• evaluate the floorplan area and if area < best area then area = best area• return

• expand the grid by an additional column and row: grid[1..w+1][1..h+1]• for each empty slot (i, j) in the grid:

• if placing die dk in slot (i, j) does not violate yield constraints:• Place dk and evaluate partial area• if partial area < best area then branch_bound(k+1, yield, grid[1..w+1]

[1..h+1])• undo placement of dk in (i, j)

Outline

Introduction to Multi-Project Wafers

Design Flow

Side-to-Side Dicing Problem and Motivation

Proposed Methodology: Floorplanning with Guaranteed Yield

Experimental Results

Experimental Results: Yield/Area results

Test Case

# Die

Die area

Yield

100 50 30 25 20

1 10 231 494 312 288 270 264

2 18 226 396 286 275 260 275

3 11 252 456 312 300 290 288

4 9 203 500 300 264 252 256

5 10 226 560 336 285 260 280

6 15 227 494 306 275 276 275

7 15 234 416 297 280 270 280

8 14 232 416 297 280 270 273

9 10 231 494 312 288 270 264

10 20 215 360 270 240 270 240

Total 2277 4586 3028 2775 2688 2443 Our method allows an area/yield trade off

Experimental Results: Comparison against Previous Work

Test Case

# Die

Die area

GTMuch Previous App. (kahng et al.)

Our Approach

Yield Area Yield Area CPU Yield Area CPU

1 10 231 18 255 28 288 80 30 288 0.02

2 18 226 16 285 25 270 783 28 260 4705

3 11 252 15 280 30 294 132 30 290 0.15

4 9 203 18 221 30 288 118 30 264 0.01

5 10 226 12 272 25 260 94 25 260 0.03

6 15 227 10 285 18 238 226 30 275 6.41

7 15 234 14 285 20 285 782 25 270 1.46

8 14 232 20 285 20 288 152 25 270 1.55

9 10 231 20 285 28 288 161 30 288 0.01

10 20 215 6 304 20 260 1020 30 240 278.0

Total 2277 149 2757 244 2757 3548 283 2705 5088Our results dominate previous approaches in both yield and area

Experimental Results: Pareto Frontier

2500

3000

3500

4000

4500

5000

0 50 100 150Yield

Are

a

Our results establish a Pareto frontier representing a trade off between area and yield

Conclusions and Future Work

A new simple approach to reticle floorplanning taking yield as a constraint

An optimal area packer using branch and bound

Our results establish a Pareto frontier that trades yield for area

Our results dominate previous approaches

Respecting reticle aspect ratios

Different dicing plans for different wafers

Conclusions

Future Work

Thank you for your attention!