Roadmap of SiGe BiCMOS technologies
Greg U’Ren
Conexant SystemsApril 17, 2002
BiCMOS Technology at Conexant
0
25
5075
100
125
150175
200
0.01 0.1 1 10Ic (mA) for Minimum We and Le=1µm
Ft (G
Hz)
SiGe200
SiGe120
SiGe60
BC30
SiGe90
0.18 µmBiCMOS
0.35 µmBiCMOS
Continued dominance of bipolar in RFIC
• BJT/HBT higher performance than MOSFET– MOS moving from MHz to GHz– BJT moving from 1-2 GHz to >200 GHz
• Significantly lower cost than GaAs
• High-level integration complexity with BiCMOS technology at moderate cost penalty
SiGe RF big bang
• Exceptional technological progress in <5 yrs
• SiGe BJT on 6x faster performance curve
1988 1990 1992 1994 1996 1998 2000 2002 2004
50
100
150
200
250
~40 GHz / yr
~5 GHz / yr
BJT technology curve
SiGe
Si
Ft (G
Hz)
Year
Si SiGe
SiGe BiCMOS secures leading RFIC position
• CMOS and BJT technology advances along near-parallel paths
• SiGe maintains performance advantage ~2x over MOS at 0.10µm
0.7 0.6 0.5 0.4 0.3 0.2 0.110
100
< 1GHz
> 2GHz 2.5Gb/s
> 4GHz 10Gb/s
> 10GHz 40Gb/s
CMOS technology node trend comparison BiCMOS and Rf CMOS
Ft (G
Hz)
Technology Node
BJT SiGe RF CMOS
Technology cost comparisons
• Cost curves advance near-parallel
• BiCMOS has moderate cost penalty over CMOS at same technology node
0.5 0.4 0.3 0.2 0.10.1
0.2
0.3
0.4
0.5
0.6
0.70.80.9
1
CMOS
SiGe BiCMOS
Technology node cost trends
Rel
ativ
e co
st /
unit
area
Technology Node
SiGe CMOS
Performance-Cost comparisons
• Overall more performance at less cost
• skewed curves with advantage to BiCMOS beyond 0.10µm
0.5 0.4 0.3 0.2 0.10.002
0.003
0.004
0.005
0.006
0.0070.0080.0090.01
0.02
CMOS
SiGe BiCMOS
Normilised technology node cost for Ft GHz performance
Rel
ativ
e co
st /
unit
area
- G
Hz
Technology Node
SiGe CMOS
Wireless: 3G System Block Diagram
GPS
3G Radio
2.5G Radio
WLAN
Bluetooth™
A/D
Display
Keypad
Microphone
Speaker
Camera
BasebandProcessor(2.5G/3G)
Power Amplifiers RF Subsystem Baseband
CMOSGaAs or SiGe SiGe BiCMOS
Wireline: Optical Networking Block Diagram
MuxCMU
DemuxCDR
LimAmp
Receiver
Transmitter
TIA
Driver
PIN
Laser
Optical Module
ForwardError
Correction(FEC)
Framer
NetworkProcessor
NetworkProcessor
SwitchFabric
10 Gb: CMOS / SiGe BiCMOS40-80 Gb: SiGe BiCMOS / III-VCMOS III-V
Outline
• Device Design for 200 GHz Ft and Fmax
• 0.18 µm SiGe BiCMOS Process Integration
Device optimization parameters
• Aggressive vertical scaling to minimize diffusion component
– Band-gap engineering– Collector doping– Emitter resistance (Re)– Base width reduction (Wb)
• Aggressive lateral scaling to minimize depletion terms
– Emitter width (We)– SA emitter
( )12
2)(2
21
−
++++++==
s
c
b
bbccbcbe
cjcjee
ecT v
WDWCRCC
qIkTCCRf
ηπ
πτ
bcb
T
CRff
π8max =
Depletion terms diffusion
Device Design for 200 GHz Ft and Fmax
0
50
100
150
200
250
0.1 1 10 100Ic (mA)
Mea
sure
d Ft
(Ghz
)(Re + kT/Ic) (Cbe + Cbc) Wb2 / (2 Db)
SiGe Collector Doping
1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb2 / (2 Db) + Wc/(2 Vs) + Rc Cbc
0
25
50
75
100
125
150
175
200
0 1 2 3 4Normalized Collector Doping
Peak
Ft (
GHz
)
CalculatedMeasured
SiGe Emitter Resistance
1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb2 / (2 Db) + Wc/(2 Vs) + Rc Cbc
0
25
50
75
100
125
150
175
200
225
0 1 2 3 4Normalized Collector Doping
Peak
Ft (
GH
z)
2x Re
0.5x Re
SiGe Emitter Resistance
1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb2 / (2 Db) + Wc/(2 Vs) + Rc Cbc
0
25
50
75
100
125
150
175
200
225
250
0 1 2 3 4Normalized Collector Doping
Peak
Ft (
GH
z)
2x Re
Re=0
SiGe Base Width
1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb2 / (2 Db) + Wc/(2 Vs) + Rc Cbc
0255075
100125150175200225
0 1 2 3 4Normalized Collector Doping
Peak
Ft (
GHz
)
+12% Wb
-12% Wb Carbon Doping
+ Reduces B diffusion
Degrades mobility
Increases Eg
Reduces Wb
Only small improvement in Ft
Base narrowing for performance gain
0.0 5.0x10-6 1.0x10-5 1.5x10-5 2.0x10-5 2.5x10-5 3.0x10-5
40
60
80
100
120
140
160
180
Leap
Performance contribution from base narrowing
Ft
(GH
z)
Wb-2 (Å-2)
Ft
SiGe Base Width
050
100150200250300350
0 1 2 3 4
Normalized Collector Doping
Peak
Ft (
GHz
)
+12% Wb
-25% Wb, Re=0
Lateral Scaling
1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb2 / (2 Db) + Wc/(2 Vs) + Rc Cbc
Fmax = ( Ft / (8π Rb Cbc) )1/2
0
40
80
120
160
200
0.1 1 10 100Ic (mA)
Ft (G
hz)
0.30 µm
0.15 µm
0.20 µm
0
30
60
90
120
150
180
0.01 0.1 1 10 100Ic (mA)
Fmax
(Ghz
) 0.30 µm
0.15 µm0.20 µm
Good scaling properties maintain Ft constant as We is reduced increasing Fmax
SiGe BiCMOS Landscape (Dec ‘01)
0
50
100
150
200
250
0 50 100 150 200Fmax (GHz)
Ft
(GH
z)
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5Current Consumption* (mA)
Ft
(GH
z)
* Current required to reach peak Ft for minimum We and Le=1µm
200 GHz Ft/Fmax opens the door to 80 Gb applications in Silicon
Outline
• Device Design for 200 GHz Ft and Fmax
• 0.18 µm SiGe BiCMOS Process Integration
0.18 µm SiGe BiCMOS Process Integration
NFET and PFETSiGe NPN
N+ Buried Layer
Emitter CollectorBase
Deep Trench
Source
Gate
Drain
NwellPwell
P- Substrate
SiGe BiCMOS: Buried Layer Integration
1. N+ Buried Layer Implant2. Buried Layer Drive3. N- Epitaxy
P-N+N-
Lower Collector Resistance
Epi-Based Epi-Less
1. High energy N+ Buried Layer Implant
P-N+
Lower CostLower Collector Substrate Capacitance
SiGe BiCMOS: Isolation
1. Deep Trench Etch2. Deep Trench Oxide/Polysilicon Fill3. N/Pwell Formation
4x Lower Collector-Substrate Capacitance
Deep Trench Junction
• N/Pwell Formation
PN+
Lower Cost
SiGe BiCMOS: Collector Implants
Used to differentiate multiple NPNs on the same wafer
GateCollector Implants
Pocket/LDDImplant
0
10
20
30
40
50
60
70
1.E-05 1.E-04 1.E-03 1.E-02 1.E-01Ic (A)
Ft (G
Hz)
BVceo=2.5V
BVceo=3.8V
BVceo=6.0V
0.35 µm SiGe BiCMOS Example
Tradeoff between Ft, Cbc, and breakdown becomes a design variable
SiGe BiCMOS: Gate Formation
Gate Pocket/LDDImplant
Gate formed prior to SiGe deposition to minimize thermal budget on NPN
SiGe BiCMOS: Emitter-Base Integration
Sacrificial Emitter
+ Lowest Rb+ Best Scaling Properties
Extrinsic Base Implant
QSA Selective Epi
SiGe
+ Lowest Cost- High Rb
+ Easy “Plug-in” to Si NPN+ Cjc self-aligned to emitter- Requires selective SiGe
SiGe
Extrinsic Base Implant Spacer Separates EmitterFrom Extrinsic BaseEmitter Edge
Selective SiGe
SiGe BiCMOS: CMOS / Silicide
S/DImplants
CMOSSpacersCo Silicide
• NPN films completely removed from CMOS regions• Silicide on all electrodes including emitter, base and collector
SRAM Cell
SiGe120 Cross-Section6 Layers of Metal 1.5 fF/µm2 MIM Capacitor
25 Ω/sq Metal Resistor
3.0µm AlCu
2µm
1.5µm AlCu
W
NPN Transistor
Conclusions
• The bipolar device has continued dominance in RFIC space for theforeseeable future
– SiGe has opened a permanent gap in performance vs. CMOS
– SiGe BiCMOS Cost / Area / GHz is competitive with that of deep-subµ CMOS
• Aggressive vertical and lateral scaling has so far enabled 200 Ft/Fmax
– Advancement of vertical profile largely responsible for gains
– Further device / process optimization en route to 300Ghz