Scaling Challenges and Device Design Requirements for High Performance
Sub-50nm Gate Length Planar CMOS Transistors
T. Ghani, K. Mistry, P. Packan#, S. Thompson, M. Stettler#, S. Tyagi, M. Bohr
Portland Technology Development, #TCADIntel Corporation
2000 VLSI Symposium
Outline• Current Industry Status
• LGATE and VCC scaling projections
• Factors limiting Conventional Planar MOS scaling
• Conclusions
Current Industry StatusGeneration [n m ] 180
L GATE [nm] 100
V C C [Volts] 1.5
T O X (e) [n m ]
T O X (Phys) [n m ]
3.1
2.1
SDE Depth [nm] 50
SDE XUD [nm] 23
L M E T [n m ] 55
Channel Doping (cm-3
) 1018
CV/I (psec) 1.65
• 180nm logic technologynode already in production
• 180nm technology nodehas 100nm LGATE transistors (Intel, IEDM 1999)
• Projections to future nodesbased on extrapolating results from 180nm node
Outline• Current Status
• LGATE and VCC scaling projections
• Factors limiting Conventional Planar MOS scaling
• Conclusions
10
100
1000
800 600 350 250 180 130 100 70
Technology Node (nm)
Siz
e (
nm
)
Feature SizeGate Size
K=0.6
K=0.7
LGATE Scaling Projection• LGATE has recently scaled
at K~0.6x per generation
• Device design concernscould limit future LGATE
scaling to ~0.7x per generation
Node LGATE
(Projected)130 nm 70 nm100 nm 50 nm70 nm 35 nm
0
0.5
1
1.5
2
2.5
3
0100200300400Technology Node (nm)
VC
C (
Vo
lts)
3
4
5
6
7
8
Ga
te O
ve
rdri
ve
(V
CC/V
T)
GateOverdrive
VCC
VCC> 4VT
VCC Scaling Projection• Limited scalability of VTH
due to standby leakageconcern
• Gate overdrive decreasingwith successive generations
• Gate overdrive limitationsto slow VCC scaling to 0.8-0.85x per generation
• 70nm technology node will reach minimum VCC limit
• Current Status
• LGATE and VCC scaling projections
• Factors limiting Conventional Planar MOS Scaling
• Conclusions
Outline
• Transistor IOFF & VTH
• Gate Oxide Leakage
• Channel Mobility
• SDE Resistance
Top Four Transistor Scaling Issues
1.E-08
1.E-07
1.E-06
180 130 100 70
Technology Node (nm)
I OF
F (
A/ µ
m)
100o C
Room
3x
2x per genration
2x
3x
Transistor IOFF Limit• 2-3x IOFF increase projected
per generation
• 2x IOFF increase => 5% performance
• Maximum IOFF limit ~150 nA/µm for single-Vt process due to standby power concerns
• 100nm technology nodecould reach maximum IOFF limit
• Transistor IOFF & VTH
• Gate Oxide Leakage
• Channel Mobility
• SDE Resistance
Top Four Transistor Scaling Issues
0
1
2
3
4
5
250 180 130 100 70
Technology Node (nm)
Oxid
e T
hic
kn
ess (
nm
) Equivalent Oxide Thickness (Physical)
TOX
(Electrical)4.5nm
2.5
2.0
1.6
3.5nm3.1
2.1
1.5
1.00.6
Oxide Thickness Scaling Projection• ~2nm Physical Gate Oxide
in production at 180nm node
• Reduction in VCC scalingto limit TOX(e) scaling to 0.8x per generation dueto reliability consideration
KEY CONERNKEY CONERN:- Dramatic JOX increase
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
0.5 1.0 1.5 2.0 2.5
TOX-EFF Physical [nm]
J OX [A
/cm
2 ]180nm
Rodder et.al., IEDM98
ProjectedNitrided SiO2
SiO2 [Lo et. al, EDL97]
70nm Node
100nm
130nm
High-k Needed
Oxide Leakage Projections
• SiO2 gate leakage (JOX) extracted from Lo et. al. (EDL 1997)
• 100-200x JOX increase per generation
• Projected JOX ~100 A/cm2
for 100nm node for nitrided-oxides
Maximum Acceptable Gate LeakageEvaluation (Inverter FO=3)
VCC
0
IGATE
1 0W=2 µm
W=1 µm
W=6 µm
W=3 µm
IOFF
IGATE
• Compute static leakage components of inverter driving FO=3 load
• Projected JOX values andcritical dimensions usedto compute IGATE for nitrided-oxide
• Total Static Leakage = IGATE + IOFF
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
20 40 60 80 100 120LGATE [nm]
Sta
tic L
eaka
ge [n
A]
IGATE
(25 &100o C)
IOFF(100oC)
JOX=
100A/cm2 IOFF(25oC)
70 100 130 180Technology Node (nm)
Static Leakage Components• IOFF temperature acceleration
factors determined from experiment
• IGATE is relatively independent of temperature
•• 180nm & 130nm Nodes180nm & 130nm Nodes:IGATE << transistor IOFF
•• 100nm Node (100 A/cm100nm Node (100 A/cm22)): IGATE 7x less than IOFF at product operating temperatures
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
20 40 60 80 100 120LGATE [nm]
I GA
TE /
I OFF
Rat
io
25oC
IOFF=IGATE
100oC
70 100 130 180Technology Node (nm)
Gate Oxide Scaling Conclusions
• 100 A/cm2 feasible for logic products from static leakagestandpoint as long as it meets reliability criteria
• Nitrided-SiO2 extendable to 100nm technology node
• High-k dielectric will be necessary for 70nm technology node
• Transistor IOFF & VTH
• Gate Oxide Leakage
• Channel Mobility
• SDE Resistance
Top Four Transistor Scaling Issues
0
1
2
3
4
5
180 130 100 70
Technology Node (nm)
Ch
ann
el D
op
ing
x10
18(c
m-3
)
0
10
20
30
40
50
60
LM
ET (n
m)
LGATE (nm)
100 70 50 35
Channel Doping Level Trend
• Assumes UNIFORM doping
• NA increases to support lowertarget LMET at smaller TOX
• What is the impact of channel ionized impurity scattering on performance?
100
150
200
250
300
0 0.5 1 1.5EEFF[MV/cm]
Mob
ility
(cm
2/(
V.s
)
NA=
3x1017
1.3x1018
1.8x1018
2.5x1018
3.3x1018
LG= 50 nm
Channel Ionized Impurity ScatteringMeasured Results
• Start to see deviation from universal mobility curve at
~2x1018 cm-3 uniform doping levels
• Substantial mobility degradation observedat NA > 2x1018 cm-3
0
5
10
15
20
25
30
180 130 100 70
Technology Node (nm)
Mob
ility
Deg
rada
tion
(%)
0
2
4
6
8
10
I DS
AT
Deg
rada
tion
(%)
LGATE (nm)
100 70 50 35
Mobility
IDSAT
Channel Ionized Impurity ScatteringMobility and IDSAT Impact
• Significant channel impurity induced mobility degradationat 100 nm technology node
• Retrograded Channels:
PastPast: Improve SCE
FutureFuture: Mitigate mobility loss
due to channel impurities
• Transistor IOFF & VTH
• Gate Oxide Leakage
• Channel Mobility
• SDE Resistance
Top Four Transistor Scaling Issues
SDE Depth Requirement• XXJJ >> W>> WDEPDEP:
LOW sensitivity of SCE to SDE junction depth
•• XXJJ < W< WDEPDEP: HIGH sensitivity of SCE to SDE junction depth
• LGATE will be 20% higher @Fixed IOFF for 100nm technology node if SDEdepth is NOT scaled
0
20
40
60
80
100
120
0 20 40 60 80 100
SDE Depth (nm)
Gat
e Le
ngth
@F
ixed
I O
FF
(nm
)
100 nm Node0.7x XJ Scaling / generation
180nm Node
No XJ Scaling
SDE Doping Requirement
• SDE resistance starts tosignificantly increasebelow 35nm depth
• Super-activation of SDE dopant atoms importantknob in minimizingSDE resistance
100
200
300
400
500
600
700
800
10 20 30 40 50 60SDE Depth (nm)
SD
E R
esis
tanc
e ( Ω
. µm
) 2.5nm/dec
3x1019 cm-3
1x1020
1x1021
0
20
40
60
100 70 50 35
Gate Length (nm)
Dim
ensi
on (
nm)
LMET
SDE Underdiffusion
23nm
16nm11nm
8nm
55nm
40nm
27nm
20nm
180nm 130nm 100nm 70nm
SDE Under-Diffusion Requirement
• Current 180nm nodedevices have ~20-25nm SDE under-diffusion (XUD)
• SDE underdiffusion to scale by 0.7x per generation to meet LGATE target
• What limits XUD scaling??
Technology Node (nm)
Increase in Accumulation /Spreading Resistance
RSHUNT
RCONTACT RSPREADING
RACCUMULATION
n+
SDE
GateSilicide
Current Flow
Thompson et. al VLSI Symp. 1998
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20SDE Under-Diffusion (nm)
No
rma
lize
d I
DSA
T
(180nm node)
3.5 nm/dec
7 nm/dec
IDSAT vs. SDE Under-diffusion
•• Thompson et. al. (VLSI 1998)Thompson et. al. (VLSI 1998)::XUD limit of ~15-20nm prior toIDSAT degradation
•• This work (Simulation)This work (Simulation):Dramatic improvement in minimum XUD limit by improving lateral abruptnessby 2x
1
2
3
4
5
6
7
8
30 50 70 90 110LGATE (nm)
Required L
ate
ral
Ab
rup
tne
ss (
nm
/de
c) Constant RSDE
1x1020 cm-3
5x1019
3x1019
70nm 100nm130nm 180nm
Technology Node (nm)
SDE Lateral Abruptness Requirement
• Study abruptness requirementto maintain fixed RSDE down to35nm LGATE node
• 0.7x XUD and XJ scaling per generation
•• REQUIREMENTREQUIREMENT:2x more abrupt junction needed at 70nm node relative to current 180nm technology node
Conventional Planar CMOS Scaling Summary
Scaling Issue Limit Potential Solutions
Node
1 Gate Leakage ~ 100 A/cm2 High-k dielectric 70 nm
2 Transistor IOFF / VTH ~ 150 nA/µm Lower Operating
Temperature
70 nm
3 Channel Mobility NA ~ 2x1018 cm-3 Retrograde channel 100 nm
4 SDE Resistance XUD~15-20nm
XJ~ 35nm
Fast Ramp Anneal?
Laser Anneal?
100 nm
Conclusionsl Planar conventional CMOS transistors can be scaled to 100nm
technology node (50nm LGATE ). 70nm node also a possibility.
l New scaling issues to appear at 100nm technology node:- Channel Mobility loss- SDE Resistance
lNew scaling issues to appear at 70nm technology node:- Transistor IOFF / VT non-scalability- Gate Leakage
lDevice design requirements and potential options to mitigate scaling bottleneck were identified
