Slides Parte1 Rev2010

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CMOS transistor circuits

CMOS technologyThe MOS transistor

Electrical behavior of the MOStransistor



Contents

• Importance of MOS technology

• The MOS transistor

• Manufacture steps of MOS technology

• Electrical model of the MOS transistor• Simple circuits with MOS transistors

• Noise model



Origin of the Integrated Circuits

• Theory of MOS integrated circuits was developed in

1925 with the invention of MOS-transistor.

• The first process of fabrication with enough robustnessonly succeeded in the 60’s.

• Quality control problems as well as the use of somematerials only allow to develop commercial productsalready in the 70’s.

• Due to its simplicity and low fabrication cost, MOStechnology is usually preferred rather than any other.



Moore’s Law• In 1965 Gordon Moore noted that the number of

transistors in a IC doubled every two years

• This observation become the roadmap for every ICmanufacture leading to a doubling in the performance ofIC every two years

• Sometime soon it will be impossible to continue to

reduce the size of the transistors due to physical limits



CMOS technology• There are several types of technologies available to build

IC (BiCMOS, bipolar, GaAs, etc)• A large part of the success of the MOS transistor is due

to the fact that it can be scaled to increasingly smallerdimensions, which results in higher performance.

• The ability to improve performance consistently whiledecreasing power consumption has made CMOSarchitecture the dominant technology for integrated

circuits.• Due to its versatility CMOS technology represents the

majority of the manufactured IC in the world.



Available elements in CMOS technology

• Capacitors with a good relative accuracy (+/- 0.1 a 0.4%)and reasonable absolute accuracy (5 a 15 %);

• Poly-silicon and diffusion resistors with good linearity butwith bad absolute accuracy (+/- 25 a 50%);

• NMOS e PMOS transistors. Very good performance interms of speed and accuracy;

• Bipolar NPN or PNP transistors depending whether thesubstrate is P-type or N-type. Very low current-gain andvery weak speed performance due to the existence of aparasitic collector connected to the substrate.



A cross section of a MOS transistor

n+n+

Gate

SiO2

W

L p- substraten-channel

GS D

B

L

G

S D

W

L



Most commonly used symbols forMOS transistors & conventions

NMOS (symbol 1) PMOS (symbol 1)

NMOS (symbol 2) PMOS (symbol 2)

NMOS PMOSV GS

I G=0

I G=0

V DS

V SD

I D I D

D

G

S

DS

G

V SG



CMOS fabrication steps• The manufacture of CMOS ICs is based on the

repetition of 5 steps: – Creating patterns on the wafers using photo

lithography (patterns defined by masks)

– Oxidizing the wafer in order to create a layer of SiO2

(silicon dioxide) or nitrate oxide – Etching material from the wafer (where not protected

by masks)

– Implanting and diffusing impurities

– Material deposition (silicon and metal)



CMOS fabrication flow (simplified)

Wafer (p-)

The process starts with silicon wafer, normally lightly doped P type

Wafer (p-)

Si02

A layer of SiO2 on top is created by oxidizing the wafer at high temperature

(dry or wet oxidation can be used)




Wafer (p-)

Si02Photoresist

A a layer of photoresistant material is spread on top, exposed with UV light in

areas defined by a mask and then developed, leaving exposed areas.

Wafer (p-)

Si02

The unprotected oxide is removed using dry or wet etching methods.

An ion beam of doping atoms is applied to the wafer, these atoms do notpenetrate the silicon crystal where it is protected by the silicon oxide.




Wafer (p-)

n-well (n-)

The oxide is etched away and the wafer is heated in a furnace (annealing) to causethe doping atoms to diffuse and to repair crystal defects caused by the implanting ions

Wafer (p-)n-well (n-)

Si02

A new layer of oxide is grown on top of the wafer and etched away, this oxide isalso know as field oxide and will be used to separate the transistors




Wafer (p-)

n-well (n-)

Si02

Thin oxide (gate oxide)

A thin layer of oxide is grown on top of the wafer, this will become the gate oxide

Wafer (p-)

n-well (n-)

Si02

Polysilicon is deposited on the wafer and then the etched away, except where

defined by a mask




Wafer (p-)

n-well (n-)

Si02

The thin oxide is etched away, the opening defines the active areas where P or N

doping atoms will be implanted and diffused.

Wafer (p-)

n-well (n-)

Si02




Wafer (p-)

n-well (n-)

Si02

N+ N+ P+ P+

The process is repeated for the P+ active areas and finally the transistors aredefined.

The next steps might apply Titanium or other metal on top of the polysilicon inorder to reduce its resistance (salicide)



The latch-up problem

Wafer (p-)

n-well (n-)

Si02

N+ N+ P+P+

P+ N+

Vss Vdd

N+P+ N- P-

Rsub

Rnwell



The latch-up problem

Rsub

Rnwell

Vss

Vdd

Vss

Vdd

IC1

IC2

Rsub

Rnwell

Vss

Vdd

0.7 V

Vdd-0.7 V

IC1

IC2

OFF State

IC1=IC2=0A

ON StateIC1and IC2 can be large !!!



The MOS capacitor behaviorS D

VB=0V

+ + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + +

N+ N+

P-

VG=0V

Depletion zone Depletion zone

S D

VB=0V

+ + + + + + + + + + + + +

+ + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + +

N+ N+

P-

VG>0V



The MOS capacitor behaviorS D

VB=0V

+ + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + +

N+ N+

P-

Depletion zone

VG=V

T

S D

VB=0V

+ + + + + + + + + + + + + + + + + + + +

N+ N+

P-

VG>V

T

Depletion zone- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

channel



The MOS capacitor behavior• V G < 0: Positive charges are concentrated in the channel

region under the gate terminal;• 0 < V G < V T : The channel region looses carriers

becoming progressively a depletion layer

• V G > V T : The electric field is strong enough to attract

electrons that create an inversion conducting layer. Thecapacitance value is restored to its maximum.



The MOS transistor in the cut-off

and weak inversion

V S

= 0 e 0 < V DS

<< 1V GS < 0, Drain and substrate terminals form a reversed-biased p-n

junction => I D = 0;0 < V GS < V T , The channel regions is in depletion => I D ≈ 0

The device is operating in weak inversion.

S D

VB=0V

+ + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + +

N+ N+

P-

Depletion zone

VB=V

T VD>0V



The MOS transistor in the linear

region

For V GS > V T the channel region is inverted into n-type, and

the drain becomes connected to the source. A positivedrain current occurs.

For low V DS voltages (close to 0, the channel region

behaves like a resistor and we have that I D = V DS / R , whereR is the channel resistance.

( )

( )

1

"overdrive" or VDS saturation voltage (VDSsat)

D n ox GS T DS

DS

Dn ox GS T

GS T

W I C V V V

LV

RW I

C V V L

V V

µ

µ

= − ⋅

= =

−

− − >



The MOS transistor in the triode

region

For V GS > V T e 0 < V DS < (V GS - V T ) the channel potential is not zeroanymore and the drain current becomes defined by:

( )2

2

( )

DS

D n ox GS T DS

DSsat GS T

V W I C V V V L

V V V

µ = − ⋅ −

= −



The MOS transistor in the

saturation (active) region

S D

VB=0V

N+ N+

P-

VG>V

T

Depletion zone

channel pinch-off

VD>V

G-V

T

For V GS > V T e V DS > (V GS - V T ) the gate-to-channel voltage closeTo the drain is not enough to keep the channel formed. The channelis then interrupted by a depletion region (is pinched-off).



The MOS transistor in the

saturation (active) region

I D current becomes nearly constant and defined by:

( ) ( )2

DS

2

( ) V saturation voltage

For

n ox

D D DS Dsat GS T

DSsat GS T

DS DSsat

C W I I V I V V

L

V V V

V V

= ≅ ≡ −

= − − >

>

• For analogy with the BJTs, this region is also often called“active region”.



Models and operating regions

Summary

I D

I D

V GS

V Tn V

DS V

DSsat

V GS =constant

Triode

region

Active

region

Linear

region

Strong

Inversion

Weak

InversionCut-off

Vdsat = Veff = (V GS - V T )




(channel modulation effects)

( ) ( ) ( )constantmodulationchannel

12

2

λ

λ

µ DS TnGS

oxn Dsat DS D D V V V L

W C

I V I I ⋅+−≡≅=

In fact, I D increases a little with V DS ! This is due to an effective

shift of the pinch-off point leading to a smaller channel lengthI D becomes dependent of V DS accordingly to:

• This effect is much more significant when short channels(minimum L) are used! Avoid using minimum channel lengthsin analogue design whenever necessary!



Models and operating regions(channel modulation effects)

I D

V DS V

DSsat

V GS

=constant

Channel

modulation

Short-channel

effects




(body effect)

• It exists whenever V S is different from zero.

• The threshold voltage, V Tn , becomes dependent (increases) withV SB = V S - V B .

( )

0

2 2 2

2

: threshold voltage for 0;

: 0.3 V, contact potential;; 11.7;

: carrier density at the surface;

Tn TOn p SB p

S imp

ox

TO SB

P

S S S

imp

V V V

q N

C

V V

K K

N

γ φ φ

ε γ

φ ε ε

= + ⋅ + − ⋅ ⋅

⋅ ⋅ ⋅=

=

≅

= ⋅ =




(some weak inversion details…)

• For 0 < V GS < V Tn , I D current is not zero! In fact, the density of

carriers in the channel is not zero but it increases exponentiallywith V GS .• I D (V GS ) is an exponential relationship and the MOS devicebehaves as a slow bipolar transistor;

• This region is very useful in low-speed ultra-low power circuits;Very high dc gains can be achieved.

{ };2,1;

25

0 ∈⋅=

≅=>>

⋅

ne I I

mV q

KT V V

qKT n

V

D D

T DS

GS



Models and operating regions(generalizing for the PMOS transistor)

• 2 main voltages exchange signals (source terminal at a highervoltage);

• Threshold voltage, V Tp , is negative;

• Mobility of holes is 1/3 a 1/2 smaller than the mobility of electrons:

µ p = µ n / 2.5;

• All expressions derived are valid for all regions.



Biasing MOS transistors (DC)

(simple current-mirrors)

Vdd

Iout

M1MB

Iin

W M1 = 10*W MB

LM1 = LMB

Iout ( Iin) = ?



Small signal analysis

(saturation region)




(saturation region)




(saturation region and low-frequency)

vGS

gm.vGS gsb.vSB

vSB

G D

S

B

rds=1/gds

• Neglecting the body-effect gsb = 0



MOS parasitic capacitances

S D

N+ N+

P-

VG>V

T

Depletion zone

VD>V

G-V

T

C SB

C DB

C GS

C GD




(saturation region and high-frequency)

CgsvGS

gm.vGS gsb.vSB

vSB

G D

S

B

rds=1/gds

Cgd

Cdb

Csb




(saturation region and high-frequency)

Cgs = 2/3 W. L . Cox + W . Lov . Cox [Tsividis, 1987]

(Cox -> 0.002 pF / um2 , for example)

Csb = (As + Achannel ) . Cjs

(Cjs -> non-linear depletion capacitance of the

source-substrate junction (voltage dependent)).

Cdb = Ad . Cjd

(Cjd -> non-linear depletion capacitance of thedrain-substrate junction (voltage dependent)).

Cgd = W . Lov . Cox (Miller capacitance)




(linear/triode region and high-frequency)

Cgs Cgd

Csb Cdbrds

G

S D




(linear/triode region and high-frequency)

Cgs = Cgd = 1/2 W. L . Cox + W . Lov . Cox (Cox -> 0.002 pF / um2 , for example)

Csb = Cdb = (As + Achannel/2 ) . Cjs (Cjs -> non-linear depletion capacitance of thesource/drain-substrate junction (voltage dependent)).




(cut-off region and high-frequency)

Cgs Cgd

Csb Cdb

G

S D

Cgb

Cgs = Cgd = W . Lov . Cox

Cgb = W . L . Cox



NOISE• Noise can be considered as any undesired signal that is

added to the desired signal.

• Noise can be divided into 2 categories:

– “Deterministic noise”: this is due to deterministic sources such asinterference from other signals. This noise can be greatly

reduced by minimizing the coupling of the offending signals (atsystem level by using appropriate filters and at physical level byusing appropriate shielding).

– Random noise: this is due to random effects and it is present at afundamental level in most electronic components, it can be

reduced by careful circuit design.

• The objective is to maximize the Signal to Noise ratio



Properties of random signals• It is not possible to predict the value of a random signal at a given

time instant.

• It is possible to predict its statistical properties, such as average valueand power value (standard deviation).

Signal 1 P=1 W Signal 2 P=1 W

2 / 2

/ 2

( )lim

T N

N T T

v t P dt

R−→∞

= ∫



Properties of random signals• A random signal can also be characterized by its power spectral

density (PSD).

• The PSD shows the average power of the signal per bandwidth.

• The power of a random signal can be calculated using:

• The PSD of a filtered random signal can be calculated using:

( )( ) N

N

P f S f

f ≈

∆

0

( ) N N

P S f df ∞

=

∫2

0( ) ( ) ( )

Nout NinS f H f S f df

∞

= ⋅∫



Noise in electrical circuits• In electrical circuits there are 5 common noise sources:

– Shot noise

– Thermal noise

– Flicker noise

– Burst noise

– Avalanche noise



Shot noise• Shot noise is always associated with current flow. Shot

noise results whenever charges cross a potential barrier,such as a PN junction. A carrier crossing the potentialbarrier is a purely random event. Thus the instantaneouscurrent, I , is composed of large number of random,

independent current pulses with an average value, I D .• Shot noise is independent of temperature.

• Shot noise can be represented as a noise current with apower spectral density given by: 2 I e DS q I = ⋅ ⋅



Thermal noise• Arises from the thermal fluctuations in the

electron density within a conductor. – “Statistical fluctuation of electric charge exists in all conductors,

producing random variation of potential between the ends of theconductor. The electric charges in a conductor are found to be ina state of thermal agitation, in thermodynamic equilibrium with

the heat motion of the atoms of the conductor. The manifestationof the phenomenon is a fluctuation of potential differencebetween the terminals of the conductor” – J.B. Johnson

• Experimentally demonstrated by Johnson in

1926• Theoretically derived by Nyquist in 1928



RC output noise voltage



Flicker noise• Flicker noise is also called 1/f noise. It is present in all active devices

and has various origins.

• Normally it is associated with impurity atoms in the semiconductorcrystal.

• These impurities create energy states that trap and release thecarriers.

• The power spectral density is given by:• Normally PMOS transistors have less flicker noise than NMOS

transistors

• If the physical size of the transistor increases the corresponding

flicker noise decreases

1Vf

ox

K

S C W L f = ⋅⋅ ⋅

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