Department of Electrical and Computer Engineering

Vishal Saxena -1-

Subranging, Folding and Interpolation ADCs

Vishal Saxena, Boise State University(vishalsaxena@boisestate.edu)

Vishal Saxena -2-

Subranging ADCs

2

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Inefficiency of Flash ADC

– 3 –

Only comparators in the vicinity of Vin are active at a time → low efficiency.

Enc

oder

VFS Vi

fs

Strobe

Do

2N-1comparators VFS

0

2N-1

Vi

Do

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Segmented Quantization

– 4 –

Analog pre-processing

divides Vin into 2M

uniformly-spaced

segments.

VFS

0

2N-1

Vi

Do

1 2 3 4 5 6 7 8

Segment indicator (M bits)

Fine quantization(N-M) bits

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Typical Subranging Block Diagram

– 5 –

Do

Ref

eren

ce L

adde

r Coarse ADC

Enc

oder

Fine ADC

ViVRT

MSB’s

LSB’s

SHA

VRB

SHA

MUX

4 bits

5 bits

8 bits

Redundancy in fine ADC provided by over- and under-range comparators

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Subranging ADC Architecture

Vi

VRT

VRB

Fine Encoder

MSB’s

LSB’s

Fine Flash

Coarse Flash

• Coarse comparators are connected to the coarse reference ladder taps

• When the MSBs are obtained, the fine ladder taps are addresses and

then fine conversion takes place

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Digital Redundancy in Fine ADC

– 7 –

• The range of fine search extended on both sides (over and under ranging)

• Corrects for small errors encountered in coarse conversion step

• Fine conversion comparators are critical (PA+AZ)

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Two-Step Subranging/Pipelined ADC

– 8 –

Coarse ADC

Fine ADCVi

MSB’s

LSB’sSHA

VR

RA

2n1

D/A

SHA

VR

• Coarse-fine two-step subranging architecture• Conversion residue produced instead of switching reference taps• Residue gain can be provided to relax offset tolerance in fine ADC• Very similar to the pipelined architecture

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Timing Diagram

– 9 –

• Four conversion steps can be pipelined (needs op-amp)

• Usually DAC + RA settling consumes most of the conversion time

• Residue gain of unity is often used to speed up conversion

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Interpolation

10

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Preamp Interpolation

– 11 –

Uniformly spaced zero-crossings in flash ADCs (Vout vs Vin)

Ref: R. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADCincorporating folding and interpolation techniques," IEEE Journal of Solid-StateCircuits, vol. 22, pp. 944-953, issue 6, 1987.

Vo1 Vo

2 Vo3

VR1 VR

2 VR3

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Resistive Interpolation

– 12 –

• Intermediate zero-crossings are recovered by interpolation.

• DNL is improved by voltage interpolation.

• Requires overlapped linear regions between adjacent preamps.

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Interpolation Nonlinearity (I)

– 13 –

• Nonlinear TF of preamps cause errors in the interpolated zero-crossings.

• Interpolation nonlinearity directly translates into DNL and INL.

• Impedance mismatch due to interpolation also causes dynamic errors.

VA

VB/4+VA*3/4

VA/2+VB/2

VB*3/4+VA/4

VB

A

B

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Interpolation Nonlinearity (II)

– 14 –

Ref: R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-Nyquist analog-to-digital converter," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1334-1344,issue 6, 1988.

• Interpolation factor of 4

• Latch input bandwidthequalized

• Critical if input SHA isnot used

• Nonlinear interpolationerrors remain

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Interpolation Nonlinearity (III)

– 15 –

Ref: P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding andinterpolating ADC," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1876-1886,issue 12, 1997.

• Resistive mesh networkimproves impedancematching at latch input.

• 2-stage (2X) interpolation avoidsthe interpolation error.

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Capacitive Interpolation

– 16 –

K. Kusumoto,

JSSC, Dec. 1993

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Current Interpolation

– 17 –

Less accurate then voltage interpolation due to mismatch of current mirrors

Ref: M. Steyaert, R. Roovers, and J. Craninckx, "100 MHz 8 bit CMOS interpolatingA/D converter," in Proceedings of IEEE Custom Integrated Circuits Conference,1993, pp. 28.1.1-28.1.4.

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Features of Interpolation

– 18 –

• Reduces the total number of preamps by the interpolation factor• Reduces the total input capacitance (larger input BW)

• Total number of latches stay the same

• More area- and power-efficient than straight flash ADC

• Voltage interpolation improves DNL (error averaging)

• Loading of interpolation network decreases the preamp gain/BW

• Subject to preamp nonlinearities

Vishal Saxena -19-– 19 –

Folding ADCs

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Inefficiency of Flash ADC

– 20 –

Only comparators in the vicinity of Vin are active at a time → low efficiency.

Enc

oder

VFS Vi

fs

Strobe

Do

2N-1comparators VFS

0

2N-1

Vi

Do

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Segmented Quantization

– 21 –

Analog pre-processing

divides Vin into 2M

uniformly-spaced

segments.

VFS

0

2N-1

Vi

Do

1 2 3 4 5 6 7 8

Segment indicator (M bits)

Fine quantization(N-M) bits

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Signal Folding

– 22 –

• Analog pre-processing→ folding amplifier

• Folding factor (F) isequal to the number offolded segments.

Segment indicator (log2(F) bits)

Fine quantizationN-log2(F) bits

VFS

0

2N-1

Vi

Do

1 2 3 4 5 6 7 8

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Folding ADC Architecture

– 23 –

• The fine ADC performs amplitude quantization on the folded signal.

• The coarse ADC differentiates which segment Vin resides in.

out

iR

F = 8

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Folding Amplifier

– 24 –

F = 3Vo+

Vo-

Vi

M1 M2 M3 M4

RL RL

M5 M6

VR/2 5VR/6VR/6

Vi

Vo

ISRL

0

ISISIS

-ISRL

VR1 VR

2 VR3

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Signal Folding

– 25 –

Pros

• Folding reduces the comparator number by the folding factor F,while the number of preamps remains the same.

Cons

• Multiple differential pairs in the folder increases the output loading.

• “Frequency multiplication” at the folder output.

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Frequency Multiplication

– 26 –

)F2(sin

fπf1

inmax

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Folding Amplifier

– 27 –

F = 3Vo+

Vo-

Vi

M1 M2 M3 M4

RL RL

M5 M6

VR/2 5VR/6VR/6

Vi

Vo

ISRL

0

ISISIS

-ISRL

VR1 VR

2 VR3

Zero-crossingsare still precise!

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Zero-Crossing Detection

– 28 –

• Only detect zero-crossings instead of fine amplitude quantization→ insensitive to folder nonlinearities.

• P parallel folding amplifiers are required.

F = 3, P = 4

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Offset Parallel Folding

– 29 –

• Total # of zero-crossings = Total # of preamps = P*F• Parallel folding saves the # of comparators, but not the # of preamps

→ still large Cin.

F = 3, P = 4

Folder 2 V2

Folder 1 V1

ViVR

Folder 3 V3

Folder 4 V4

Vi0

Vi0

Vi0

Vi0

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Folding + Interpolation

– 30 –

Vi

Cross-connectP & N sides atthe endpoints

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“Rounding” Problem

– 31 –

• Large F results in signal “rounding”, causing gain and swing loss.

• Max. folding factor is limited by Vov of folder and supply voltage.

F = 3

F = 9

Vi0

Vi0

Vo

Vo

2√2(Vgs-Vth)

2√2(Vgs-Vth)

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Folding vs. Interpolation

– 32 –

Folding• Folding works better with non-overlapped active regions between

adjacent folders.• Large Vov (for high speed) of folders and low supply voltage limit

the max. achievable F.

Interpolation• Works better with closely spaced overlapped active region between

adjacent folding signals.

Observation• Small F and large P (parallel folders) will help both folding and

interpolation, but introduces large Cin – approaching flash…• What else can we do?

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Cascaded Folding

– 33 –

• Ideal: A large folding factor F can be developed successively.

• Small F in the 1st-stage folder → large Vov, less capacitive loading, andless frequency multiplication effect.

F = 3

F = 9

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Cascaded Folder Architecture (I)

– 34 –

• Gilbert four-quadrant multiplier based folding amplifier

• Only works with even P, requires a lot of headroom

F = ?

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Cascaded Folder Architecture (II)

– 35 –

• Simple differential pair-based folding amplifiers

• Only works with odd P, compatible with low supply voltage.

Vi

Vo+

Vo-

F = ?

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Mechanical Model of Cascaded Folding

– 36 –

Bult (JSSC’97)

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Distributed Preamplification

– 37 –

Large signal gain developed gradually along the signal path

→ from “soft” to “hard” decision

Input and Reference Ladder

1st-stage Folding and Averaging

Interpolation and 2nd-stage Folding

Interpolation and Averaging

Comparators

Gain

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Useful Formulas

– 38 –

Assuming a two-stage cascaded folding & interpolating ADC,

F1 = 1st-stage folding factor, F2 = 2nd-stage folding factor,

P = # of offset parallel folders, I = total interpolation factor,

then,

Total # of decision level = P*F1*IADC Resolution = Log2(P*F1*I)

Total # of fine comp = P*I/F2

Total # of coarse comp = P*F1 or P+F1?where, usually P = F2 holds.

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Circular Thermometer Code

– 39 –

• Very tight coarse comparator offset requirement (<1/2 LSB)

• Aperture delay b/t coarse and fine worsens the problem.

overflow

underflow

F = 4

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Coarse-Fine Sync (Bit Alignment)

– 40 –

• “Coarse” fold indicator with offset thresholds combined with the output offine comparator A precisely determines which fold Vin resides in.

• Large tolerance on coarse comparator offset and aperture delay errors

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Useful Formulas

– 41 –

Assuming a two-stage cascaded folding & interpolating ADC,

F1 = 1st-stage folding factor, F2 = 2nd-stage folding factor,P = # of offset parallel folders (P>F2), I = total interpolation factor, then

total # of decision level = P*F1*I,ADC Resolution = Log2(P*F1*I),

total # of preamps in 1st folder = P*F1,total # of preamps in 2nd folder = P,total # of fine comparators = P*I/F2,

total # of coarse comparators = F1*F2, F1+F2, or F1+P?

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Cascaded Offset Bit Alignment (I)

– 42 –

• F1 coarse comparators at input and P coarse comparators at 1st-stagefolder outputs resolve F1*P (>F1*F2) folds.

• One fine comparator output is utilized to perform offset bit alignment.

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Cascaded Offset Bit Alignment (II)

– 43 –

Two-step offset bit alignment – large offset tolerance on F1 coarsecomparators and medium tolerance on P comparators.

Ref

eren

ce L

adde

r

F 1C

mp’

s

Dig

ital L

ogic

1st-s

tage

Fol

ders

(P*F

1)

2nd-s

tage

Fol

ders

(F2)

PC

mp’

s

Fine

Com

para

tors

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References1. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog

Converters,” 2nd Ed., Springer, 2005..2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.3. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.