IEEE Transactions on Nuclear Science, Vol. NS-28, No. 6, December 1981

TERMINAL MODELING OF HARDENED INTEGRATED CIRCUITS

C. T. Kleiner, R. Haas, M. Peacock, G. MandelG. C. Messenger D. Weakley, Vince DeMartino

Rockwell International3370 Miraloma Avenue

Anaheim, CA

SUMMARY

A technique for device terminal modelinghardened DIICs for TREE has been described. Theresult provides a methodology which has been success-fully applied to 16 ICs described in a previous paper(Ref 1).

Because of the inherent flexibility of themodeling technique presented in this paper, theauthors have extended the application to include otherparts including more advanced Schottky TTL devices.This also includes subroutines for beta degradation,including rapid anneal.

The models can be made available through theSYSCAP II program described in Ref (3).

INTRODUCTION

In a previous paper (Ref 1) the authordescribed the modeling and test verification tech-niques used to develop medium-scale, DielectricallyIsolated Integrated Circuits (DIIC). This paperdescribes how the same circuits have been modeled forapplication by design and radiation hardening engi-neers. The part types modeled are shown in Table 1.

Table 1. DIIC Parts Modeled

Name Source Control Drawing Nearest Common Equivalent

Quad 2 NAND 477-1269 SN54LSOO

Dual 4 NAND 477-1270 SN54LS20

Dual Line Receiver 477-1280 9615

Operational Amplifier 477-1281 HA2620

Dual J-K F/F 477-1271 SN54LS112

Dual 4-1 MUX 477-1272 SN54LS253

Dual DEMUX 477-1273 SN54LS155

4-Bit Counter 477-1276 SN54LS193

4x4 Register File 477-1284 SN54LS670

Sense Amplifier 477-1285

Dual Analog Switch 477-1283 DG191

4-Bit Register 477-1277 SN54LS194A

ALU 477-1274 SN54LS181

ROM 477-1275 SN54187

PROM 477-1286 (Electrical/FunctionalOnly, No Radiation)

THE PROBLEM

In the process of developing the hardened partsdescribed in (Ref 1), the part manufacturers usedcomplex, detailed Computer Aided Design (CAD) modelswhich included many internal "elements" and param-eters. Various codes were used to develop these CADmodels including: SPICE, SYSCAP, RCACAP, and others.Single computer runs using the complex "element"models were lengthy and not intended for applicationsor hardness analysis at the circuit board or systemlevel. To significantly reduce model complexity andcomputer run time, a simplification of the CAD modelswas deemed necessary. This simplification processhas been described in a previous paper (Ref 2), butwas oriented to EMP rather than Transient RadiationEffects on Electronics (TREE) and was directed to an

earlier part type (SSI).

TECHNICAL SOLUTION

The initial concept (Ref 2) used the detail ele-ment model and electrical tests at the terminals todevelop segmented (piece-wise linear) characteristicsof the input and output terminals of the device whichwere controlled by FORTRAN statements based on termi-nal voltage, current, and loading conditions. Thistechnique proved unsatisfactory for TREE with theresult that the following solution was used:

1. The input circuit of the detailed elementmodels is used at the immediate monitoringinput terminal interface.

2. A "simplified" internal equivalent monitor-ing point is selected for functional(FORTRAN) monitoring.

3. The monitoring point(s) are processedthrough a FUNCTION (Ref 3) to control theoutput, which in the case of the digitalICs, is a "totem-pole" circuit.

4. The "simplified" internal equivalent of theoutput totem-pole model is modified tosatisfy terminal model requirements.

5. The photocurrent generators are included inthe SYSCAP II Code (Ref 3).

6. Parameter degradation is included inseparate FUNCTION (Ref 3) which reduces theoutput totem-pole transistor gain as afunction of (a) neutron fluence or (b) totaldose.

DESCRIPTION OF TERMINAL MODELS

The parts like those listed in Table 1 aredesigned by the part vendor by using a variety ofcomputer-aided design programs. These veiidor CADmodels are often termed detailed element models. Thevendor CAD models are complex, expensive to run, anduse a significant amount of computer memory space.

The designers use the design guidelines and thecomponent source control drawings to initially designthe computer circuits. Terminal models were developedto aid in the worst-case circuit analysis, NuclearHardness and Survivability (NH&S) predictions, Relia-bility Analysis (part application review), and FailureMode and Effects Analysis. Typically, computer run

time for terminal models is at least one order ofmagnitude lower than vendor CAD models. The terminalmodels include:

1. Terminal characterization

2. Source control drawing specification data

3. Input circuit (including radiation effects)

4. Output circuit (including radiation effects)

0018-9499/81/1200-4334$00.75© 1981 IEEE4334

5. Non I/O section modeled as a function

6. Power supply loading (including radiationeffects)

The models are baselined to source controldrawings and supplemental test data (primarily radia-tion effects data) presently available to the computerdesigners and NH&S and Reliability engineers. Theterminal and/or detailed models can also be used tofill-in for unspecified or untested part application/specifications.

The concept for IC terminal models was origi-nally developed by the undersigned and associatesduring the In-Place EMP program. This concept isdocumented in (Ref 2). The modeling described hereinretains the accuracy of the vendor-generated detailedmodels by using simplified input/output circuit ele-ments and substituting transfer functions (in theform of FORTRAN subroutines) for the IC internal cir-cuitry. The terminal models account for thefollowing:

1. Electrical Response - Input/output, powersupply, and loading effects

2. Nuclear Radiation - Degradation, ionizingthreshold (short and long pulse), andprompt survival pulse response

The models represent nominal and selected worst-case conditions (i.e., maximum propagation delay,minimum output current sink capability, and minimumradiation threshold levels). The data base for theterminal models is derived from the following sources:

1. Source control drawings

2. Vendor-developed detail models (whereavailable)

3. Hardened parts review data

4. Supplemental lab test data

5. Engineering judgment when (1) through (4)above do not provide required data, e.g.,unspecified/untested characteristics.

EXAMPLE NAND GATE

A detailed schematic for one-fourth (one gate)of the 477-1269 Quad Dual-Input NAND gate IC is shownin Figure 1. The input structure for the terminalmodel of one gate is shown in Figure 2. The inputdiodes (Dl through D4) along with resistor RI(= 16 kQ) are the same as the input on the detailedmodel. The diode tied between Rl and ground (calleddiode DQ15 or DQ) has an 'M' such that the drop at thesumming node (point where diodes D3, D4, and DQ meet)is equivalent to the voltage at the same node in thedetailed model. When both inputs to the gate arehigh, diodes D3 and D4 are reverse biased and DQ isturned on. Current through DQ is:

IDQ - CC ( BEQ1 + VBEQ5) (1)DQ Rl )

A Computer-Aided Analysis (CAA) on the detailed model,with VCC = 5 V and Rl = 16 kQ shows that under theabove conditions VBEQ1 = 0.744 V and VBEQ5 = 0.74 V.

Figure l.Detailed Circuit Model of Quad 2-Input NAND Gate

Figure 2. Input Circuit for 2 In. NAND Gate Terminal Model

I =5 - 1.484 0.22 mA (2)

=.0x -15Using an = x10 A and RB = 638 Q for DQ and

utilizing the CAA diode equation, solve for " Q.

(VBEQ1 +VBEQ5) -BR DQ _1MDQ 0.026 x Zn(IDQ/Is + 1) (3)

The output structure for the terminal modelconsists of a totem-pole arrangement of two transis-tors as shown in Figure 3. The similarity between thetwo (terminal and detailed model) outputs has provento be a close match compared to previous modelingefforts. When the output is in the low state, tran-sistor QUP is turned off by changing its RB to a largevalue. Transistor QLO is driven into saturation bylowering its RB to account for the current provided

by R2 (= 4 kQ) as in the detailed model. Thus, RBmust have a value consisting of the RB of Q5 (detailedmodel), R2 and the drop across Q1.

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*RADIATION EFFECT DIODECOMBINES Rl P-N JUNCTION ANDPHOTOCURRENT IN Q1

15 VFDQ15 - VBEQ1 + vBEQ5

NOTE: THE TWO VBE DROPS OF

Ql + Q5 ARE COMBINED INONE DIODE MODEL WHERE:

R5

Q3LlDETAILED(TOTEM POLE)

0 _. UP M- 2

z~~~~~~~~~~~4*itvpp

M~~~~- - 2

TRANSFORMED TO: SIMPLIFIEID OUTPUT(TOTEM POLE)

*PHOTOCURRENT GENERATORSINCLUDED IN MODEL

Figure 3. Output Circuit for 2 InputNAND Gate Terminal Model

VccCC CEQ1

R2 RBQ5 (4)

with VCEQl = 0.2 V and RBQ5 = 28 2; RB = 4.198 ko.

In the detailed model, a sweep circuit contain-ing transistor Q3 turns on for about 3 ns and consumespart of the current to Q5. This is simulated by

making REL of QLO low enough during the 'sweep time'to sink some of the base drive. After 3 ns, REL ischanged to a high value and allows all of the currentthrough RB to reach the junction. The Schottky diode

effect is modeled by changing QLO's, MC, ICS, CCB, andTC (calculations are based on two diodes in parallel,QLO's collector diode and the Schottky diode).

When the input goes low, RB is switched to a

high value and transistor QLO is shut off. During thesw!itch. from low to a high output, excess charge in thebase of QLO is swept out by lowering the value of REL.In the high state, transistor QUP is on. QUP is a'PSUEDO' transistor, modeling the action of theDarlington pair in the detailed model (transistors Q2

and Q4. QUP should then have a beta equal to

0NQ2 x SNQ4. The minimum for each transistor in the

detailed model is 30, thus, 0N QUP = 900. An Ebers-

Moll representation for QUP is shown in Figure 4below. Using this model, it is possible to derive MC,HE, ICS, and IES.

With the output high or at least 2.4 V (VOH'minimum), the transistor should be near saturation.In this condition, the sum of the base-emitter voltagedrops (VBE-Q2 + VBEQ4) is 1.18 V. This is VBE(SAT)for QUP. Assuming aI = 0,

IEBE(SAT) I'E x (0-026)Qn I; IEF = IB + IC (5)YES

RB

Figure 4. Ebers-Moll Equivalent of Darlington Pair, QUP

RC = 100 Q (from detailed model); RB =

4170 Q (R2 + RB-Q2)

I and I are derived using the detailed model.B C

V -V - V1 cCC BE(SAT) OUT 5.0 - 1.18 - 2.4

B R2 4 kQ

0.36 mA

vCC vBE(SAT) OUT 1.42IC RC 100 =14.2 mA;

IEF = 14.56 mA

Since there is one equation for VBE(SAT) and two

unknowns (ME and IES), it is necessary to choose areasonable value for ME. The total VBE(SAT) for

the Darlington is VBE-Q2 + VBE-Q4' hence

ME =ME + ME =21, and:Q2 Q4

IEFES Exp [VBE(SAT)/ME*(0.026)1

(6)

(7)

(8)

(9)

Values for CEP and TE are derived by comparing CAAresults to the terminal model (similarly for CCB andTC). It remains to derive MC and ICS. By definition:

vCE(SAT) BE(SAT) BC (SAT)

V = MC(0.026)Zn I; ICFBC(SAT) C (10)

ICaNIB + 1N)IC =

B l+1+

= 0.36 mA+ 14.2 mA - 0.376 mA1+900

From CAA, VCE (SAT) = 0.289.

Once again, choose MC:

MCQUP = MCQ2 + MCQ4 = 2.26

(11)

IaN ICF

REL -

OUTPUT

4336

Then solve for ICS.

ICS- I x Exp _BE(SAT) CE(SAT) 97 ACF C(0.026)

Resistor REL is chosen to insure that transistor QUPstays off when the output of the gate is low.

The next step involves developing a functioncontrolling the switching of the output circuit (Fig-ure 3) by the input monitor, Node 4. Figure 5 illus-trates a simplified flow chart for this function.Table 2 presents the comment cards for the function.Figure 6 illustrates the assembled terminal model ofthe input, output, and function to compose one cell ofthe NAND gate. This cell can then be copied toaccount for N-inputs and M-cell logic chips. Thetechnique is then extended to all the digital DIICs.Table 3 presents the coding for the complete terminalmodel.

Figure 5. Flow Chart for 2 Input NAND GateControl Function

Table 2. SYSCAP II NAND Cell Function Coding

Table 2. SYSCAP II NAND Cell Function Coding (Continued)

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TRACAPFUNCTION FUNCI (RB3,RB4,RL4.LASTL*LASTHtV4.V4P.TEP,TS)REAL8STEP TEICOMMON/FIXCOM/ICONT(100), TE,TEITO

C

C

C THIS FUNCTION IS DESIGNED TO SWITCH THE TWO TRANSISTORS'C 03 AND 04 BETWEEN CUTOFF AND SATURATION, TO SIMULATE THEC ACTUAL FUNCTION OF A DETAILED VERSION OF THIS NAND GATE.C

C VARIABLES INVOLVEDC RB3 AND RB4---BASE BULK RESISTORS FOR TRANSISTORS 03 AND 04C RL4---EMITTER LEAKAGE RESISTANCE FOR 04C LASTL.LASTH---USED TO DETERMINE THE PREVIOUS STATE OF THEC OUTPUT.A VALUE OF 1 FOR LASTH AND 0 FOR LASTLC INDICATES THE OUTPUT WAS PREVIOUSLY HIGHC (SIMILAR BUT REVERSED VALUES FOR LOW)C V4---ACTUAL VALUE OF THE VOLTAGE AT NODE 4C V4P---DELAYED VERSION OF V4(CALCULATED IN THE FIRST BLOCK OF CODEC AND USED BY THE REST OF THE PROGRAM TO DETERMINE OUTPUT)C TEP---TIME AT WHICH LAST VALUE OF V4P WAS CALCULATED'C TS--- INDICATES TIME AT WHICH OUTPUT HAS GONE LOWC (ALONG WITH DELTAT USED TO ENABLE THE FUNCTION TO

C SIMULATE A SWEEPING OF THE BASE CURRENT FOR 04)C TO---DELTA TIME, AS USED IN TRACAPC TE---ELAPSED TIME FOR A PARTICULAR RUNC B---USED TO INDICATE STATE OF INPUTS AS DETERMINED BY V4PC NOTE... .THE VALUE OF FUNCI INDICATES THE FRESENT STATE OFC THE OUTPUT, AS INDICATED BELOWC

C VALUE OF FUNCI OUTPUT---------------------------

C

C -1.0 LOWC 0.0 CHANGINGC 1.0 HIGHC 888888888888888*88888888888

C nPIF(TE.NE.0.0)GO TO 10

TEP a 0.0

V4P a V4C

C INITIAL CONDITIONSC

00 TO 3010 CONTINUE

IF(TE.GT.(TEP + 0.58TO))GO TO 2000 TO 30

20 CONTINUEV4P a (V4 + ((6.25E-10) V4P / TO))/( 1.0 + 6.25E-10/TO)TEP a TE

C

C V4P IS DELAYED FROM V4 BY THE ABOVE CODE(THIS GIVES THEC OUTPUT A SMALL STORAGE TIME IN WHICH NOTHING OCCURS)C

.M) CONTINUEB * V4P - 0.91IF(B.GT.O.O)GO TO 100RB3m4170.0RB4.1 .OE+7RL4n2778.0

CC 03 TURNED ON, 04 TURNED OFF(OUTPUT HIGH)C

IF(LASTH.NE.O)GO TO 50LASTH-1LASTL=O

50 CONTINUEFUNC1-1 .0RETURN

100 CONTINUEIF(B.LT.O.5)GO TO 200RB3a1 .OE+7RB4=4198.0

.CC 03 TURNED OfF, 04 TURNED ON(OUTPUT LOW)C

IF(LASTL,NE.O)GO TO 150TS-TELASTLn1LASTH-0

150 CONTINUEDELTAT-TE-TSRL4-2779.0IF(DELTAT.GT.3.OE-9)RL4-1 .OE+6FUNCl-1.0RETURN

200 CONTINUEB a B* 2.0

CC AS 9 RANGES FROM 0 TO liC RB3 RANGES FROM 4170 TO IOMEG OHMS ANDC R34 RANGES FROM 1OMEG TO 4198 OHMSC

LASTL=ORL4s2778 . 0IF( (LASTH.EG.0) .AND. (TE.NE.O.0))RL4-100.0R83 * 10.0 88 ((3.3799 8 9) + 3.6201)R34 - 10.0 8* (7.0 - (3.377 8 B))FUNCClO.0RETURN

END

Device types that were modeled by this techniqueare shown in Table 1. The equivalent circuit for thecomplex ALU is shown in Figure 7. Figure 8 illus-trates the bit stream output of the ALU for electricalstimulus only. This demonstrates the effectiveness ofthe technique since a detailed model of the ALU wouldbe two orders of magnitude more complex than the ter-minal model.

The modeling technique is also adaptable to theintroduction of rapid anneal by introducing a control(via the FUNCTION) for hFE (¢, T) based on predicteddevice response or device test data.

Table 3. Terminal Model Coding

MOfIEL, 02NT(A1P42,C3,G5,N14)R'i (14,4) 16KD1SI(A4,Cl )8.3,2.1E-12,1.06,3.3MEG,25,lOU,100. 1.8F',0.6,0.5,0.1NP0.54PF'O.lO.lN,ODiS2(A59C1)20,8.8E-13,1.06,1.6E+8, 25,10U,100, 1.04F'P,0.6,0.5,0.lN,0.41P,O.l,O.lN,C

DS3 (A4 ,C2 I) DSi[IS4(A5,C2)DS2D015()A4,C5)638,1.6E--16,1.97,10G,12,OU,l1000.12F9,0.9,0.45,0.3NOPOPO,0O[414(44,C14)70,2.34E-15, 1.13, lOG,t-'5,lOU,10,0.35F',0.75,0.33,0.lU,078F,O.l,81P0.10OPRI (A3,C14)48,95.3 E--15,2.18,0. 1G,?5,lOU, 10,0.8F',0.75,0.33,0.lU,0.34F',0.1,0,0L'R2'(A5,C3)3'I,9.24E-1'5,2.18,0.1G,^S,5lOU,10,1.38F',0.75,0.33,0.1U,0.61F',O.l,O,OriR3(A5vC14)0.75,0.'5U,2.O,O.26,75,0.01,10,0,0.75,0.33,9200N,2OF',O.1,0,003(B14,C14,E3)900,2-M,48,lU,l8P330M,O4170rlOOv0097F',:..6,1E+7,25,lOU, 10,0.13F',0.75,0.33,5N,0.621F',O.1,2OON,O0F',,1 ,1E+56, lOU,100,0. 15F',0.9,0.45,0.3N,0.03F',0.1,0,0

04()14,C3,F i)60,3M,0.85,1U,0.45,30M,3,1E+6,26,1lM1. 1SF', I. 13,1. OE+7, 75,IOU,I 0,?. 3P,0. 75,0. 33, 2N,0. 61F'0. 1,200N,07.68E-16,1.05, 1E+5,6, lOU, 100,0.R8F',0.9,0.45,0.3N,0.060'O.1,0,0A=FUNCI ()3RF,04R14,P4REL,0.0,0.0NOIIF 4,0.0,0.0,0.0)F INI1

Figure 6. Terminal Model for Quad -- 2 InputNAND Gate (Single Gate)

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H-- ----t

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5541

amu

IhS~~~~~~~~~~~~~4os

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5543

ALU (SCD 477-1274)

Figure 7. Terminal Model for the ALU

4338

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4454I0I

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Figure 8. ALU Output Bit Response (Cont)Figure 8. ALU Output Bit Response

CONCLUSION

The technique described in this paper signifi-cantly improves the cost-effective application ofcomputer programs such as SYSCAP II. The terminalmodel offers the designer of radiation hardened elec-tronic circuits a method for evaluating the effects ofradiation transients on single or multiple piece-partresponse at the circuit board level. Although themodels presented in this paper were intended for TREEdesign and analysis, it is possible to extend the tech-nique to EMP or SGEMP evaluations. This can be accom-plished since the input and output portion of themodel retains the "detailed" element characteristicsnecessary to simulate nonlinear frequency-dependentloading and permits calculation of instantaneous pulsepower calculations for burn-out evaluations.

REFERENCES

1. "Modeling and Test Verification for HardenedIntegrated Circuits" C. T. Kleiner, et al,July 1979 IEEE Trans. on Nucl. Sc., Vol. NS-26.

2. "Integrated Circuit Model Development for ENP"C. T. Kleiner, et al, Dec 1974 IEEE Trans. onNucl Sc., Vol NS-21, No. 5, pp 323-331.

3. "SYSCAP II System of Circuit Analysis ProgramsUsers Information Manual". Control Data Corpora-tion Document 76070600, Rev D, pp 4-64 [FUNCTIONOPTION].

For the more complex models (ALU and ROM) severalpages of FORTRAN coding were needed, however, thisreplaces hundreds of nodes and elements that were usedin the detailed CAD model.

The models have been used by more than fiftydesign and hardness engineers as of this writing.

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