The Development and Characterization of Novel Pd/Sn Ohmic...

The Development and Characterization of Novel Pd/Sn Ohmic Contacts to n-type GaAs

Thesis

Submitted to Dublin City University

for the degree of

Doctor of Philosophy (PhD)

by

MD SHAFIQUL ISLAM, B Sc Eng , M Sc Eng

School of Electronic Engineering Dublin City University

Research Supervisor Dr Patrick J McNally

February, 1997

DECLARATION

I hereby certify that this material, which I now submit for assessment on the programme of study leading to the award of Doctor of Philosophy is entirely my own work and has not been taken from the work of others save and to the extent that such work has been cited and acknowledged within the text of my work.

Signed: > Date: A g I f f î .

ACKNOWLEDGEMENTS

I like to express my sincere appreciation to my supervisor Dr Patrick J McNally for his friendly and encouraging guidance for this work He is a man o f in depth knowledge in my research field and I am very grateful for his patience and discussions we shared during this course and also in writing this thesis In real sense, Dr McNally introduced me in the world o f Ohmic contact technology for GaAs devices

I am also indebted to my co-supervisor Dr David C Cameron for his knowledgeable and friendly help in the Edward Vacuum Coating system For his sincere guidance, I was able to familiarize with this system within a couple o f months I appreciate him for his discussions during this work

I am very grateful to my wife Pew, for her constant inspiration, love, sacrifice, patience and understanding particularly during the cource of my research I remain in debt to her I am indebted to my mum who brought me in this beautiful world and cherished me perfectly

I am grateful to my elder brother Mr Rafiqul Alam, for his tireless support and encouragement to build up my career and to do this work I also thank to all other relatives and friends in Bangladesh for their well wishes for my work

I like to thank Professor M S J Hashmi and Professor Charles McCorkell for their encouragement and financial support during my research Thanks to Dr Tony Herbert, Plasma Ireland Ltd , for his co-operation m doing some o f my experiments at the National Microelectronics Research Centre (NMRC), Cork, Ireland Also thanks to Dr Simon Romani for his assistance with SIMS at NMRC I am also grateful to Mr Paul Rozengrave, NMRC, Cork and Mr David John, Central Electron Microscope Unit, Tnmty College, Dublin for their friendly assistance with SEM

I would like to thank John Whelan, Liam Meany, Conor Maguire, Paul Wogan, Peter McGorman and Stephen Neville of Electronic Engineering school for their help and co-operation throughout this work Thanks to Dr John Curley, Microelectronics Res Lab , for his encouragements in my research I am also grateful to Al Devine, School of Physical Sciences, DCU, who helped me a lot in taking photographs o f my equipments and some of the experimental results He also helped me m scanning the photographs for my thesis

Finally, I like to thank all Bangladeshi students here in DCU and relatives m Ireland for their hospitality and encouragements in the last three years.

i

DEDICATION

To my parents and

To my wife

tl

Contents

Acknowledgements i

List of Symbols vii

List of Abbreviations ix

Abstract x

1 Introduction 11.1 Introduction........................................................................................................ 11.2 Ohmic contact formation mechanisms............................................................ 41.3 Recent developments of Ohmic contacts............................................................ 7

1.3.1 Pd/Ge and Ge/Pd metallizations ........................................................... 81.3.2 Pd/Ge/T i/Pt metallizations.....................................................................101.3.3 Pd/AuGe/Ag/Au metallizations............................................................ 101.3.4 Pd/Si metallizations............................................................................... 101.3.5 Pd/In metallizations............................................................................... 121.3.6 AuGe/Ni metallizations......................................................................... 141.3.7 Multilayer Au/Ge/Au/Ni/Au metallizations........................................ 171.3.8 Ni/AuGe/Ag/Au metallizations............................................................ 181.3.9 Au/Ni/NiSn metallizations.....................................................................191.3.10 N ilnW m eta lliza tio n s ........................................................................................ 19

1.3.11 Ni-based non-gold metallizations.........................................................201.3.12 Au-Ge metallizations.............................................................................231.3.13 Au/Te/Au metallizations ............................................................. 241.3.14 High-temperature refractory metallizations.........................................251.3.15 InAs-based metallizations......................................................................27

1.4 Applications of Ohmic contacts to n-GaAs......................................................291.5 Conclusions..........................................................................................................311.6 O rganisation o f this th e s is .............................................................................................32

2 Objectives of this research 34

2.1 Introduction...................................... 34

2 2 Objectives2 3 Characterization of the contacts

3536

3 Optimization of Pd and Sn evaporation rates for better surface

morphology of the Pd/Sn contacts 37

3 1 Introduction 373 2 Experiments 383 3 Results 383 4 Summary 44

4 - Pd/Sn Ohmic contacts to n-GaAs 45

4 1 Introduction 454 2 Conventional TLM (cTLM) method 454 3 Experiments 474 4 Results and discussions 48

4 4 1 Electrical characteristics 484 4 2 Surface profilometry measurements 504 4 3 Surface morphology using SEM 524 4 4 Contact depth profiles using SIMS 544 4 5 Mass spectrometer analysis 604 4 6 Correlation between Ga signal and contact behaviour 624 4 7 Effect of layering sequence 644 4 8 Effects of two-step annealing on the characteristics of

Pd/Sn Ohmic contacts 654 5 Summary 69

5 Effects of Au overlayers on the characteristics o f Pd/Sn Ohmiccontacts to n-GaAs 715 1 Introduction 715 2 Experiments 715 3 Results and discussions 72

5 3 1 Electrical characteristics 725 3 2 Surface profilometry measurements 745 3 3 Surface morphology using SEM 76

5 3 4 Contact depth profiles using SIMS . 795 3 5 Mass spectrometer analysis 81

5 4 Conclusion 84

IV

6 Comparison of Pd/Sn, Pd/Ge, Pd/Sn/Au and alloyed Au-Ge/Ni

Ohmic contacts to n-GaAs 856 1 Introduction 856 2 Experiments 856 3 Results and discussions 86

6 3 1 Electrical characteristics 866 3 2 Surface morphology using SEM 87

6 4 Conclusion 89

7 Thermal and long-term stability of the Pd/Sn and Pd/Sn/Au Ohmic

contacts to n-GaAs 917 1 Introduction 917 2 Experiments 917 3 Results and discussions 92

7 3 1 Thermal stability at 410 °C 927 3 2 Long-term stability at 300 °C 95

7 4 Conclusion 98

8 Fabrication of GaAs MESFETs using Pd/Sn and Pd/Sn/Au

Ohmic contacts 100

8 1 Introduction 1008 2 Experimental procedures 100

8 2 1 Level 1 - Mesa isolation 1008 2 2 Level 2 - Ohmic contacts 1018 2 3 Level 3 - Schottky (Gate) contacts 102

8 3 Results and discussions 1038 3 1 Ohmic contacts 1038 3 2 MESFET characterization 104

8 4 Conclusion 115

9 Conclusions and suggestions for future research 1169 1 Conclusions 1169 2 Suggestions for future research 119

References 120

Appendix A Resistance heating (thermal) evaporator A1

Appendix B Graphite strip annealer B1

V

Appendix D

Appendix E

Appendix C Original STM photographs of the Pd/Sn contacts to GaAs(SI)

Calculation of pinch off voltage

Publications based on this work

List of Symbols

A contact area

Â metallization thickness

d channel depth

Ec conduction band minimum

Ef Fermi level

Ev valence band maximum

E g band gapfE'OO tunneling parameter

S m transconductance

gm(mt) intrinsic transconductance

S m ax maximum transconductanceh Planck’s constant

I g s gate current

I d s dram current

I d s s dram saturation current

J current density

k Boltzmann constant

L separation between the contacts

L c contact length

L t transfer length

L g gate length

L g s gate-to-source distance

L g d gate-to-drain distance*

m electron effective massm Sn to Pd thickness ratioN d donor concentration

q electronic charge

R o contact resistance

R f total resistance

R -sh l sheet resistance o f the active layer under the contact

& sh 2 sheet resistance o f the active layer between the contacts

R P resistance of the interconnect wires

Vll

Ra average surface roughness

Rs series resistance

T temperature

TIR maximum peak-to-valley distance o f the scanned surfaceT1 m melting point

T1 an annealing temperature

V voltage

Vp pinch off voltage

VB built in potential

Vds dram-to-source voltage

Vgs gate-to-source voltage

v F diode forward voltagew contact width

Pc contact resistivity

Apc measurement error

Q resistance

barrier height

S dielectric constant o f the semiconductor

<t>m metal work function

semiconductor work function

V i l i

List of Abbreviations

AES Auger Electron Spectroscopy

CHINT Charge injection transistor

cTLM Conventional transmission line model

DI De-ionized

EDAX Energy Dispersive Analysis o f X-rays

FE Field emission

FEM Field Emission SEM

HEMT High electron mobility transistor

HBT Heterojunction bipolar transistor

I-V current-voltage

LPMOCDV Low pressure organometallic chemical vapor deposition

LED Light emitting diode

MESFET Metal semiconductor field-effect transistor

MQW Multiple quantum-well

MODFET Modulation doped field-effect transistorMOVPE Metal-organic vapor phase epitaxy

NERFET Negative differential resistance field-effect transistor

RTA Rapid thermal annealing

RTP Rapid thermal processing

SEB Scanned electron beamSLS Strained layer superlatticeSD Switching diodeSTM Scanning Tunneling MicroscopySEM Scanning Electron MicroscopySIMS Secondary Ion Mass SpectrometrySI Semi-insulatingSDSR Standard deviation of surface roughness

TE Thermionic emission

TFE Thermionic field emission

TEM Transmission Electron MicroscopyTLM Transmission line model2DEG Two-dimensional electron gasXRD X-ray diffraction

IX

The Development and Characterization of Novel Pd/Sn Ohmic Contacts to n-type GaAs

MD. SHAFIQUL ISLAM

Abstract

A novel Ohmic contact system comprising of Pd/Sn metallizations has been developed for n-GaAs and systematically characterized using Scanning Tunneling Microscopy (STM), Scanning Electron Microscopy (SEM), Surface Profilometry measurements, Secondary Ion Mass Spectrometry (SIMS), Energy Dispersive Analysis of X-rays (EDAX) and current-voltage (I-V) measurements. Contact resistivities, pc, of the proposed metallizations are measured utilizing a conventional Transmission Line Model (cTLM) method. The Pd/Sn metallizations show lowest pc

5 2 18 3in the range of low 10' Q-cm on Si-doped (2x10 c m ') n-GaAs. A Au overlayerimproves the characteristics of the Pd/Sn Ohmic contacts. The Pd/Sn/Au contacts

6 2display lowest pc in the range of low 10' Q-cm . The Pd/Sn and Pd/Sn/Au Ohmic contacts are very adhesive to the substrates. Both Pd/Sn and Pd/Sn/Au contacts exhibit improved characteristics when compared with alloyed Au/Ge/Au/Ni/Au contacts.

The Pd/Sn and Pd/Sn/Au metallizations show better thermal stability at 410 °C than non-alloyed Pd/Ge contacts. The Pd/Sn/Au metallizations also display better thermal stability than alloyed eutectic Au-Ge/Ni and Ni/Au-Ge/Ni contacts. However, at this temperature thermal stability of the Pd/Sn/Au metallizations is comparable to that of alloyed Au/Ge/Au/Ni/Au contacts. Long-term stability of the Pd/Sn/Au metallizations at 300 °C is comparable to non-alloyed Pd/Ge contacts. No change in surface morphology is observed after having been annealed at 300 °C for 400 h. At 300 °C, the Pd/Sn/Au metallization exhibits pc which is slightly higher than those of the alloyed Au-Ge/Ni, Ni/Au-Ge/Ni and Au/Ge/Au/Ni/Au contacts.

GaAs Metal Semiconductor Field-Effect Transistors (GaAs MESFETs) have been fabricated using Pd/Sn and Pd/Sn/Au metallizations as source/drain contacts. MESFETs fabricated with Pd/Sn/Au Ohmic contacts display improved characteristics when compared to Pd/Sn contacts. MESFETs fabricated with Pd/Sn/Au contacts show comparable edge uniformity to non-alloyed Pd/Ge metallizations which is very important for VLSI GaAs devices. The newly developed, thermally stable, Pd/Sn and Pd/Sn/Au metallizations appear to be promising candidates for future GaAs device technology.

CHAPTER 1

Introduction

1.1 Introduction

The purpose of an Ohmic contact to a semiconductor is to allow electrical current to flow into or out o f the semiconductor The contact should have a linear I-V

characteristic, be stable over time and temperature, and contribute as little resistance as

possible Simply placing a metal in contact with a wide bandgap III-V compound

semiconductor, such as GaAs generally results in a rectifying contact (a diode) rather

than an Ohmic one Therefore, achieving a stable, low-resistance Ohmic contact has been as much technical art as science, and this problem generated a large amount of

research over several decades

Recent remarkable progress in semiconductor technology has made it possible

to fabricate high performance GaAs devices [1] Although many useful contact schemes

have been developed, further improvements in contact resistance are still necessary in

order to keep pace with developments in the novel device design The primary

requirements o f Ohmic contacts are a low contact resistivity, an insignificant contact

metal diffusion into the semiconductor both laterally and vertically, reproducibility, thermal stability and reliability

Advances in ultra-fast electronics and optoelectronics have considerably

accelerated demand for GaAs devices in recent years This has been achieved through

an improvement in GaAs device fabrication and processing techniques, new device structures and new circuit designs The need for a reliable and well-controlled Ohmic

contact is central to the successful operation of almost all GaAs devices Achieving a low resistance Ohmic contact to GaAs is not trivial, and requiring in addition that the

contact be thermally stable during subsequent processing at temperatures up to 400 °C

(about 800 °C if the contact is to be used as a mask for dopant implants),

morphologically uniform on the 0 1 jam scale and compatible with conventional

lithographic patterning techniques, presents a formidable challenge Yet the

development o f low resistance contacts that meet these requirements is necessary for

further miniaturization o f devices such as the GaAs metal-semiconductor field-effect

transistor (MESFET) shown in Fig 1 1 In this device, lateral encroachment o f the

1

source and drain Ohmic contacts towards gate contact can occur during the contact

annealing treatment, thereby limiting the minimum gate-to-source and gate-to-drain

separation

source contact gate contact \

n

dram contact

n n

GaAs(SI)|«-<1 înu)

Fig 1 1 Schematic diagram of sub-nm GaAs-MESFET illustrating the demands on contact metallizations [2]

In the MESFET, the source and dram resistances are key parameters that determine its performance The source resistance strongly affects the device

transconductance and noise figure An increase in both source and dram resistances

tends to increase the power consumption and slow down device operation Low contact

resistivity is also required in efficient optoelectronic devices both from the point of

view of power consumption and heat dissipation

source contact + _n -GaAs

V

dram contact \

u-AlGaAs ~200 nmX -----2DEG in u-GaAs

n -GaAs substrate n-AlGaAs

'¿ ¿ /////7 7 .& -------------------------

backside contact

Fig 1 2 Schematic diagram of the NERFET illustrating the demands on contact metallizations [3]

The scaling o f GaAs devices to submicrometre dimensions imposes more

stringent requirements on the electrical and metallurgical characteristics o f Ohmic

contacts The morphological constrains on low resistance contacts are even more severe

for heterojunction devices in which the current is confined in the form of a two-

dimensional electron gas (2DEG) at the buried interface (e g GaAs-Al,.xGaxAs) For

example, the source and dram contacts in the negative differential resistance field-effect

transistor (NERFET) [3] (Fig 1 2) must make contact with the buried 2DEG without

2

penetrating the thin (about 200 nm) A l|.xGaxAs barrier layer Even a localized

penetration will introduce a path for excessive leakage current and render the device

inoperable

Smaller intrinsic resistances make the problem of low contact resistivity more

acute For Gunn diodes and LEDs, contact resistivity, pc = 10'3-10'5 Q-cm2 has been

adequate since the Ohmic contacts employed in these devices are realtively large in area

and the resulting contact resistivity can easily be smaller than a few Ohms For

MESFETs with 1 jxm gate, a pc of mid 10-6 Q-cm2 may suffice, but for sub-|am

devices, where the semiconductor channel resistance is lower by more than a factor of

two, the pc should be reduced to low 1 O’6 Q-cm2

From the point of view o f metallurgical characteristics, requirements for fine

pattern capability and precise control of the penetration depth of the Ohmic contact

have become crucial Modem device designs require contacts with morphological

uniformity such that lateral depth definition and depth o f penetration of the

metallization can be controlled to within tens of nanometres Fine pattern capability is

necessary for minimizing gate-to-source spacing in all types o f field-effect transistors

To realize the high dc current gam, high speed and high microwave cut-off frequency

capabilities o f thin base heterojunction bipolar transistors (HBTs), vertical scaling of

the Ohmic contact is necessary to avoid contact penetration into the adjacent active

region o f the HBT In the case of a high electron mobility transistor (HEMT), a rigid

control is required on the vertical scaling of source and dram contacts providing an

Ohmic contact directly to the 2DEG channel [1]

It is clear therefore that with ongoing miniaturization and integration of GaAs

devices, the ever-increasing demand for high performance Ohmic contacts is one o f the more challenging problems m GaAs IC technology Many reports describing Ohmic

contacts to GaAs already exist in literature, including a number of reviews The reviews

by Rideout [4], Popovic [5] and Piotrowska [6] present a theoretical treatment as well as a summary of research activities prior to 1983 Shen et al [7] very concisely treated a number o f basic issues related to Ohmic contacts on GaAs The role o f mterfacial

reactions in Ohmic contact formation is described by Piotrowska [8] and Sands [2]

Additionally, information regarding Ohmic contacts can also be found in a number of reference books [9-12]

The remainder o f this chapter is concerned with a brief discussion of Ohmic

contact formation mechanisms This will be followed by a detailed review o f recent and

important research activities related to Ohmic metallizations for n-GaAs Different

3

Ohmic contact schemes will also be summarized for various GaAs device applications

The relative advantages and disadvantages o f each contact scheme will be pointed out

Finally, the organisation of this thesis will be presented

1.2 Ohmic Contact Formation Mechanisms

An Ohmic contact is defined as a metal-semiconductor (M-S) contact that has a linear

current-voltage (I-V) characteristics and also has a negligible contact resistance relative

to the bulk or spreading resistance o f the semiconductor A satisfactory Ohmic contact

should not significantly perturb device performance and it can supply the required

current with a voltage drop that is sufficiently small compared with the drop across the

active region of the device If R c is the contact resistance and A is the contact area then

the contact resistivity pc is given by the product o f R c and A When evaluated at zero

bias, this pc is an important figure of merit for Ohmic contacts A formal definition of pc

is usually given as

Fig 1 3 Ohmic contact formation mechanisms (a) TE, (b) FE and (c) TFE The conduction band minimum, Fermi level and valence band maximum are indicated by Ec, Ef and Ev, respectively

Basically, there are three mechanisms [9] which govern the current flow in a M-S

contact These mechanisms are described below very concisely

• Thermionic emission (TE): dominant in moderately doped semiconductors,

Ad<(~1017 cm-3) In this case, the width of depletion region is relatively wide,

implying that the probability of electrons tunneling through the barrier is rather

small If the barrier height (<j)B) is small, the electrons can easily surmount the top of

the low barrier by thermionic emission (Fig 1 3(a)) For low doped or high-bamer

(1 1)

2where J=current density (ampere/cm ) and F=applied voltage across the contact (volts)

EcEf

Ev VEcEf

(a) (b) (c)

4

semiconductors, the vast majority o f electrons are unable to overcome this barrier in

either direction and result in non-Ohmic (rectifying) contacts• Field emission (FE): effective in heavily doped semiconductors, jVD>(~1018 cm'3)

For this situation, the depletion region is so narrow that electrons can easily tunnel

through the barrier and tunneling is the dominant transport mechanism (Fig 1 3(b))

• Thermionic-field emission (TFE): applicable for intermediately doped

semiconductors, (~1017 cnr3)<iVD<(1018 cnr3) Both thermionic and tunneling are

significant as shown m Fig 1 3(c)

For each o f these three mechanisms, the contact resistivity pc can be calculated with the

help of a very useful parameter k T / E 00 introduced by Yu [13], where

E471 \

N d- 4 (12)e m

E 00 is the tunneling parameter, q is the electronic charge, h is the Planck's constant, N d

is the donor concentration, s is the dielectric constant o f the semiconductor, and m * is

the electron effective mass

For k T / E og» \ , l e for moderate N D , the TE mechanism dominates the current

conduction and the contact resistivity is given by

P c °C e X p ~ife7 r ( 1 3 )

From eqn (1 3), it is clear that the contact resistivity is dependent on temperature At

higher temperatures, the thermionic emission current increases resulting m a smaller pcFor k T / E oo~ 1, î e for intermediate N D , a mixure of both thermionic and tunneling

mechanisms (TFE) is observed and the contact resistivity is

B /-1 ,« \

Pc « exP ------------- r (I 4)

e ~ c o A T F

It is seen that the contact resistivity depends on both the temperature and the transmission coefficient for tunneling

For k T / E 00« l , i.e for heavy doping concentrations, contact resistivity becomes

r t n n «p ^ e x p — (15)

5

In this case, pc depends strongly on doping concentration and the field emission (FE) mechanism prevails As the doping concentration is increased further, the depletion width of the Schottky junction decreases resulting in an increase of the tunneling transmission coefficient Hence, even a metal with a high barrier to the semiconductor can form an Ohmic contact

If a large number of surface states exists in the semiconductor, the Fermi level is pinned and the barrier height is independent of the metal work function This is the Bardeen limit [14] which stands in contrast to the Schottky limit where the metal - semiconductor contact is assumed ideal and the surface states are ignored In practice, the surface Fermi levels of most III-V compound semiconductors are pinned

somewhere in the gap, which is what determines the barrier height It can then be concluded that the barrier height depends not only on the gap of the semiconductor, but also on the surface state density

Three mam approaches have been used to obtain low pc Ohmic contacts on n-GaAs These three approaches are described below very briefly• Contacts to very small band gap semiconductors: When a metal is brought into

contact with a semiconductor, the Fermi levels in the metal and semiconductor must align under equilibrium conditions (Fig 1 4(a)) If the work function of the metal (<|)m) is smaller than the work function of the semiconductor (<)>s), the Fermi levels are aligned by transferring electrons from the metal to the semiconductor This raises the semiconductor electron energy relative to the energy of electrons in the metal at equilibrium The Fermi level is pinned in the conduction band of the small band gap material, for example InAs (Eg~0 36 eV) (Fig 1 4(b)), therefore, the junction has a very small pc, in the range of 10'7-10-8 Q-cm2 (TE mechanism) [15]

• Contacts in the case of low barrier height and heavily doped semiconductors: This approach is also successful for attaining low pc (TFE mechanism) For example, contacts made on n+-InGaAs (Eg~0 75 eV)/GaAs exhibit a contact resistivity in the range of 1 O'6-10s Q-cm2 (Fig 1 4(c)) [16,17]

• Contacts in the case of heavily doped semiconductors: The heavier the doping at the semiconductor surface, the thinner the barrier width, and earners can tunnel more easily between the metal and the semiconductor (FE mechanism) (Fig 1 4(d)) Contacts made on GaAs (Eg~l 42 eV) with a surface doping of 1018-1020 cm '3 fall into this category Contact resistivities in the range of 10"5-10‘7 Q-cm2 are generally obtained [18-21]

In particular, the contact resistivity depends greatly on the doping level in the semiconductor, the bamer height of the metal-semiconductor combination, carrier effective mass, dielectric constant and temperature

6

In practice, the most widely used Ohmic contacts to GaAs today involve

multicomponent metallization systems prepared by conventional deposition and

annealing techniques Heat treatment is used to drive a suitable dopant from the

metallization into the GaAs surface region to form a tunneling junction and/or to

fabricate, in contact reaction, a suitable heteroj unction with low effective barrier height

layer ia y e r (0 8<x<i 0)

(c) (d)Fig 1 4 Schematic diagrams of band bending for various metal/semiconductor interfaces The conduction band minimum, Fermi level and valence band maximum are indicated by Ec, EF and Ev, respectively(a) The typical band line-up for metals deposited on air exposed n-GaAs {100} Under

bias, electrons are transported by thermionic emission over the ~0 8 eV energy barrier [2]

(b) Band diagram for metal/n-InAs/n-GaAs [7](c) Band diagram for metal/n+-InxGai_xAs (0 8<x<l 0)/n-GaAs [17](d) Band diagram for metal/n+-GaAs (heavily doped) [2]

1.3 Recent Developments of Ohmic Contacts

The most important areas o f recent investigations into Ohmic contacts to n-GaAs are

those involving the use of rapid thermal annealing (RTA) or rapid thermal processing

(RTP), scanned electron beam (SEB) annealing, electroless deposition of metals, the 8-

doped epilayer technique, development o f refractory metallizations and the application

of heavily doped and/ or small band gap materials [17, 18, 22-28] Metallizations

containing dopant elements, such as Si, Ge and Sn for n-GaAs are preferred in order to

7

form heavily doped surface layers that are essential for low pc contacts [19, 20, 29, 30]

At high temperatures, out-diffiision of GaAs constituents occur Therefore, it is

necessary to incorporate a barrier layer to reduce this outdiffiision A variety of

materials have been used as barrier layers refractory metals (platinum, palladium,

chromium, molybdenum, tungsten, e tc ) and related alloys (TiW, MoW, e tc), and

above all, low resistivity compounds (borides, nitrides, silicides, e tc ) [27, 31-35]

1.3.1 Pd/Ge and Ge/Pd metallizations

The Pd/Ge metallization scheme can provide Ohmic contacts with a low pc similar to

that obtained in AuGeNi contact systems Furnace annealing at 325 °C for 30 min is

usually used to form Pd/Ge Ohmic contacts [18] However, it is often desirable to use

an annealing process with shorter duration The Ohmic contact formation mechanism

for the non-alloyed Pd/Ge or Ge/Pd contact can be explained by a solid-phase regrowth

mechanism [19,36] The regrowth process begins with a limited low-temperature (-100

°C) reaction between the Pd and GaAs substrate to produce an intermediate Pd4GaAs

phase (Figs 1 5(a) and 1 5(b)) A subsequent reaction at a high temperature (-300 °C)

between the Ge overlayer and the intermediate Pd4GaAs phase results m the

decomposition of the Pd4GaAs phase and the epitaxial regrowth of a Ge-doped n+-GaAs

surface layer (Fig 1 5(c)) The excess Ge is then transported across the PdGe layer and

epitaxially grows on the GaAs substrate (Fig 1 5(d))

I

Ge

Pd

GaAsJ

40 0 °C

GePd

Pd4GaAsGaAs J

-300 °CGe PdGePdGe Ge

n+ -GaAs(Ge)— ►n+ -GaAs(Ge)

J(a) (b) (c) (d)

Fig 1 5 Shematic diagram of the regrowth mechanism using the Pd/Ge system [20]

Since Ge creates an n+ doping on the GaAs surface upon annealing and Pd can

decompose Ga and As oxides, Pd/Ge or Ge/Pd metallization systems have been

extensively investigated on n-GaAs as possible Ohmic contacts [18, 20, 22, 31, 32, 37-

49] There are additional but less notable advantages such as a lower barrier height for

Ge/GaAs heterojunctions (-0 5 eV), compared to Pd/n-GaAs junctions where the Fermi

level is generally pinned at -0 8 eV In general, research has concluded that for a

doping level m the low 1018 cm-3 range and a heat treatment o f 325-375 °C up to 30

mm, a solid-phase reaction takes place producing contacts with pc~10"6 Q-cm2 RTA or

8

R TP was reported to form good Ge/Pd and Pd/Ge contacts, having better surface morphology, better edge defin ition , low er pc, high re lia b ility fo r aging and exhibiting a shallow (non-spiking) nature [22, 37, 38].

Since Ge and Pd form compounds at low temperatures, the Pd/Ge or Ge/Pd contacts also exhib it pc~10'6 Q-cm2 fo r doping concentrations o f ~1018 cm '3 [18, 40, 41, 44, 50]. The addition o f a A u overlayer reduces sheet resistance o f the m etallization and facilitates A u w ire bonding [51], An optimum Ge/Pd m etallization thickness w ith excess Ge (Pd~500A, Ge~1265A) can result in better pc [18]. The same author found an increase in pc, about one order o f magnitude when the contacts were treated at 400 °C fo r 5 h. Scanned electron beam (SEB) annealing contacts [23, 52] gave better results than those o f furnace annealing.

A number o f fabrication techniques have been reported fo r im proving the therm al stab ility o f Ohmic contacts to GaAs. These approaches invariab ly depend on the use o f a suitable A u d iffusion barrier such as T iN [33], T iW [27], W S i [34], W N [35] and Pd [23]. Thermal stab ility and long-term stab ility o f Pd/Ge Ohmic contacts have been studied by many authors [23, 31, 32, 38, 44, 51]. T i/P t/A u [31, 32], W N /A u [31], T i/P d /A u [53] and T i/A u [21] overlayers im prove the therm al stab ility o f the Pd/Ge m etallization. The Ge/Pd contact [44] was found to be stable at 300 °C fo r at least 50 h. A n in terd iffusion degradation model o f this contact [44] was also proposed. Long-term stab ility was investigated by annealing the Pd/Ge/Au and Ge/Pd/Au contacts at 180 °C fo r 280 h [51], No change in contact resistance or surface morphology was observed. The SEB annealed Au/Pd/Ge Ohmic contact exhibited good therm al stab ility after 25 h o f aging at 500 °C [23]. Tsuchimoto et al. [38] investigated the long-term stab ility o f Pd/Ge contacts and observed an increase in pc from lx l0 '5 to 1.2x10 '5 Q - cm2 at 300 °C after 1000 h. Th is degradation is equivalent to a 10% deterioration in 109 years at 70 °C. Another model fo r the aforementioned degradation was also proposed[42].

The presence o f N i in Au/Pd/Ge contacts results in a reduction in the pc and good surface m orphology [23, 52], Th is is because N i by its e lf form s some N i-G e interm etallics and is known to enhance Ge d iffusion into GaAs [54]. In addition, N i prevents any interaction between Pd and Ge thereby enabling the Pd layer to effectively act as a A u d iffusion barrier. The effectiveness o f polyim ide and r f sputtered S i0 2 passivation layers on the stab ility o f a Au/Pd/N i/G e Ohmic contact [52] shows that both types o f passivation provide good thermal stab ility. The operating life o f th is Ohmic contact fo r an eightfold increase in pc is in excess o f 100 000 h at room temperature

9

(300 K ) High-temperature (800-900 °C) R T A is used to form G e/Pd/W /Au Ohmic contacts [55] w hich are compatible w ith ion im plantation activation processes

1.3.2 Pd/Ge/Ti/Pt metallizations

Pd/G e/Ti/P t appears to be an excellent candidate as an Ohmic contact fo r both n- and7 2p-GaAs [56, 57] Contact resistiv ities m the range o f m id 10" Q-cm are obtained fo r

both n- and p-GaAs using R T A The T i was added to the Pd/Ge contact p rim arily to promote the adhesion o f the P t to the contact and act as a d iffus ion barrier fo r the Pt The P t layer was protected from the Pd and Ge layers so that it would not participate in the contact form ing reactions and would therefore retain its smooth morphology Therm al stab ility o f the contacts has also been studied [56, 57] The contact is stable at 300 °C fo r 20 h, but at 400 °C it is stable fo r on ly about 35 s

1.3.3 Pd/AuGe/Ag/Au metallizations

Shallow Ohmic contacts have been developed using Pd/AuG e/Ag/Au m etallizations [58,59] The structure offers low res is tiv ity (pc~ 2 x l0 '6 Q-cm2) Ohmic contacts w ith good adherence to the substrate in the temperature range from 400 to 500 °C The lim ited m etal-GaAs reaction and the un iform interface m orphology make the structure very attractive in large-scale integrated circuits The same m etalliza tion can be used fo r A lxGa,.xAs [58] which is very im portant fo r ligh t-em itting diodes, laser diodes and other heterostructures

1.3.4 Pd/Si metallizations

This m etalliza tion system is in many ways sim ila r to Pd/Ge, including a lo w p c~10‘ 6 Q-cm2 fo r s im ila r doping levels i f the Si/Pd ra tio is equal to or greater than 0 65 [19] The Ohmic contact form ation mechanism is described by many authors [2,7,8,19,40,44] The regrowth mechanism can be b rie fly summarized as shown in F ig 1 6 W ith a layer structure o f Si/Pd/GaAs (F ig 1 6(a)), the regrowth mechanism begins w ith a low-temperature (-100 °C) reaction between a Pd layer and GaAs to form a stable PdxGaAs (x~4) ternary compound (F ig 1 6(b)) The reaction

xPd + GaAs —» P dxGaAs (1 6)

starts at the Pd/GaAs interface and at higher temperatures (about 200-275 °C) the reaction

Si + 2 P d -» P d2Si (1 7 )

10

starts at the Si/Pd interface (F ig 1 6(c)) Since PdxGaAs and Pd2S i have almost identical crystal structures, the ternary compound is loaded w ith S i v ia d iffus ion o f S i atoms (F ig 1 6(d)) W hen PdxGaAs and Pd2Si meet, the therm al stab ility o f Pd2S i then drives the reaction

2S i + P d 4 G a A s —» 2 P d 2 S i + G a A s (18)

to the righ t in the presence o f excess S i at the subsequent higher temperatures (>300 °C) Th is reaction results m the epitaxial regrowth o f a th in GaAs layer as a product o f the above reaction on the GaAs substrate [36] During the regrowth process, S i atoms incorporated in the Pd4GaAs layer are carried along in to the GaAs lattice in th is process In th is manner, the regrowth layer is doped w ith S i atoms Equation (1 8), thus, is m odified to be

2S i + P d f i a A s ( S i ) -* 2 P d , S i + G a A s ( S i ) (1 9)

where Pd4G aAs(Si) and G aAs(Si) signify the doping o f S i in these layers (F ig 1 6(e)) The thickness o f th is regrown layer is about 100A In order fo r th is regrown layer to be strongly n-type (> 2 x l0 19 cm-3), S i atoms must p referentia lly occupy Ga vacant sites

100°C 200°C -2 7 5 °C 20 00C ~275°C 300°C ~ 400°CSi Si Si Si SiPd Pd Pd7Si

Pd Pd2 Si P d jS iPd.GaAs4 1 ---^ Pd4GaAs 1 Pd4GaAs(Si' -----►if-G aA s(S i)

; GaAs ; 2 GaAs ; ; GaAs ; - GaAs : 2 GaAs ' ;(a) (b) (c) (d) (e)

Fig 1 6 Schematic diagram o f the regrowth mechanism using the Pd/Si system [40]

In terms o f this regrowth mechanism, the significance o f excess Si is evident S ignificant interaction between Pd2Si and GaAs was observed at temperatures above 400 °C fo r the samples w ithout excess S i [60] However, the presence o f excess Si tends to drive eqn (1 9) to the righ t hand side, thus leading to Ohmic behaviour as w e ll as form ing a stable contact by preventing the Pd2Si layer from reacting w ith GaAs The m ajor difference between the Si/Pd/GaAs and Ge/Pd/GaAs systems is that epitaxial Ge is in contact w ith GaAs m the Ge/Pd/GaAs system, whereas Pd2S i is m contact w ith GaAs in the Si/Pd/GaAs system However, both systems can result in Ohmic contact behaviour on n-GaAs w ith pc in the range o f 10'6 Q-cm2 on lx lO 18 cm '3 n-GaAs From

11

th is fact, it is clear that the epitaxial Ge (o r a possible low barrier height at the Ge-GaAs heterojunction) is not essential fo r the Ohmic behaviour, but it may be responsible fo r reducing the contact resistance

The Pd/Si contact is stable at 300 °C fo r at least 50 h [44] The fin a l layer sequence o f Si/Pd/GaAs system is Si/Pd2Si/GaAs The therm al stab ility o f this system is related to the stab ility o f the Pd2Si/GaAs interface The importance o f excess S i in the Pd/Si m etallization is also reported [44] Excess S i is needed to form the n+ layer fo r the contact to become Ohmic Excess S i also stabilizes the Pd2Si/GaAs interface The excess Si may also stop the Ga and As ou t-d iffusion because S i has been shown to be a good annealing cap fo r implanted GaAs [61]

1.3.5 Pd/ln metallizations

The mam m otivation fo r considering In-based m etallization is the resultant form ation o f the sm all band gap m aterial InGaAs on GaAs which can improve pc However, the reaction between In and GaAs w ithout surface oxides starts above the m elting point o f In (156 °C), hence, form ation o f the liqu id phase and possible oxides may lead to poor interface and surface morphologies Palladium form s several refractory compounds w ith Ind ium , such as InPd, In 3Pd, and In 3Pd2, whose m elting points lie between 700 °C and 1300 °C [62,63] Thus the thermal stab ility and m orphology o f Pd /ln m etallizations are improved M oreover, palladium deposited on GaAs increases the out-d iffusion o f gallium when heated, which facilitates the in -d iffus ion o f doping species like Zn or Ge The same behaviour is expected fo r indium [47,63,64]

Ohmic contacts to n-GaAs based on Pd/ln m etallizations are reported by many authors [50, 65-69] The Ohmic contact form ation mechanism o f Pd /ln m etallization starts at low temperatute (-10 0 °C) A t th is temperature, a lim ited reaction occurs between Pd and GaAs to form Pd4GaAs and between Pd and In to form Pdln3 During subsequent exposure to high temperatures (>550 °C), the high m elting point phase, Pdln, nucleates The reaction continues at higher temperatures to form Pdln resulting in the extraction o f Pd from the m terfacial layer o f Pd4GaAs and the regrowth o f InxGa,.xAs The sequence o f solid-phase reactions are as fo llow s

APd + GaAs -> Pd^GaAs (1 10)

(-10 0 °C, at the Pd/GaAs interface) and

3 In+ Pd —> Pdln3 (1 11)

12

(-10 0 °C, at the Pd/In interface).A t higher temperatures (>300 °C)

Pdln3 + Pd^GaAs -» P dln+ InxG a]_x As. (1-12)

(The In fraction x is significantly greater than 0 on ly above -5 5 0 °C). Equation (1.12) is not balanced since the exact stoichiom etry o f the ternary compound Pd4GaAs and the growth Ii^G aÂs layers are not known, although x is estimated to be -0 .4 fo r temperatures above 550 °C.

The effect o f a th in Ge layer (2 nm) on Pd in Pd/In Ohmic contacts was investigated by Wang et al. [65], Both contacts w ith and w ithout Ge are stable in the low 10'6 Q-cm2 range at 400 °C fo r 48 h. Since the localized oxides p rio r to In deposition represent a problem, the use o f a Pd, N i, or P t th in film to reduce the oxides has met w ith good results [66,67]. Form ation o f sm all band gap InAs on the GaAs was found in one In /P t contact study [67]. A thermal study o f the Pd/In contact [66] was carried out and the contact was seem to be re la tive ly stable during anneals at 400 °C. A unique electroless method [63] which co-deposits A u-Pd-In and Pd-In onto an n-GaAs substrate has also lead to Ohmic contacts w ith pc~ 6 x l0 '6 Q-cm2 in th is case on ly fo r Pd-In after annealing at 470 °C fo r 2 m in. A pc o f the order o f -1 0 '6 Q-cm2 was obtained using both SEB and R T A processed Pd/In Ohmic contacts [68] w ith SEB annealed contacts exhib iting a superior surface m orphology and therm al stab ility.

Fig. 1.7.Schematic diagram o f alloying sequence o f Pd/In m etalliza tion to n-GaAs [70].

V e ry recently, M a et al. [70] presented a growth mechanism fo r Pd/In contacts as depicted in Fig. 1.7. Below 400 °C, it is proposed that In firs t reacts w ith Pd, developing a stable In3Pd compound on the GaAs layer. Th is reaction continues un til the Pd is entire ly consumed. A t 400 °C, solid-state d iffus ion occurs as excess In diffuses through the In 3Pd, form ing a low resistive InxGa,.xAs compound w ith GaAs. The

13

Ir^GaÂs compound is believed to form an abrupt heterojunction w ith GaAs which restricts carrier transport more than the m etal-InxGa,.xAs barrier and hence reduces the pc values. Wang et al. [69] investigated Pd-In-Ge non-spiking Ohmic contacts to n-GaAs (1018 cm*3). They observed that a layered structure o f Pd/In/Pd/n-GaAs w ith 10-20A o f Ge embedded in the Pd layer adjacent to the GaAs can lead to a hybrid contact. W hen the Ohmic form ation temperature was above 550 °C, a layer o f In^GaÂs doped w ith Ge was formed between the GaAs structure and the m etallization. When the annealing temperature was below 550 °C, a regrown layer o f GaAs doped w ith Ge was formed at the Pdln/GaAs interface, g iving rise to an n+ surface layer and a tunneling junction as shown in Fig. 1.8. The pc o f (2-3)xl0~7 Q-cm2 fo r th is contact structure is nearly independent o f the contact area from 900 to 0.2 (am2. This contact has been shown to be therm ally stable up to a temperature as high as 600 °C.

(-10 0 °C)Pd PdIn Pdln,

Pd 4 Ge (10-20Ä) Pd4GaAs(Ge)

j n-GaAs : - n-GaAs i

Low Temp. (<550°C)

H igh Temp. (>550°C)

Pdln

IiixG a^ A s(x -0 .4 ) : : n-GaAs ;

Fig. 1.8. Schematic diagram showing the solid-phase reaction o f the Pd/In/Pd(Ge) contact [69].

1.3.6 AuGe/Ni metallizations

Among Ni-based m etallizations, eutectic AuG e/N i is the most common contact m aterial fo r n-GaAs [52, 71-80]. In th is contact system, Ge serves to increase the surface doping, w hile N i form s a barrier and a conductive N iA s compound. Two-stage annealing techniques can improve the overall performance o f AuGeNi-based Ohmic contacts [71]. A pre-anneal can remove the inhomogeneity o f the m etal/GaAs interface [71]. M elting has been attributed to the p-AuGa phase m odified by the other elements present. The addition o f a T i/A u cap also improves the topography o f the annealed m etallization but

14

contact resistiv ities are poorer [71]. RTP (R T A ) is also a popular means to improve Au- based contacts [78-80], A uG e/N i non-alloyed Ohmic contacts have been formed on heavily doped n-GaAs layers activated by SiO xN y-capped infrared rapid thermal annealing (R T A ) [78]. A further reduction in pc has been accomplished by low - temperature (300 °C) alloying w ithout m elting the AuGe eutectic. Both conventional annealed and R T A AuG e/N i contacts [80] have identical pc values, but the interface reacted layer was w ider fo r the firs t process.

Scanned electron beams (SEBs) have also been used fo r the alloying o f AuG e/N i m etallization [52,77]. Capped alloyed A uG e/N i contacts were found to have a higher resistance to degradation than uncapped alloyed A uG e/N i contacts [52]. Capped AuG e/N i contacts also exhibited longer operating life than uncapped contact structures fo r tw ofo ld , fourfo ld and eightfold increases in the ir pc values. Cohen et al. [77] fabricated AuG e/N i Ohmic contacts u tiliz in g furnace and SEB annealing techniques. They observed that SEB-alloyed contacts exhibited less red istribution o f contact constituents compared w ith furnace-alloyed contacts.

The importance o f N i to Ge ratio and o f annealing cycle fo r the resistiv ity and morphology o f AuG eN i Ohmic contacts to n-GaAs was investigated by Procop et al. [73]. The morphology o f the contact layer at the m inim um pc was determined by the selected annealing cycle and by the N i to Ge ratio. G oronkin et al. [72] used N i/G e/A u Ohmic contacts on GaAs and GaAs/AlGaAs. They did not observe any m elting and lateral encroachment o f the Ohmic metals alloyed at 460 °C. The use o f N i/G e/A u Ohmic contacts on GaAs/AlG aAs w ith 460 °C, 8 m in a lloying cycles produced low - resistance contacts, no lateral encroachment, and sharp edge acuity. The AuG e/N i contacts to n-GaAs [74] have m ixed structure, composed o f about 84% o f n n-contact and about 16% o f the Schottky contact. The results obtained w ith AuG e/N i and N i/A uG e/N i Ohmic contacts [75] indicate that the incorporation o f Ge into GaAs occurs v ia solid-state d iffusion and Ge d istribution w ith in the m etallization layer d iffers in the two systems.

The effect o f N i as a firs t layer in the AuG eNi Ohmic contact was also reported [81]. The un ifo rm ity o f the interface structure was greatly improved by the deposition o f a 5 nm -thick N i firs t layer due to its effects on kinetics o f the a lloying reaction (F ig . 1.9). Fo r sample A (w ithout an in itia l N i layer) N i3Ge is formed between AuGe and A u at temperatures below 420 °C. When the annealing temperature is higher than 440 °C, a reaction between A u and GaAs is in itiated , fo llow ed by the d iffusion o f N i3Ge or the remaining N i to the GaAs interface and the form ation o f a protruded N iA s(G e) phase. The top layer is binary Au-Ga consisting o f (3-AuGa and P '-A uG a

15

phases w ith m elting points o f 375 °C and 347 °C, respectively The interface in this particular sample is nonplanar B y contrast, in sample B (w ith an in itia l N i firs t layer), the firs t layer N i reacts w ith GaAs and form s N i2GaAs or N i3GaAs compounds at -200 °C Above 400 °C, N iG a and N iA s develop A n in itia l N i layer clearly optim izes the alloying kinetics A llo y in g at a higher temperature, such as 600 °C, causes N iAs(G e) grams to grow, resulting in d ilu tion o f Ge in the grams w hich then causes an increase in pc The effect o f the AuGe thickness in th is m eta lliza tion was also reported to have an impact on pc [82] The same m etallization has been u tilized to find out the effect o f A lA s m ole fraction (x ) on A lxGa,_xAs [43]

Before a lloying During heating (below 420 °C)

A fte r a lloying at 440 °C fo r 2 mm

A uSample A

(w ithou t N i firs t layer)

N iAu-Ge

GaAs

Au(G a)N ijG e

Au(Ge,Ga)

GaAs

Sample B (w ith 5 nm N i firs t layer)

A uN i

Au-Ge-N i:

GaAs

Au(G a)N i,G e

A |A u (G e ,G a )'/ /T7 / / / T 7 7

I

N ix GaAs GaAs L

N iAs(G e)GaAs

Fig 1 9 Schematic illus tra tio n o f the sequence o f a lloying reactions fo r sample A and B, respectively [81]

A novel theoretical model fo r electron transport has been presented by Shenai [29] and extrem ely low pc is reported using N i/G e/A u m etallizations in Sn-doped n+-GaAs layers The N i/G e/A u contact revealed extensive GaAs consumption [50] The pc o f A u/A uG eN i contacts formed by rapid electron-beam annealing [83] is much low er than that formed by other techniques The contacts formed by th is technique are found to be considerably stable w ith therm al aging Ion beam m ixing has been utilized to produce m orphologically improved Ohmic contacts to n-GaAs using G e/N i/A u m etalliza tion [84] The values o f pc depend both on ion dose and ion im plant temperature.

16

Solid-state and alloyed A uG eN i/Z rB 2/A u Ohmic contacts to n-In^G ag 47As have been investigated fo r optoelectronic integrated circuits [85] Z rB 2 acted as a d iffus ion barrier m these contacts Non-alloyed, high-temperature stable G e-N i-Au Ohmic contacts to n-GaAs w ith a LaB6 d iffusion bam er are also reported [86] The stable W S iN d iffus ion bamer (against gold) in A u /W S iN /(A u ,G e,N i) m etallization [87] resulted in a lloying depth less than 10 nm and values o f pc in m id 10‘ 7 Q-cm2 range The influence o f the internal layer (A u,G e,N i) sequences on pc is optim ized and it is found that a combination o f 25 nm Au, 5 nm N i, 20 nm Ge resulted in low er pc values Reproducible and therm ally stable non-alloyed Ohmic contacts are achieved by interposing a W 60N 40 d iffusion barrier between the N i/G e and the A u in N i/G e/A u system [35]

Both the contact un ifo rm ity and the res is tiv ity o f G e/A u/N i/A u Ohmic contacts may be greatly improved when a th in T i/A u layer is deposited on the GaAs wafer backside p rio r to alloying [88] T i/A u cap also improves the topography o f N i/A uG e/N i/A u m etallization [71] Very small area G e/A u/N i/A u contacts on GaAs have been reported [89] The proportions o f N i and AuGe m R T A A uG e/N i/A u Ohmic contacts have also been optim ized fo r low-temperature annealing [90] The annealing temperature fo r form ing low pc contacts to th in n+ GaAs epilayers can be reduced from the standard 420 °C to 300-320 °C by varying the percentage o f N i in the contact Non- alloyed and alloyed low resistance N i/G e /A u /T i/A u Ohmic contacts w ith good m orphology fo r GaAs using a graded InGaAs cap layer have been developed [91] A low pc o f 4x10 '8 Q-cm2 fo r a N i/A u -S n /N i contact on n-G alnAs has also been obtained and compared w ith a N i/A u -G e/N i contact [92] The Au-G e contact shows better results than that o f Au-Sn contact The contact res istiv ity and therm al stab ility o f N iG e(A u)W Ohmic contacts were studied as a function o f the A u layer thickness between 0 and 75 A [93] A gold layer o f -6 0 A produced a m inim um contact resistance o f 0 15 Q-mm

1.3.7 Multilayer Au/Ge/Au/Ni/Au metallizations

A five-layer Ohmic contact structure [41,94] (F ig 1 10) annealed at 425 °C fo r 60 s using a R T A has the fo llow ing advantages compared to conventional approaches• The donor/acceptor layer is separated from the barrier layer Th is prevents

undesired chemical reactions between the dopants and the bamer• Evaporation o f eutectic alloys containing the dopants is not necessary Thus

fractional d is tilla tio n m the evaporation process is avoided and the resulting contacts show better reproducibility.

• The top gold layer is su ffic ien tly th ick to perm it bonding A post evaporation o f gold over the alloyed area is not needed

17

• O nly three metal evaporation sources are required to create the five-layer structure Using th is m etalliza tion contact resistiv ities in the 10"7 Q -cm 2 range on both n- and p- type m aterials are obtained Th is m etallization technique is applicable fo r fabricating a wide variety o f m icrowave and lightwave devices including sw itching diodes and fie ld effect transistors

Au(240 nm)N i( l l nm) Au(14 nm ) Ge(14 nm ) Au(14 nm)

Fig 1 10 Cross-sectional view o f five-layer A u/G e/A u /N i/A u m etallization [94]

1.3.8 Ni/AuGe/Ag/Au metallizations

S ilver (A g) barrier Ohmic contacts are very im portant fo r GaAs based H E M T structures, such as A lG aAs/G aAs, A lG aAs/InG aAs and A lInA s/InG aA s It has been found that the Ohmic contact to GaAs based H EM Ts requires high a lloying temperature because the Ohmic metal has to penetrate the high band gap A lG aAs to reach the low band gap GaAs (or InGaAs) channel layer The conventional AuGe based Ohmic schemes (N i/A uG e/A u) can not w ithstand high temperatures above 450 °C The sample alloyed at high temperature, in order to diffuse Ohmic metal deeply in to the H E M T layer, may exhib it very rough m orphology and high contact res is tiv ity due to the ln terd iffusion between the top A u layer and substrate [95] To a llow higher temperature a lloying , researchers have added d ifferent d iffus ion barriers such as silicon nitride, T iW and silve r to this alloyed metal system Among them the Ag d iffus ion barrier is one o f the m ost popular approaches and has been used in most o f the reported state-of-the-art H EM Ts [96-99] Low resistance (<0 1 Q -m m ) Ohmic contacts to the low er band gap m aterial in both A lG aAs/G aAs and A lInA s/G alnA s M O D FE T structures can be fabricated using s lig h tly d ifferent m etallizations based on A uG eN i/A g /A u [100] Ag in an A lG aAs/G aAs M O D FE T creates an A g /A u a lloy that reduces Ga outd iffusion from the semiconductor at temperatures up to -5 70 °C In th is way the GaAs stochiometry beneath the m etallization is w e ll maintained

B A R R IE R L A Y E R

SEM IC O N D U C TO RS U B STR A TE

18

1.3.9 Au/Ni/NiSn metallizations

These m etallizations are electroplated to n-GaAs. K e lly and W rixon [101] developed low temperature electroplated alloyed A u/S nN i/A u Ohmic contacts in 1978. They observed that layer thicknesses o f 4000A Au, 5000A SnN i and 3 500A Au gave m inim um pc after alloying at 300 °C fo r 3 m in. T in (Sn) in a shallow donor and is 0.006 eV from the edge o f conduction band in GaAs. Th is results in a barrier w ith a high tunneling probability. A S nN i/N i/A u Ohmic contact scheme to n-GaAs has also been proposed [102], Inclusion o f a Pt layer to reduce A u (acceptor) d iffusion into the contact results in higher pc. In A u/N i/SnN i/G aA s junctions, Sn is expected to diffuse into Au-induced Ga vacancies thereby producing an excess electron concentration [103]. N i is expected to provide good wetting so that Sn does not "b a ll up" during the a lloying process. Th is process is s im ilar to that occuring fo r Au/N i-G e/G aAs contacts w ith Sn taking the place o f Ge. The addition o f Sn to Au/N i/n-G aAs system lowers pc by at least tw o orders o f magnitude [103].

as-deposited 300 °C 700 °C 750 °C 900 °C

W W W W N ' . ' n wNi-In Ni-In Ni-In v V---V-- -

------N i-In --------------Ni ---------- -► N 2GaAs -► N ,G aA s

-*• N 2GaAs NiAs • 4

GaAs ; : GaAs ;InxG a,.xAs

: GaAs

-9

I"»G a ' - ASN iA !GaAs GaAs

Fig. 1.11. Schematic illus tra tion o f alloying sequence o f N i/N i-In /N i/W m etallizations to n+-GaAs [105],

1.3.10 NilnW metallizations

Rough surfaces and deteriorated contact edge profiles are observed in AuG eN i Ohmic contacts after annealing in form ing gas at 440 °C fo r 2 m in needed to form an Ohmic contact [81,104], Th is lim its extendability o f this contact fo r use in submicron devices. N iln W Ohmic contacts have been developed which are very attractive fo r GaAs M ESFETs because o f improved morphology and therm al stab ility after Ohmic contact form ation [105-109], A typical example o f the a lloying sequence in the N i/N i-In /N i/W m etallization system [105] is illustrated in Fig. 1.11. In itia lly , N i from the upper layer diffuses into the N i-In layer, form ing a m ixture o f amorphous N i-In and polycrystalline N i phases. Under heat treatment at 300 °C fo r 30 m in, an epitaxial N i2GaAs phase forms at the N i/G aAs interface w hile In partia lly interm ixes w ith W and N i2GaAs. A t 700 °C, broad areas o f In^GaÂs phase, w ith x=0.6, form at the N i2GaAs/GaAs interface.

19

Heating to 750 °C produces additional N iA s precipitates under N i2GaAs Further annealing at 900 °C leads to interfacial m icrostructures w ith large grains o f regrown Ir^GaÂs w ith x=0 3 covenng -90% o f the interface, the other 10% comprising o f N iA s phase N i3In form s on top o f the InxGa,.xAs phase, w h ile the W layer remains above the N iA s and N i3In phases The W layer is usually inert and causes no electrom igration problems m applications

A reduction m pc fo r the N iln W m etallizations has been obtained by adding donors to the contact m aterial The N i(S i)In W contacts w ith various S i concentrations were prepared and annealed at temperatures in the range o f 750-900 °C fo r 2 s The lowest pc value reached 8x10 '7 Q-cm2 at 5% Si and an approxim ately 50% increase in the S i doping at the InxGa,.xAs (x=0 4) layer was believed to be achieved [106] Excellent stab ility in M ESFETs w ith the N iln W Ohmic contacts was observed [105] No deterioration was observed at 400 °C fo r 180 h, 450 °C fo r 18 h and 500 °C fo r 2h The ro le o f N i on N iln W contacts was investigated [107] and it was found that N i contributed to both a reduction o f pc and to improved therm al stab ility

The unreacted In after annealing is o f great concern fo r therm al stab ility The unreacted In m elts above 156 °C and the electrical properties o f the contacts deteriorate To deposit In at the critica l thickness is extrem ely d iffic u lt and is not practical The addition o f an element which form s high m elting point (T m) compounds w ith the unreacted In improves therm al stab ility after contact form ation and is attractive from the view point o f the fabrication process N ickel is observed to form various N ixIny compounds which have T m higher than 900 °C N i3In (T m=908 °C), N iA s (T m=962 °C) and In^GaÂs (T m>900 °C) were observed in the N i/N i-In /N i/W contacts and no evidence fo r the existence o f unreacted In was obtained [107] A very low pc in the range o f 10'7 Q-cm2 was obtained w ith N iln W m etallizations after annealing under As overpressure [108] Glas et al [109] reported a N i4(G aAs)3 annealing product fo r the firs t tim e in N iln W contacts

1.3.11 Ni-based non-gold metallizations

Therm al instab ility is o f serious concern fo r AuG eN i contacts u tilized in very large scale integration (V L S I) devices As previously noted, th is undesirable instab ility is due to form ation o f low m elting point (T m~375 °C) p-AuGa phases during contact annealing In order to improve the thermal instab ility o f the AuG eN i contacts, Ni-based non-gold Ohmic contacts have been developed [110,111] The rem oval o f A u from the AuG eN i contacts is effective in im proving the therm al instab ility after contact form ation as seen in N iG e contacts [110] The therm al stab ility o f N iG e contacts is

20

strongly influenced by the compounds that are formed at the interface between the N iG e and the GaAs after contact annealing The compound form ation is controlled by the Ge concentration in the N iG e contacts and the annealing temperature A contact w ith 38% Ge prepared by annealing at 600 °C had a smooth surface and yielded good thermal stab ility at 400 °C, which was due to the form ation o f refractory N iG e compounds w ith a m elting point (T m) o f 850 °C

as-deposited 200 °C 600 °C

O H M IC I (L o w Pc ) i>

a-GeN i

a-Ge_Nl

Ni^GaAs*n+-GaAs

- - y * N ix GaAsRegrown n+T-GaAs

O H M IC t (H igh pc )

N ia-Ge

N in+ -GaAs

N i a-Ge

N iv GaAs

N iG e N ix GaAs

Regrownn++-GaAs

Fig 1 12 Schematic illus tra tion o f m icrostructural changes o f N iG e Ohmic contacts, where a-Ge represents amorphous Ge [110]

A model fo r the electron transport mechanism through the GaAs/NiGe interface was also proposed by correlating the electrical properties and the m icrostructure The interfac ia l m icrostructure o f the N iG e Ohmic contact w ith low pc is discussed by referring to F ig 1 12 A t the in itia l stages o f annealing at 200 °C, N i reacts w ith GaAs to form a ternary N ixGaAs compound by

xNi + GaAs -> N ixGaAs (1 13)

The thickness o f the N ixGaAs layer increases w ith increasing the thickness o f the N i layer deposited d irectly on the GaAs A fte r annealing at temperatures above 300 °C, N i and Ge start to react, form ing N iG e compounds W hen N i in the N ixGaAs layer reacts w ith Ge, the thickness o f the N ixGaAs layer reduces, leaving the regrown GaAs layer as shown by a dashed line in the bottom o f F ig 1 12 Th is reaction is expressed by

N ix GaAs + Ge -» NiGe + GaAs (regrowth) [110] (1 1 4 )

W hen N i reacts w ith GaAs form ing the N ixGaAs layer, a sm all amount o f Ge atoms d iffuse to th is ternary layer Some o f the Ge atoms remain m the regrown GaAs,

21

resulting m form ation o f a n^-GaAs layer The Ge-doped n^-G aAs layer enhances earner tunneling probability and Schottky behaviour transforms to Ohmic behaviour, leading to a reduction in pc Therm ally stable N 1 S1W Ohmic contacts to n-GaAs have been developed [111] Ohmic behaviour was found to have dependencies on the Si concentration o f the N 1S1W contacts and the annealing condition Ohmic contacts w ith 40% Si, prepared by annealing at 650 °C, had smooth surfaces and yielded excellent therm al stab ility during subsequent annealing at 400 °C after contact form ation Thecross sections o f the N iS iW Ohmic contacts before and after annealing are shown inFig 1 13 W hen the N iS iW contacts are annealed at temperatures above 300 °C, the Si atoms diffuse in to the crystalline N i layers to form amorphous m ckel-silicon layers (indicated by a -N i-S i) A t higher temperatures, the a -N i-S i layer close to the GaAs surface transforms into the crystalline structure that is indicated by c-N i-S i The best candidate fo r th is crystalline structure as determined by X R D measurements and TE M observation is 5 -N i2Si

A t fin a l stage o f annealing -6 5 0 °C

a-N i-S ik c -N i-S i^ n++-GaAs

n+-GaAs

(N O N -O H M IC )

Fig 1 13 Schematic illus tra tion o f m icrostructural changes o f N iS iW Ohmic contacts, where a -N i-S i and c -N i-S i indicate am orphous-nickel-silicon and crystalline-m ckel- silicon, respectively [111]

The N ixGaAs phases were not detected in the N iS iW Ohmic contacts even at the in itia l stages (=300 °C) o f R T A Therefore, the n++-GaAs layers fo r the N iS iW Ohmic contacts were believed to be formed by in-d iffusing S i atoms The growth o f the N iA s compounds results in non-Ohmic behaviour, which is schematically shown m F ig 1 13 The form ation o f N iA s is found to be suppressed by increasing the S i concentration and decreasing the annealing tim e using R T A The top W layer reduces the sheet resistance o f the contact m etal, improves the surface m orphology o f the N iS i contacts and also reduces the form ation o f N iA s compounds

a-N i-S i c -N i-S i N iA s

n-GaAs

A t in itia l stageAs-deposited

N i a-N i-S iS i SiN i a-N i-S i

n-GaAs n-GaAs

22

The kinetic effects o f a layering sequence in A l-G e-N i Ohmic contact components on (OOl)GaAs were investigated by Lampert et al. [112]. A l-G e-N i m etallizations have been successfully fabricated on both n- and p-type GaAs [113]. For n-type GaAs, the thickness o f Ge deposited and the a lloying tim e have a large influence over the degree o f O hm icity observed. The contact interface is extrem ely fla t and un iform w ith a continuous single phase polycrystalline layer o f A l3N i adjacent to the semiconductor. K a lku r et al. [79] have analyzed the m icrostructure o f A l-G e-N i R TA Ohmic contacts. Ep itaxia l G aAs/N iA l/G aAs heterostructures consisting o f buried N iA l layers and GaAs overlayers that are m onocrystalline and w e ll aligned were also reported [114].

The A l-S n -N i [115] m etallizations can produce Ohmic contacts to both n- and p- type GaAs and they have morphological characteristics superior to the A l-G e-N i contacts [79, 112, 113]. It is easy to pattern A l-S n -N i w ith the lif t - o f f process and the surface remains remarkably smooth and planar after a lloying . Contact resistiv ities in the range o f 10'4 Q-cm2 are obtained fo r both n- and p-type GaAs [115]. The homogeneity o f alloyed N i-S n Ohmic contacts to n-GaAs was investigated by N iko laev et al. [116]. They reported intermediate phases N iA s, N iG a, and SnAs fo r the inhomogeneity o f these contacts. S im ila rly , the role o f Ge in N iAs/n-G aAs, N iAs/G e/n-G aAs and Ge/N iAs/n-G aAs structures have been investigated [117].

1.3.12 Au-Ge metallizations

M ost commonly employed Ohmic contacts to n-type GaAs are based on the Au-12wt.% Ge eutectic a lloy [118,119]. A m inim um pc o f 9 x l0 '7 Q-cm2 is obtained fo r an epilayer doping o f 3 x l0 17 cm'3 after annealing at 450 °C fo r 214 m in [119], M elting o f th is eutectic a lloy at a temperature o f about 360 °C causes the localized dissolution o f GaAs (presumably at pinholes in the native oxide). The higher so lu b ility o f Ga in the Au-Ge m elt encourages the so lid ifica tion o f As-rich GaAs during cooling. Ge is thus incorporated preferentia lly on the Ga site in the precipitated GaAs, resulting in n-type GaAs and a tunneling Ohmic contact. Iliad is and Singer [119] observed that the role o f Ge in Au-G e m etallization is not sim ply as dopant, but it is also the key element in in itia ting the m elting. B arrier height reduction in Au-Ge m etalliza tion is investigated by Iliad is [118]. A massive reduction in barrier height [<()B (TFE)=0.34 eV] at a 300 °C heat treatment is due to the large fraction o f Ge atoms that is not accommodated in Ga vacant sites and indiffuses along w ith the A u atoms.

23

Recently, non-alloyed Au-Ge Ohmic contacts to n-GaAs have gamed sigmficant research interest [120-123] Low emperature, non-alloyed Au-Ge contact form ation is a m ulti-step process [121] Ohmic behaviour was observed after 3 hrs o f annealing at 320 °C and a Ai^Ga phase was found at th is stage Samples annealed w ith S i3N 4 cap layers to prevent As sublim ation resulted in higher pc values than uncapped samples [121] A novel model was presented fo r single crystal, non-alloyed epitaxial Au-Ge Ohmic contacts in R e f [120] According to this model, A u firs t comes in contact w ith the GaAs at points where the Ge layer is either very th in or nonexistent I t reacts w ith the GaAs to form AuGa phases which results in the form ation o f free As and/or vacancies in the GaAs lattice The Ge then rapidly mdiffuses substantially v ia Ga vacancies form ing GeAs related phases Heavy Ge doping may then occur, leading to Ohmic contact form ation Isotherm al regrowth o f doped, smooth and planar Ohmic contacts w ith low pc using Au-Ge m etallization has also been reported [122] Th is procedure is suitable fo r form ing Ohmic contacts on shallow junc tion devices Extrem ely low resistance non-alloyed Au-Ge Ohmic contacts on 5-doped GaAs have also been developed [123] and recently, properties o f Au-Ge Ohmic contacts after the a lloying process have been studied [124]

1.3.13 Au/Te/Au metallizations

In A u /Te /A u m etallizations, Te is used as the dopant to form an Ohmic contact to n-GaAs Te atoms become electrically active donors on ly when occupying As sites Therefore, As vacancies must be created during m eta lliza tion A lthough reports on Au/Te/A u/G aAs contacts are scarce, several mechanisms have been invoked to explain the ir Ohmic behaviour In particular, W uyts and co-workers attributed the form ation o f an Ohmic contact to the form ation o f either a metal/Te/Ga^Te3(Au)/G aAs or a m etal/(Te)/G ajTeÂs)/G aAs heterostructure [125-127]

M under et al [128] investigated pulsed laser beam and furnace annealed A u /Te /A u m etallizations For furnace annealed contacts the mechanism responsible fo r the Ohmic behaviour was dominated by the form ation o f a Ga^Te^ polycrystalhne Te and a h igh ly disordered GaAs layer [125,129] For laser annealed contacts electron tunneling through the potential barrier invo lv ing localized gap states was postulated fo r Ohmic behaviour The effects o f an A120 3 cap on the structural and electrical properties o f A u /Te /A u contacts on n-GaAs were also ameliorated [130,131] Contacts annealed w ithout the capping layer became Ohmic after annealing at 420 °C fo r 3 mm w ith a pc o f ~1 6x1 O'4 Q-cm2 [130] In the uncapped system, the contact reaction is dominated by the Au-G aAs interaction, as indicated in TABLE I by the appearance o f A u 7Ga2 phase and large arsenic losses

24

Annealing under a capping layer changes the kinetics o f the contact reaction. For sealed G aAs/Au/Te/Au contacts, the losses o f both Te and As are lim ited. Suppression o f As vapourisation restrains the Au-GaAs reaction, w h ile reduction o f Te sublim ation activates the Te-GaAs reaction. Ga^Te, and A s2Te3 are the m ain products o f the interaction, apart from unreacted Au. Such interactions, however, do not lead to the form ation o f Ohmic contacts to n-GaAs. The results indicated do not support the heterojunction model o f Ohmic contact, but rather testify in favour o f the doping model.

TABLE I. The influence o f A120 3 capping layer on the outcome o f n-GaAs/Te and n-G aAs/Au/Te/Au contact reaction [131].

Contactmaterial

Annealing

T( °C) t(m in)

Phasecomposition

As loss

NAsx l0 15(atom/cm2)

Te loss

NTex l0 15(atom/cm2)

Te As-deposited Te380 3 Te (small amount)420 3 Te (traces) 300460 3 Te (traces) 310

Te/A l20 3 380 3 Ga2Te3420 3 G a ^ e j, As2Te3 (traces) 10460 3 Ga2Te3, As2Te3 (traces) 33

Au/Te/Au As-deposited Au+Te380 3 Au+AuGa(50 at. %)420 3 Au+Au7Ga2 139 45.5460 3 Au+Au7Ga2 320 50.4

Au/Te/Au/ 380 3 Au+Ga2Te3+As2Te3(traces)a i2o 3 420 3 Au+Ga2Te3+As2Te3(traces) 17.3 0.5

460 3 Au+Ga2T e3+As2T e3(traces) 53 0.7

1.3.14 High-temperature refractory metallizations

The m ain reason fo r using refractory metals, e.g., W , T i and M o, is to achieve thermal stab ility o f the contact both during processing and in real applications. Refractory metal contacts are expected to w ithstand high temperatures encountered during device

25

processing such as those used to activate the ion implanted dopants. In addition, the m etals/alloys can act as a barrier against Ga and As ou t-d iffiis ion . Since the refractory m etals/alloys are good alternatives to N i/AuG e m etallization, many research groups have attempted to exp lo it these high-temperature m etallization schemes.

Among the composites recently investigated are [27,28,86,105,107-109, 132-142] as fo llow s: Au/TiW /G e/Pd, N iln W , M oG eW , MoGe, G e-M o-LaB6-Au, G e-W Si2-A u, W Ge, W -In , T iW S ix, T iW /G e, T ixW yS iz, T i/P t/A u , T i/P t and T i/M o (w ith Si & Ge). In most o f these investigations, W is common and chosen over other high temperature metals because o f its com patib ility w ith processes used in dry etching (reactive ion), its thermal stab ility (<(>B on GaAs is stable up to 700 °C) and its com patib ility w ith A lC u w iring . Refractory N iln W m etallizations [105,107-109] have already been discussed. Arsenic(As)-doped G eM oW i.e., G e(As)M oW refractory Ohmic contacts can be fabricated fo r n-GaAs using d ifferent annealing techniques [108,132]. V ery low contact resistiv ities, in the range o f a few 10'7 Q-cm2, have been obtained when annealed under an As overpressure. W ithout As doping, the same m etallization gives higher pc values.

A m inim um pc o f 5x10"6 Q-cm2 has been obtained w ithout arsenic doping in the G eM oW contacts annealed at 800 °C fo r 7 m in [132,134]. As the arsenic doping is increased, the pc values are decreased w ith pc~ 2x10 '7 Q-cm2 fo r an arsenic doping o f 1020 cm '3 (800 °C, 10 m in). A m inim um pc o f 0.176 Q -m m is obtained at an annealing temperature o f 500 °C using G eM oW contacts to n-GaAs w ith a In05Ga05As cap layer [133]. The Iii^ G a^ A s cap layer significantly widens the range over w hich the n-GaAs is Ohmic (300-700 °C). M erkel et al. [28] applied G eM oW m etallization as source/drain contacts to G aAs-M ESFETs w ith A l and T iP tA u as gate contacts. Both G eM oW /TiP tA u and G eM oW /A l are therm ally stable up to 450 °C. Therm al cycling at 500 °C resulted in degradation o f both contacts w ith G eM oW /A l exhib iting less degradation. Furtherm ore, self-aligned high-temperature MoGe Ohmic contacts fo r H BTs have been fabricated by Ketata et al. [135].

Refractory m etallizations incorporating d iffusion barriers [86] or refractory m etalliza tion d iffusion barriers [27,136] can improve the overall therm al stab ility o f Ohmic contacts. The choice o f W S i2, which also acts as a d iffusion barrier, is due to its phase stab ility w ith GaAs [136]. T iW and LaB6 d iffusion barriers are also utilized in PdGe and G eM oAu m etallizations, respectively [27,86], Therm ally stable WGe Ohmic contacts fo r G aAs/AlG aAs H BTs have also been reported [137]. W -In-(G e, S i or Te) Ohmic contacts to n-GaAs show therm al stab ility up to 500 °C w ith good surface m orphology [138], The W -In-S i/n-G aAs structure shows a pc o f 3x10-6 Q-cm2. Ohmic

26

contacts to n-GaAs using graded-band-gap layers o f low pressure organometallic chemical vapor deposition (LPM O C VD )-g row n InxGa,.xAs and sputter-deposited T iW S ix film s were investigated [139]. The as-deposited contacts exhibited pc values o f lx lO '5 Q-cm2 and 9x1 O'7 Q-cm2 fo r In^G a,,5As and InAs caps, respectively. T i/P t/A u non-alloyed source and drain contacts to Sn or Si doped AlG aAs/G aAs H EM Ts were fabricated w ithout additional intermediate InGaAs or InAs layers [140]. T i/P t m etallization has been utilized to form contacts on both n+-InA s em itter cap and p+ base layers o f H BTs [141]. Comparison o f T i, M o and C r m etallizations w ith Ge- or S i- doped GaAs have been reported [142]. T a b l e I I summarizes the results obtained w ith many o f these refractory metals. One can clearly see that a ll o f these refractory contacts have very low pc and are stable at -4 00 °C. Th is temperature is compatible w ith the w iring and packaging process.

T a b l e I I. Summary o f refractory m etallizations to n-GaAs.

M eta lliza tion Doping Contact concentration resistiv ity (cm-3) (Q-cm 2)

Thermalstab ility

Application Ref.No.

A u/T iW /G e/Pd 2 x l0 18 1 .4 5 x l0 '6 4 1 0 °C, lh M E S FE T [27]G eM oW 3 x l0 18 0.21 Q-mm* Up to 450 °C, 10 m in M E S FE T [28]G e(As)M oW 4 x l0 18 ~ 4xl O'7 H B T [132]G eM oW 5 x l0 18 0.176 Q-mm [133]GeM oW lx lO 18 2 x l0 -7 H B T [134]MoGe lx lO 18 H B T [135]A u /W S i2/Ge lx lO 16 5x10 '5 460 °C, lh M E S FE T [136]WGe 7 .5 x l0 '7 H B T [137]W -In -S i 3x1 O'6 Up to 500 °C [138]T iW /S i/A u 3 x l0 18 -9x1 O*7 Up to 500 °C [139]T i/P t/A u lx lO 19 - l . lx lO '6 H E M T [140]T i/P t ~ 3 x l0 ‘ 7 H B T [141]* 2Q -m m and Q-cm " can be correlated i f the contact w id th is known.

1.3.15 InAs-based metallizations

In form ing good Ohmic contacts to large band gap GaAs, narrow band gap InAs has been used as a cap layer sandwiched between the metal and GaAs. Since the Ferm i

27

level o f metals is norm ally pinned in the conduction band o f InA s (F ig 1 14(a)), the conduction barrier at metal-GaAs interface can be drastically reduced However, due to the re la tive ly large band gap difference between GaAs and InA s (F ig 1 4(b)), on ly a reasonable value w ith non-alloyed pc o f about 10'6 Q-cm 2 has been obtained in a nearly abrupt layer o f n+-InA s [143] To elim inate th is band d iscontinuity and thus the high barrier fo r carrier transport, an epitaxial layer o f InxGal.xAs w ith the In mole fraction graded from x=0 at the GaAs interface to x = l at the surface contacting m etal has been proposed [16] and pc values in the range from 5 x l0 '7 to 5 x l0 -6 Q-cm2 are obtained This graded metal/n-InAs/n-In^Ga,_xAs/n-GaAs (x=0-0 53) structure is shown in Fig 1 14(b) Applying a graded InGaAs cap layer has also led to pc o f 5 x l0 *8 Q-cm2 fo r non-alloyed T i/P t/A u contacts [17]

(a)

non abrupt interface

/ / / / / , E'Gai

(b)n -I^ G a ^ A s

Fig 1 14 Band-bending diagrams fo r (a) metal on n-InA s and (b) metal on n-InAs on graded n+-In xGa!_xAs/n-GaAs [144]

A refinem ent to the InAs on GaAs procedure is to replace the th ick and cumbersome InGaAs graded layer w ith a thm superlattice structure In doing so, the refinem ent resulted m dramatic reductions o f pc (1 5 x l0 -8 Q-cm2) on n-GaAs as demonstrated by Peng et al [15] using an strained layer superlattice (SLS) structure Ohmic contacts using an SLS structure have many advantages F irs tly , the SLS scheme requires a sm aller overall layer thickness than the graded structure Secondly, a SLS is easier to fabricate and pliable fo r d ifferent structures Hence it is convenient to incorporate th is structure in devices and optim ize it to obtain even low er pc The im plem entation o f th is SLS scheme m a G aAs-M ESFET has been demonstrated [144] Huang et al [145] have concluded that quantum tunneling through SLS conduction bands plays an essential role in the effective barrier low ering leading to extrem ely low contact resistance

28

1.4 Applications of Ohmic Contacts to n-GaAs

Ongoing m in ia turization o f GaAs devices requires Ohmic contacts having very low pc (<10"6 Q-cm2), easy reproducib ility, a shallow (non-spiking) interface, smooth surface m orphology and therm al stab ility M any devices based on GaAs and its alloys, such as the high electron m ob ility transistor (H E M T), heterojunction bipolar transistor (H B T), charge in jection transistor (C H IN T)/negative resistance fie ld -effect transistor (N E R FE T), metal-semiconductor fie ld -effect transistor (M E S FE T), m odulation doped fie ld -effect transistor (M O D FET) and m ultip le quantum -well (M Q W ) superlattice devices require reliab le planar low-resistance Ohmic contacts Nonspiking Ohmic contacts are essential to GaAs-based very large scale integration (V L S I) technology Three o f the most im portant issues are ( 1) achievement o f low-resistance Ohmic behaviour w ith a w ide processing w indow, ( 1 1) therm al stab ility at temperatures up to -5 0 0 °C and (1 1 1) applicability to sm all contact areas (down to sub-(am sizes) Thermal stab ility o f Pd/In Ohmic contacts [65,66,68,69] is more than suffic ient to meet the demands o f subsequent device and circuit fabrication steps Pd/Ge Ohmic contacts fo r GaAs M ESFETs [21,31,32,38,53] are an even better alternative to conventional AuG eN i ones, w ith a fabrication process fu lly compatible w ith standard M E S FE T technology M oreover, these contacts are obtained by a solid-phase interaction at a low er temperature allow ing easier control o f the process, better flatness and edge defin ition

A lG aAs/G aAs heteroj unction structures are extensively used in fabricating H BTs, H EM Ts and C H IN T/N ER FETs Rapid therm al annealed (R T A ) Pd/Ge [38] and G e/Pd/W /Au [55] contacts have already been u tilized in fabricating H BTs The successful application o f Pd/Ge contacts is also reflected in m ultip le quantum -well (M Q W ) structures [18,39] Chen et al [146] found that the Pd/Ge/Au contact is not suitable fo r the H E M T structure, but it could be useful in some heteroj unction devices, such as M Q W structures, in which the apparent in a b ility o f the Pd-Ge to diffuse beyond the A lG aAs/G aAs interface could be used to advantage Based on the above assumption Wang et al [20] have successfully applied the Pd/Ge Ohmic scheme to an A lG aAs/G aAs H E M T Han et al [56] developed a non-alloyed Pd/G e/Ti/P t Ohmic contact fo r optical sw itch (OS) C H IN T /N E R FE T devices require shallower Ohmic contacts La i and Lee very recently developed even shallower R T A Ohmic contacts fo r C H IN T /N E R FE T devices using Pd/Ge m etallizations [22,37] Using th is process technology, the fabrication tolerances fo r the C H IN T /N E R FE T become much less critica l

29

TABLE III. Summary o f Pd-based m etallizations to n-GaAs.

M eta lliza tion Dopingconcentration(cm '3)

Annealing Contact condition resistiv ity

(Q -cm 2)

Application Ref.No.

Pd/Ge lx lO 18 325 °C, 30 m in - lx lO "6 M Q W [18]Pd/Ge 4 x l0 18 325 °C, 30 m in ~ 3 x l0 '7 H E M T [20]Pd/Ge 2 x l0 18 R TA , 450-500 °C, ó O s -lx lO '6 C H IN T /N E R FE T [22]Pd/Ge 2 x l0 17 R TA , 450-500 °C, 6 0 s ~ lx l0 ’ 6 C H IN T /N E R FE T [37]Pd/Ge 1 .5 x l0 17 325 °C in form ing gas 0.16 Q-m m M E S FE T [31]Pd/Ge 1 .5 x l0 17 325 °C, 30 m in 0.16 Q-m m M E S FE T [32]Pd/Ge 3 x l0 18 R TA , 500-750 °C, 10s~7.5xl0*6 H B T/M E S FE T [38]Pd/Ge 4 .5 x l0 18 250-500 °C, 1-5 m in ~ 1 .25x l0 -6 M Q W [39]Pd/G e/Ti/A u 1.5x1017 325 °C, 30 m in 4 x l0 '6 M E S FE T [53]Pd/G e/Ti/A u lx lO 17 340 °C, 2 m in ~ lx l0 '5 M E S FE T [21]G e/Pd/W /Au lx lO 17 R TA , 800-900 °C, 10s~5xl0’ 6 H B T [55]Pd/G e/Ti/P t 2 x l0 18 R TA , 450-450 °C 4.7x1 O'7 OS [56]Pd/Ge/Au lx lO 18 450 °C, 30s - lx lO "6 H E M T [146]

* 2Q -m m and Q-cm can be correlated i f the contact w id th is known.

H EM Ts are also fabricated on n-GaAs by incorporating d iffusion barriers [87,99] and capping layers [71] to AuG eNi Ohmic contacts. Two-stage annealing incorporating a Ag barrier in AuG eN i contacts is used to fabricate conventional H EM Ts (C H EM Ts) [99]. Th is Ag barrier is also used in fabricating A lG aAs/G aAs and A lInA s/G alnA s M O D FETs [100], Rapid thermal annealed (R T A ) AuG eN i contacts w ith a W S iN barrier are utilized to fabricate M ESFETs as w e ll as H BTs and H EM Ts [87]. G oronkin et al. [72] found that AuG e/N i Ohmic contacts are more suitable fo r GaAs M ESFETs than fo r G aAs/A l GaAs M O DFETs. M u ltilaye r AuG eN i Ohmic contacts [94] are very attractive fo r fabricating a wide variety o f m icrowave and lightwave devices including sw itching diodes (SDs) and M ESFETs. GaAs M ESFETs w ith AuG eN i and N iln W m etallizations have been successfully fabricated [105] and the ir characteritics were evaluated. N iln W contacts have improved thermal stab ility compared to AuG eNi contacts and the fabrication process is compatible w ith the current GaAs M ESFET technology. Therm ally stable non-gold N iG e and N iS iW Ohmic contacts fo r M ESFETs are reported by Takata et al. [110,111]. A l-S n -N i Ohmic contacts [115] on both types o f GaAs w ith pc~10~4 Q-cm 2 are very cost effective in a rapid turnaround fabrication procedure. Refractory m etallizations (TABLE II) are very attractive fo r the fabrication o f therm ally stable, high-speed, self-aligned GaAs devices. The applications o f Pd- and

30

Ni-based Ohmic contacts, along w ith other useful parameters, are listed in T a b l e I I I and T a b l e IV , respectively

TABLE IV Summary o f Ni-based m etallizations to n-GaAs

M etallizations Dopingconcentration(cm-3)

Annealingcondition

Contactres is tiv ity(Q -cm 2)

Application R efNo

AuG e/N i (2 -7 )x l0 17 340 °C, 30 m in H E M T [71]Au/G e/N i 2 x l0 18 460 °C, 8 m in --------- M E S FE T , M O D FET [72]A u /W S iN / ( l- 2 )x l0 17 430-470 °C, 150s ~ 5 x l0 -7 M ESFET, [87]Au/N i/G e H E M T & H B TA u/G e/A u/ 2 x l0 18 425 °C, 1 mm 8 8x1 O'7 SD, M E S FE T [94]N i/A uA u/A g /A uG e/N i-------- 250 °C, 20s + ~0 1 Q-m m H E M T [99]

400 °C, 40sAu/Ag/AuG e/N i~2x 1018 540-600 °C 0 06-0 2 Q-mm* M O D FET [100]N iln W R TA , 800 °C, ~7s M E S FE T [105]N iln W R T A M E S FE T [107]N i/G e/N i 1x10'* 200-700 °C, 5 mm 0 78 Q-m m M E S FE T [110]N i/S n /A l 1 9 x l0 18 505-605 °C, 1-4 mm lx lO "4 H B T [115]* 2Q-m m and Q-cm can be correlated i f the contact w id th is known

1.5 Conclusions

From the above discussions it is evident that therm ally stable, non-spiking Ohmic contacts are necessary to meet device m in ia turization and speed requirements Special attention is given to rapid thermal annealed (R T A ) Ohmic contacts because the R T A process often gives better results than those o f conventional furnace annealing I t is found that the scanned electron beam (SEB) annealing process is more advantageous than the R T A process Refractory Ohmic contacts have been developed to meet the demands o f self-aligned fabrication process o f GaAs devices

The highlights o f the most recent developments in Ohmic contacts are summarized as fo llow s• M eta lliza tions such as Ge/Pd, Ge/Pd/Au, Pd/G e/Ti/P t, Pd/AuG e/Ag/Au, Si/Pd,

In/Pd, etc to n-GaAs have low contact resistiv ities o f ~10‘ 6 Q-cm2 and are good

31

alternatives to the AuG eN i m etallization B ut the ir therm al and long-term stabilities at and above 400 °C s till require further studies

• High-temperature (refractory) contacts have both therm al stab ility and low pc However, other properties such as therm al expansion coefficients compared to GaAs and adhesion to GaAs should be investigated

• R T A is an excellent means o f lim itin g interfacia l reactions and has distinct advantages over conventional a lloying procedures

• Several techniques such as the use o f capping layers, d iffus ion barriers and GaAs surface treatments, have been used extensively to reduce pc

The advantages o f high-speed GaAs devices can on ly be exploited i f adequate and reliab le Ohmic contacts are available For th is reason, efforts should be directed towards the fabrication o f new therm ally stable Ohmic contacts to n-GaAs More fundamental interface studies o f the interactions between metals and GaAs, along w ith the ir long-term re lia b ility , are necessary M oreover, further investigations are required to optim ize various m etallizations fo r the fabrication o f high-speed, sub-|am size GaAs devices fo r both present and future requirements

1.6 Organisation of This Thesis

This thesis is organised into nine chapters The theoretical background and research survey related to Ohmic contacts to n-GaAs have been described in this introductory chapter

• Chapter 2 presents the objectives o f th is research and b rie f highlights o f the characterization techniques to be employed

• Chapter 3 presents the optim isation o f Pd and Sn evaporation rates fo r better surface m orphology o f Pd/Sn contacts on GaAs(SI) using Scanning Tunneling M icroscopy (S TM )

• Chacter 4 introduces the conventional Transm ission L ine M odel (cTLM ) method employed to determine the pc o f the contacts on n-GaAs Th is chapter also presents the effects o f m etallization thickness on the characteristics o f Pd/Sn Ohmic contacts to n-GaAs

32

• Chapter 5 describes the effects o f a A u overlayers on the characteristics o f Pd/SnOhmic contacts A comparative study o f non-alloyed Pd/Sn and Pd/Sn/Au andalloyed A u/G e/A u/N i/A u Ohmic contacts w ill also be presented in th is chapter

• Chapter 6 compares the electncal and morphological characteristics o f non-alloyed Pd/Ge and alloyed A u-G e/N i Ohmic contacts w ith those o f non-alloyed Pd/Sn and Pd/Sn/Au m etallizations

• Chapter 7 presents a study o f the therm al stab ility o f the contacts at temperatures o f300 °C and 410 °C Long-term stab ility o f the contacts is earned out fo r 400 h at300 °C

• Chapter 8 examines the characteristics o f G aAs-M ESFETs fabricated using Pd/Sn, Pd/Ge and Pd/Sn/Au Ohmic contacts

• Chapter 9 presents the conclusions o f this research and offers suggestions fo r further study

33

CHAPTER 2

Objectives of this research

2.1 Introduction

Because Ohmic contacts are so important to GaAs devices (section 1.1), substantial experimental e ffo rt has been directed toward developing practical m etallization and processing procedures. O f a ll the m etallizations investigated, none has proven superior to Au-Ge based systems fo r contacting n-GaAs. However, as device dimensions have shrunk into the sub-(im and even toward the nanometre regime, the shortcomings o f A u- Ge based Ohmic m etallization have become serious. These deficiencies are:

• High contact resistivity pc. A typical Au-Ge pc«10 '6 Q-cm2 produces a 5Q contact resistance to a 10 (am diameter diode but a 50KQ contact resistance to a 100 nm diameter diode. Contact resistance [147] in modem GaAs FETs may comprise at least h a lf the to ta l parasitic source resistance and noise figures are particularly sensitive to such resistances. Parasitic resistance is lik e ly to be the lim ita tio n in high frequency exp loitation o f vertical transport devices.

• Poor morphology. During annealing the typical AuG eN i eutectic m ix is in the liqu id phase which can result in balling-up and surface roughness or patchiness.

• Thermal instability. The Au-Ge system is not therm ally stable [118-121], due to the form ation low m elting point (-375 °C) 0-AuG a phase [104], so cannot be used fo r high temperature applications or be subjected to subsequent high temperature (400 °C) processing steps.

• Metal diffusion. The alloying steps necessary to contact form ation results in the component metals, particularly Au, m oving both ve rtica lly and latera lly in to the underlying semiconductor over distances that can be several thousand Angstroms. Th is necessitates the growth o f th ick contact layers on epitaxial structures and imposes a low er lim it on lateral separation. Furtherm ore, metal m igration during device operation compromises device re lia b ility causing shorts and other failure modes.

To overcome the aforementioned disadvantages o f Au-G e based contact systems, nonalloyed Pd/Ge contacts have been developed [38,148]. Nonalloyed Pd/Ge

34

contacts have low pc in the range o f ~10‘ 6 Q-cm2 [22,39,148]. Pd/Ge contacts are also very shallow in nature and therefore can be used fo r GaAs based heterojunction devices [148-150],

One o f the most im portant criteria fo r an Ohmic contact is its therm al stab ility. A lthough a suitable A u d iffusion barrier is used to improve the therm al stab ility o f Pd/Ge contacts (section 1.3.1), thermal stab ility o f this contact system at and above 400 °C s till requires further study [31,148,151],

2.2 Objectives

Pd/Ge Ohmic contacts are extensively used to fabricate GaAs devices. To our knowledge, Pd/Sn Ohmic contacts to n-GaAs have yet to be developed. N i-S n based alloyed Ohmic contacts are reported [102,115], but the ir contact resistiv ities are very high and surface m orphology is poor. A lthough both Ge and Sn are shallow amphoteric dopants in GaAs and are 0.006 eV from the edge o f the conduction band, Sn has a distinct advantage over Ge. Sn is a less-compensated amphoteric dopant compared to Ge [152] which results higher net doping concentration and thus lowers pc values. A lthough little w ork has been carried out on the Pd/Sn m etalliza tion system [153], there is enough in form ation to suggest that this system could w ithstand the elevated temperatures associated w ith modem GaAs device processing.

Anticipating the above facts, a novel potentia lly non-alloyed Pd/Sn Ohmic contact system is fabricated on n-GaAs. The objectives o f the present research are:

1) to undertake the development o f a new contact to n-GaAs comprising a Pd/Sn m ix undergoing a solid-phase reaction. The successful com pletion o f th is undertaking would place the users at the forefront o f a whole new contact technology fo r the m icrowave and optoelectronic industries.

2) the design, fabrication, testing and m odelling o f the contact having target properties o f

contact res is tiv ity pc<10'6 Q-cm2 <=> therm al stab ility up to 410 °C ^ smooth m orphology on a sub-(am scale

abruptness i.e. having a vertical and lateral penetration o f metal in the semiconductor o f <50 nm.

35

In addition, the effects o f a A u overlayer on the properties o f Pd/Sn contacts 1 e the properties o f Pd/Sn/Au contacts w ill also be investigated A comparative study among the characteristics o f Pd/Sn, Pd/Sn/Au, Pd/Ge and conventional A u-G e/N i contacts w ill be performed F in a lly , G aAs-M ESFETs w ill be fabricated u tiliz in g Pd/Sn, Pd/Ge and Pd/Sn/Au Ohmic contacts

2.3 Characterization of the Contacts

The m eta lliza tion w ould be deposited by therm al (resistance heating) evaporation (Appendix A ) onto n-GaAs bulk and epitaxial wafers patterned w ith test structures by photolithography L if t-o ff techniques w ill produce the required metal test structures w hich w ill then undergo the annealing steps by conventional graphite strip annealer (Appendix B ) and rapid therm al annealer (R T A ) Experim ental design principles w ill be applied in the optim isation o f metal component relative proportions, order o f deposition, thicknesses and annealing conditions A furnace w ill be employed to characterize the long-term therm al stab ility o f the contacts

In addition, the characterization o f the contact and evaluation o f the contact structure and chem istry w ill be undertaken by

■=> Current-Voltage (I-V ) measurements to examine conversion from Schottky to Ohmic behaviour o f the contacts

^ Transm ission L ine M odel (T L M ) to determine the contact re s is tiv ity pc ^ Scanning Tunneling M icroscopy (S TM ) to study surface m orphology ^ Tencor surface p rofilom etry measurements to determine surface roughness ^ Scanning Electron M icroscopy (SEM ) to study surface m orphology ■=> Energy Dispersive Analysis o f X-rays (E D A X ) to study phase form ation before and

after annealing the contacts ■=> Secondary Ion Mass Spectrometry (S IM S ) to evaluate the phase and component

chem istry o f the contacts and movement o f the metals in to the substrate

36

CHAPTER 3

Optimization of Pd and Sn evaporation rates for better surface morphology of the

Pd/Sn contacts

3.1 Introduction

C onventionally alloyed Au-G e/N i is the most common Ohmic contact m aterial regime fo r n-GaAs [38,72,73,78] A fte r a lloying , th is contact system gives very rough surface m orphology which is detrim ental fo r V L S I GaAs devices Once Ohmic contact is formed, a second m etallization (e g T iA u ) fo r bonding is required to connect the Ohmic contact to the outside environm ent I f the surface m orphology o f the contacts is very bumpy or rough, it is d iffic u lt to define a sm all area bonding pad, which imposes geometrical constraints on V L S I GaAs devices Rough surface m orphology Ohmic contacts may also be o f a spiking nature Spiking contacts cannot be used fo r GaAs based heterojunction devices One o f the most im portant reasons fo r the development o f non-alloyed Pd/Ge Ohmic contacts [22,53,148] is to overcome the rough surface m orphology o f conventional alloyed Au-G e/N i contacts Since Pd/Ge contacts are nonalloyed, they show better surface morphology and a non-spiking nature which can be used fo r GaAs based V L S I devices [31,53,149,154]

In th is chapter, a non-alloyed contact system comprising o f Pd/Sn m etallization is fabricated on GaAs Considering the aforementioned importance o f the surface m orphology o f an Ohmic contact, the m orphology o f the proposed m etallization is optim ized using Scanning Tunneling M icroscopy (S TM ) fo r various evaporation rates o f Pd and Sn The effect o f Sn to Pd thickness ratio (m) is investigated fo r both as- deposited and annealed contacts M etallizations are deposited using a resistance heating evaporator (Appendix A ) and annealing is earned out in a conventional graphite strip annealer (Appendix B )

37

3.2 Experiments

Undoped sem i-insulating (S I) GaAs substrates o f (001) surface orientation were sequentially cleaned in trichloroethylene, acetone, methanol and de-ionized (D I) water each fo r 10 m in. The substrates were blow-dried im m ediately using dry N 2. P rio r to loading into an evaporator, the substrates were soaked in a solution o f D I H20:HC1 (15:1 by volum e) fo r at least 2 m in and then blow dried to remove native oxides. Samples (GaAs/Pd/Sn structures) listed in TABLE V were prepared by sequential deposition o f Pd and Sn in a resistance heating evaporator w ithout breaking vacuum. The base pressure was ~ 4 x l0 ‘7 To rr and pressure during evaporation was - lx lO "6 Torr. Samples A to J were then annealed in a conventional graphite strip annealer w ith a flow ing form ing gas (5% H2 + 95% N 2) ambient at 200-400 °C fo r 5 or 10 m in. Surface m orphology o f samples A to J was investigated using STM .

TABLE V . Summary o f GaAs/Pd/Sn samples used in STM .

Sample Pd evaporation rate (A /s)

Sn evaporation rate (A /s)

Contact structures Value o f m

A 5 5 G aAs/Pd(466A)/Sn(2726A) 5B 5 8 G aAs/Pd(530A)/Sn(2694A) 5C 5 10 G aAs/Pd(638A)/Sn(2734A) 5D 5 12 G aAs/Pd(532A)/Sn(2646A) 5E 5 5 GaAs/Pd(5 3 2A )/Sn( 1924A ) 3F 5 8 GaAs/Pd(624A)/Sn( 1640A ) 3G 5 10 G aAs/Pd(570A)/Sn( 1688A) 3H 5 12 G aAs/Pd(568A)/Sn( 1796A) 3I 8 10 G aAs/Pd(540A)/Sn( 1862A ) 3J 7 15 G aAs/Pd(588A)/Sn(2800A) 5

3.3 Results

A surface area o f 60000Ax60000A was scanned using STM . T a b l e V I summarizes the surface m orphology o f samples A to J before and after annealing at 200 °C fo r 10 m in. In the as-deposited state, samples A , E and G exhib it smooth surface morphology compared to other samples. A fte r annealing at 200 °C fo r 10 m in, a ll samples, except sample H show rough surface morphology. Further annealing o f samples B, C, D, F, G,

38

I and J at temperatures above 200 °C result m a very rough surface Therefore, surface roughness o f samples A , E, and H was further investigated Fig 3 1 shows the standard deviation o f surface roughness (SDSR) o f m etallizations as a function o f Sn evaporation rate fo r the as-deposited condition w ith m=3 and m=5 From F ig 3 1, it is clear that fo r better surface morphology in the as-deposited state the evaporation rates o f both Pd and Sn should be around 5 A /s It is also noted that m=3 gives better surface morphology under these conditions The STM photographs o f samples A , E, G and H before and after annealing at 200 °C fo r 10 m in are shown in F ig 3 2 and Fig 3 3 The results, summarized in T a b l e V I, are also confirmed from these photographs

TABLE V I Summary o f surface morphology before and after annealing at 200 °C fo r 10 mm

Sample Pdevaporation rate (A /s)

Snevaporation rate (A /s)

Value o f m

Surface condition before annealing

Surface condition after annealing

A 5 5 5 Smooth WorseB 5 8 5 Rough WorseC 5 10 5 Rough WorseD 5 12 5 Rough WorseE 5 5 3 Smooth W orseF 5 8 3 Rough WorseG 5 10 3 Smooth WorseH 5 12 3 Rough BetterI 8 10 3 Rough WorseJ 7 15 5 Rough Worse

3000

2500

°< 2000 £g 1500 co

1000

5003 7 11 15

Sn evaporation rate (A/s)

Fig 3 1 Standard deviation o f surface roughness (SD SR) as a function o f Sn evaporation rate o f samples A , B, C, D, E, F, G and H under as-deposited condition, Pd evaporation rate being constant at 5 A /s Data points are connected fo r visual aid

39

0 60000A

Sample A (as-deposited)

o 60000A

Sample A (200 °C, 10 min)

Fig 3 2 S TM photographs o f samples A and E under both as-deposited and annealed (at 200 °C fo r 10 mm) conditions O rig inal photographs are given m Appendix C

40

0 60000A

Sample G (as-deposited)

0 60000A

Sample G (200 °C, 10 mm)

Fig 3 3 STM photographs o f samples G and H under both as-deposited and annealed (at 200 °C fo r 10 mm) conditions O rig inal photographs are given in Appendix C

The SDSR o f samples A , E and H as a function o f various annealing temperatures is shown in F ig 3 4 Annealing tim e is 10 mm fo r a ll temperatures except at 300 °C where annealing tim e is 5 mm Both samples E and H have m=3, but sample E shows better surface morphology than that o f sample H at alm ost a ll annealing temperatures investigated (F ig 3 4(a)) The SDSR o f samples A and E is shown in Fig 3 4(b) For annealing temperatures above 300 °C, a ll samples give better surface m orphology (F ig 3 4(a) and Fig 3 4(b)) Th is behaviour is significant because O hm icity o f Pd/Sn m etalliza tion is expected to occur at and above 300 °C In th is region, sample A (w ith m=5) exhib its better surface morphology than that o f sample E (F ig 3 4(b))

41

3000

150 200 250 300 350 400 450 Annealing temperature (°C)

(a)

150 200 250 300 350 400 450 Annealing temperature (°C)

(b)F ig 3 4 Standard deviation o f surface roughness (SD SR) as a function o f annealing temperature o f (a) samples E and H, (b) samples A and E Data points are connected fo r visual aid

Fig 3 5 shows the STM results fo r samples E and H after annealing at temperatures o f 350 °C and 400 °C fo r 10 mm A t 350 °C, both samples show almost identical surface m orphology A fte r annealing at 400 °C, the surface morphology o f sample E deteriorates when compared to that o f sample H Fig 3 4(a) also confirms these results A t these temperatures, the STM photographs o f sample A are shown in F ig 3 6 Sample A shows a s lig h tly deteriorated surface m orphology at 400 °C compared to that at 350 °C However, at these temperatures, sample A shows the best surface m orphology among a ll o f the samples investigated These results are also confirm ed from Fig 3 4(b)

42

0 60000A

Sample E (350 °C, 10 mm)

0 60000A

Sample E (400 °C, 10 mm)

Sample H (350 °C, 10 mm) Sample H (400 °C, 10 mm)

Fig 3 5 STM photographs o f samples E and H annealed fo r 10 mm at temperatures o f 350 °C and 400 °C O rig inal photographs are given in Appendix C

43

0 60000Â

Sample A (350 °C, 10 mm)

0 60000Â

Sample A (400 °C, 10 min)

Fig 3 6 S TM photographs o f sample A annealed fo r 10 mm at temperatures o f 350 °C and 400 °C O rig inal Photographs are given in Appendix C

3.4 Summary

Surface m orphology o f the Pd/Sn contacts on G aAs(SI) has been optim ised fo r various evaporation rates o f Pd and Sn u tiliz in g STM The effects o f Sn to Pd thickness ratio (m ) on the morphological characteristics o f Pd/Sn contacts are also presented From the results, the fo llow ing conclusions can be drawn

• Evaporation rates o f both Pd and Sn should be around 5 Â /s fo r better surface m orphology

• For the in itia l evaporation, m=3 gives best results under alm ost a ll evaporation rates investigated

• For annealing temperatures, T an>300 °C the surface m orphology o f the contacts improves

• Sample A w ith a contact structure o f G aAs/Pd(466Â)/Sn(2726Â) shows the best surface m orphology among a ll o f the contacts investigated at ^ > 3 0 0 °C

44

CHAPTER 4

Pd/Sn Ohmic contacts to n-GaAs

4.1 Introduction

A n Ohmic contact system comprising o f Pd/Sn m eta lliza tion has been developed fo r n-GaAs fo r the firs t tim e [155-157] M etallizations are deposited using a resistance heating evaporator and annealing is carried out in a conventional graphite strip annealer M eta lliza tion thickness and annealing cycles are optim ized to reduce pc values The effects o f layering sequencing on the O hm icity o f the Pd/Sn contact are reported The effects o f two-step annealing on the characteristics o f Pd/Sn contacts are also investigated

Pd/Sn contacts are system atically characterized using Surface P rofilom etry measurements, Scanning Electron M icroscopy (SEM ), Energy D ispersive Analysis o f X-rays (E D A X ), Secondary Ion Mass Spectrometry (S IM S ) and current-voltage (I-V ) measurements Surface P ro filom etry measurements and SEM are u tilized to investigate surface m orphology o f the contacts Conversion from Schottky to Ohmic behaviour o f the contacts is confirm ed by I-V measurements Contact resistiv ities, pc, o f the proposed m etallizations are measured using the conventional Transm ission L ine M odel (cTLM ) method w hich w ill be described in Section 4 2 E D A X is used to determine the various signal peaks o f the contacts at d ifferent annealing temperatures These signal peaks w ill be correlated w ith the measured pc values Contact depth profiles are analyzed by SIM S The form ation o f various compounds at d ifferent annealing temperatures w ill be determined by mass spectrometer analysis

4.2 Conventional TLM (cTLM) Method

The T L M pattern used fo r the contact resistance measurements is shown in Fig 4 1 The tota l resistance between tw o adjacent Ohmic pads o f w id th W separated by a distance L

is given byR7 = 2 R + ^ - L + Rn (4 1 )' c ¡ y p v '

45

where Rsh2 is the sheet resistance o f the active layer between the contacts (i.e., the film resistance per square), Rc is the contact resistance and Rp is the resistance o f the interconnect wires. I f R=RT- RP then equation (4.1) may be w ritten as

ß _ 2 R Sh \ L T R sh2 ^

W W(4.2)

L Ohmic contact

active layer

SUBSTRATE

F ig .4 .1. T L M pattern. Three or more Ohmic contacts w ith d ifferent distances between adjacent contacts are used in T L M measurement.

where Rshi is the sheet resistance o f the active layer under the contacts and LT is the transfer length [12], Fo r the non-alloyed contact it is assumed that RShi=RSh2■ For the alloyed contact, RShi*Rsh2-

Fig .4.2. P lo t o f measured resistance as a function o f contact separation yields sheet resistance, contact resistance and other parameters.

Assuming that sheet resistance is constant, a p lot o f R as a function o f L w ill yield a straight line, as shown in Fig .4.2. The slope o f the line gives the value RShi/W and the intercept w ith the R axis gives the value 2Rc. The intercept w ith the L axis, -Lx, is related to the transfer length, Lf.

_ 2R W __ 2RM LT (4.3).V

Thus the ¿-axis intercept would give the value o f LT i f Rshi=Rsh2=Rsh- Equation (4.1) gives unequivocal answers fo r Rsh2 and Rc; these are the experimentally determined variables. Additional data is needed to accurately determine the quantities pc, RM or Lr.

Technically, the end resistance measurement [10] can supply the necessary inform ation i f the length, Lc, o f the contact is known. The end resistance measurement is useful on ly i f Lc is not greatly larger than LT. U sually, Lc» L r, so that Rc is independent o f Lc.

Under these circumstances the area WLC does not have much significance, but W its e lf s till does, o f course. The effective area o f the contact is WLr and the contact resistiv ity is given by

Pc = WLtRc = RshL r 2. (4.4)

4.3 Experiments18 3Contacts were fabricated on a Si-doped (2x10 c m ") n-GaAs epitaxial layer grown by

metal-organic vapor phase epitaxy (M O V P E ) in a metal-semiconductor fie ld -effect transistor (M E S FE T) structure. The starting m aterial fo r th is M E S FE T structure was sem i-insulating (S I) GaAs substrate o f (100) surface orientation. The epitaxial structure consists o f the fo llow ing layers: a 50 nm A lA s undoped barrier layer, a 2500 nm GaAs undoped channel layer, a 200 nm n-GaAs (5 x l0 17 cm’3) layer fo r recessed gate m etallization, and a 100 nm n-GaAs (2 x l0 18 cm'3) layer fo r Ohmic contacts (Fig.4.3). The top 100 nm GaAs heavily doped layer is used to reduce contact re s is tiv ity and the 50 nm A lA s barrier layer is used to confine electrons in the channel layer.

100 nm n-GaAs (2x1018 cm '3)

200 nm n-GaAs (5x1017 cm '3)

2500 nm GaAs (undoped)

50 nm AlAs (undoped)

GaAs(SI) substrate

Fig.4.3. Schematic diagram o f the GaAs M E S FE T substrate.

The GaAs substrates were sequentially cleaned and degreased in trichloroethylene, acetone, methanol and de-ionized water (D I H 20 ), each fo r 10 m in. The substrates were blow-dried im m ediately using dry nitrogen (N 2). Ohmic test, m orphology and T L M patterns were defined by standard photolithography and lif t -o ff processes. A solution o f H 20 2:NH40 H :D I H20 (1:3:15 by volum e) was used as an etchant fo r mesa defin ition .

47

P rio r to loading into an evaporator, the wafers were soaked in a solution o f D I H20:HC1 (15:1 by volum e) fo r at least 2 m in and then b low dried using dry N 2 to remove native oxides. The n-GaAs/Pd(30 nm )/Sn(90 nm ), n-GaAs/Pd(30 nm)/Sn(150 nm), n-GaAs/Pd(40 nm )/Sn(120 nm) and n-GaAs/Pd(50 nm)/Sn(125 nm ) samples were prepared by a sequential deposition o f Pd and Sn in a resistance heating evaporator w ithout breaking vacuum. In addition, n-GaAs/Sn(25 nm)/Pd(25 nm) and n-GaAs/Pd(25 nm)/Sn(25 nm) samples were prepared in order to investigate the effect o f the layering sequence on Ohmic behaviour. The base pressure was -4x10 " T o rr and pressure during evaporation was between 1.5x10"6 T o rr and 3.5x1 O'6 Torr.

A ll samples were then annealed by a conventional graphite strip annealer in a flow ing form ing gas (5% H 2 + 95% N 2) ambient. The n-GaAs/Pd(30 nm )/Sn(90 nm) and n-GaAs/Pd(30 nm)/Sn(150 nm) contacts are annealed in the temperature range o f 300-400 °C fo r 30 m in, whereas the n-GaAs/Pd(40 nm )/Sn(120 nm) and n-GaAs/Pd(50 nm)/Sn(125 nm ) contacts are annealed in the temperature ranges o f 330-400 °C fo r 30 m in and 360-425 °C fo r 30 m in, respectively. The n-GaAs/Pd(25 nm)/Sn(25 nm) contact is annealed at 390 C fo r 20 m in, whereas the n-GaAs/Sn(25 nm)/Pd(25 nm) contact is annealed at 400 °C fo r 5 m in. For two-step annealing, the samples were firs t annealed in a rapid therm al annealer (R TA ), and then in a conventional graphite strip annealer under the same ambient condition.

Surface m orphology o f the contacts was investigated using a Tencor Instruments Surface Profilom eter and a H itachi S-4000 FESEM (FE M ). A Cameca IM S 3 f SIM S intrum ent using an 0 2+ prim ary ion beam w ith an impact energy o f 12.5 keV was used in depth p ro filing studies. Conversion from Schottky to Ohmic behaviour o f the contacts was examined by I-V measurements. Contact re s is tiv ity was measured u tiliz ing the cTLM method.

4.4 Results and Discussions

4.4.1 Electrical characteristics

The pc o f the Pd/Sn Ohmic contacts are measured in a test pattern conform ing to the T L M (F ig .4.1), w ith the pad spacing ranging from 2 to 128 (am. The w id th o f the Ohmic pad, W, is 140 nm. The transfer length method [12] is u tilized to measure pc values o f the contacts. It is assumed that the sheet resistance o f the semiconductor under the contacts, Rshj, is equal to the sheet resistance o f the semiconductor between the contacts,

48

R m Fig 4 4 shows the measured average contact resistivity vs annealing temperature

curves for 4 TLM patterns The measured current-voltage curves show rectifying

behaviour when the annealing temperature is <300 °C The Pd(30 nm)/Sn(150 nm) contact shows a lowest pc o f 3 26x10-5 Q-cm2 after annealing at 360 °C for 30 mm,

whereas the Pd(30 nm)/Sn(90 nm) contact shows a lowest pc of 6 05x1 O'5 Q-cm2 for

the same annealing condition However, both Pd(40 nm)/Sn(120 nm) and Pd(50

nm)/Sn(125 nm) contacts exhibit a lowest pc of 2 3 8x10'5 Q-cm2 and 2 07x10‘5 Q-cm2,

respectively after annealing at 400 °C for 30 mm Thus, metallization thickness has a

significant effect on annealing cycles for the Pd/Sn contacts It is also clear that excess Sn does not lower the pc values significantly Measurement errors, Apc, of the Pd/Sn

Ohmic contacts at the lowest pc points are shown in TABLE VII The Pd(50 nm)/Sn(125

nm) Ohmic contact appears to have excellent reproducibility with a Apc of ±0 92x1 O'3 Q-cm among all metallizations investigated

E01G

5>(0V)aL _

4 -1o<0coo

Annealing temperature (°C)

Fig 4 4 Contact resistivity vs annealing temperature curves o f the Pd/Sn contacts to n-GaAs All contacts are annealed for 30 min

TABLE VII Summary of contact resistivity, p c, and measurement error, A p c, of the Pd/Sn Ohmic contacts to n-GaAs

Contact structure Annealing condition pc (Q-cm2) Apc (Q-cm2)

Pd(30 nm)/Sn(150 nm) 360 °C, 30 mm 3 26x10'5 ±2 50x10’5Pd(30 nm)/Sn(90 nm) 360 °C, 30 mm 6 05xl0‘5 ±1 63x10’5Pd(40 nm)/Sn(120 nm) 400 °C, 30 mm 2 38xl0'5 ±1 25x10’5Pd(50 nm)/Sn(125 nm) 400 °C, 30 mm 2 07x10'5 ±0 92x10'5

49

TABLE VIII Summary of calculated sheet resistance, R sh, and transfer length, L r ,

parameters o f the Pd(30 nm)/Sn(150 nm) contact to n-GaAs under vanous annealing temperatures

Annealing condition R sh (« /□ ) L r ( jam)

300 °C, 30 min 191 49 54 91

330 °C, 30 mm 192 80 29 18

360 °C, 30 mm 165 00 04 45

400 °C, 30 mm 288 08 05 53

T a b l e VIII summarizes the calculated sheet resistance, R sh and transfer length,

L t , parameters o f the Pd(30 nm)/Sn(150 nm) contact under different annealing

temperatures Both R sh and L T decrease up to an annealing temperature o f 360 °C where

the minimum pc value occurs Above 360 °C, both R sh and L T tend to increase At 360

°C, L T is 4 45 p.m which is much lower than the length o f contact, L c (100 jam) This

validates the application o f the transfer length method for the Pd/Sn contacts

4.4.2 Surface profilometry measurements

Surface profiles o f the Pd(30 nm)/Sn(150 nm) contacts under both as-deposited and

lowest pc conditions are shown m Fig 4 5 In the as-deposited condition, the maximum

peak-to-valley distance, TIR, o f the scanned surface is 30 nm and the average surface

roughness, Ra, is 5 nm (Fig 4 5(a)) At the lowest pc condition (360 °C, 30 min), these

values are 90 nm and 15 nm, respectively (Fig 4 5(b)) TABLE IX summarizes the

surface profiles of all Pd/Sn contacts under both as-deposited and at the lowest pc

conditions In the as-deposited state, the Pd(30 nm)/Sn(90 nm) contact shows a TIR of

30 nm and a Ra of 5 nm For the Pd(40 nm)/Sn(120 nm) contact, these values are 45 nm and 5 nm, respectively The Pd(50 nm)/Sn(125 nm) contact shows better surface profiles under as-deposited condition with a TIR of 24 5 nm and a Ra o f 3 5 nm

At the lowest pc point, the Pd(30 nm)/Sn(90 nm) contact displays a TIR of 10

nm and a Ra of 0 nm, whereas for the Pd(40 nm)/Sn(120 nm) contact these values are

60 nm and 10 nm, respectively The Pd(50 nm)/Sn(125 nm) contact shows a TIR of 33

nm and a Ra o f 5 nm at the lowest pc condition (400 °C, 30 mm) Therefore, the Pd(30

nm)/Sn(90 nm) contact exhibits best surface profiles among all the contacts investigated at the lowest pc conditions

50

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Fig.4.5. Surface profiles o f the Pd(30 nm )/Sn(150 nm ) contact to n-GaAs: (a) as- deposited and (b) annealed at 360 °C, 30 m in.

T A B L E IX . Summary o f surface profiles o f the Pd/Sn contacts to n-GaAs under both as- deposited and lowest pc conditions.

Contact structure Annealing condition T IR (nm) Ra (nm)

Pd(30 nm )/Sn(150 nm) as-deposited 30.0 5.0Pd(30 nm )/Sn(150 nm) 360 °C, 30 m in 90.0 15.0Pd(30 nm )/Sn(90 nm) as-deposited 30.0 5.0Pd(30 nm )/Sn(90 nm) 360 °C, 30 m in 10.0 0.0Pd(40 nm )/Sn(120 nm) as-deposited 45.0 5.0Pd(40 nm )/Sn(120 nm) 400 °C. 30 m in 60.0 10.0Pd(50 nm)/Sn(125 nm) as-deposited 24.5 3.5Pd(50 nm)/Sn(125 nm) 400 °C, 30 m in 33.0 5.0

51

4.4.3 Surface morphology using SEM

SEM micrographs o f the Pd(30 nm )/Sn(150 nm ) and Pd(30 nm )/Sn(90 nm) contacts under both as-deposited and lowest pc conditions are shown in Fig.4.6. M icro-crystals o f the order o f -1 .0 jam in diameter are observed on the surface w ith the Pd(30 nm )/Sn(150 nm) contacts under both as-deposited (F ig .4.6(a)) and at the lowest pc (Fig .4.6(b)) conditions. However, m etallizations are more un ifo rm ly distributed at the lowest pc point compared to the as-deposited state. The Pd(30 nm )/Sn(90 nm) contact shows m icro-crystals o f the order o f -0 .5 (im in diameter under the as-deposited state (F ig .4.6(c)). A fte r annealing at 360 °C fo r 30 m in, the size o f these m icro-crystals does not change appreciably (F ig .4.6(d)) but the m etallizations seems to be more un ifo rm ly distributed compared to the as-deposited condition. Therefore, excess Sn appears to have a significant effect on the surface morphology o f the Pd/Sn contacts.

Fig.4.6. SEM micrographs o f the Pd/Sn contacts to n-GaAs: (a) Pd(30 nm )/Sn(150 nm), as-deposited; (b) Pd(30 nm )/Sn(150 nm), 360 °C, 30 m in; (c) Pd(30 nm )/Sn(90 nm), as- deposited and (d) Pd(30 nm )/Sn(90 nm), 360 °C, 30 m in.

52

The size of micro-crystals improves significantly after annealing at the lowest pc

point for both Pd(40 nm)/Sn(120 nm) and Pd(50 nm)/Sn(125 nm) contacts (Fig 4 7) In

the as-deposited state, Pd(40 nm)/Sn(120 nm) and Pd(50 nm)/Sn(125 nm) contacts

show micro-crystals o f the order o f ~1 0 (im and ~0 75 fim diameters, respectively

(Figs 4 7(a) & 4 7(c)) At the lowest pc point, the size of micro-crystals decreases to

~0 5 jim for both contacts (Figs 4 7(b) & 4 7(d)) Thus, excess Pd shows little effect on

the surface morphology of the Pd/Sn contacts

(a) (b)

N M R C 0 1 1 0 - 0 k V X 1 5 . Ó k ‘ ‘ a 0 0 V m N M R C 0 1 I 0 . O k v X 1 5 . 8 K 2 . ’ 0 0 » ' m

Fig 4 7 SEM micrographs of the Pd/Sn contacts on n-GaAs (a) Pd(40 nm)/Sn(120 nm), as-deposited, (b) Pd(40 nm)/Sn(120 nm), 400 °C, 30 mm, (c) Pd(50 nm)/Sn(125 nm), as-deposited and (d) Pd(50 nm)/Sn(125 nm), 400 °C, 30 mm

It is postulated that the Ohmic contact formation mechanism of the Pd/Sn

metallization to n-GaAs is similar to that which occurs in the Pd/Ge metallization

(Fig 1 5), with Sn taking the place of Ge and is shown schematically in Fig 4 8 In

Pd/Sn metallization, Sn dopes n-GaAs at temperatures T>300 °C (Fig 4 8) and

consequently a low resistance Ohmic contact is obtained At the lowest pc point, all of

the Pd could react to form the compound PdSn which is comparable to PdGe formation

53

for the Pd/Ge metallization scheme annealed at 325 °C for 30 min [18] This layer is at

the sample surface It is believed that excess Sn is now transported through the PdSn

layer to dope the n-GaAs to form n+-GaAs layer resulting m the lowering of pc values

-100 °C -3 0 0 °C >300 °C

Sn Sn Sn PdSn

Pd Pd PdSn Sn

GaAs

------ ►Pd4GaAs

------ ►n+-GaAs (Sn) n+-GaAs (Sn)

GaAs GaAs GaAs

Fig 4 8 Schematic representation of regrowth mechanisms using the Pd/Sn metallization to n-GaAs (postulated)

4.4.4 Contact depth profiles using SIMS

SIMS depth profiling shows how metallizations penetrate into the underlying GaAs

Due to the 'knock-on' effect of the primary 0 2+ ion on the contact constituent elements,

it is difficult to determine the exact penetration depths of metals into the underlying

GaAs using SIMS In the as-deposited sample, knock-on produces “metal tails”

Preferential knock-on of species is not responsible for the shape changes of profiles, rather they reflect genuine diffusion Therefore, the best approach is to compare shapes

(e g peaks) and look for relative changes between profiles

The SIMS depth profiles o f Pd(30 nm)/Sn(150 nm) and Pd(30 nm)/Sn(90 nm) contacts at the lowest pc point are shown in Fig 4 9 and Fig 4 10, respectively The

depth profiles for Pd and Sn of the former contact (Fig 4 9) have lower slopes than those

of the latter contact (Fig 4 10) However, the Ga and As profiles are identical for both contacts Therefore, a Pd(30 nm)/Sn(90 nm) contact is more abrupt than that o f a Pd(30 nm)/Sn(150 nm) contact

54

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Fig 4 10 SIM S depth profiles o f the Pd(30 nm )/Sn(90 nm ) contact annealed at 360 °C, 30 m in

SIM S depth profiles o f the Pd(40 nm )/Sn(120 nm ) contact under both as- deposited and lowest pc (400 °C, 30 m in) conditions are shown in F ig 4 11 and Fig 4 12, respectively The metal/GaAs interface is w e ll defined in the as-deposited state (F ig 4 11) A fte r annealing at 400 °C fo r 30 mm, Ga and As profiles remain almost identical as those in as-deposited state, although slight ou td iffusion o f Ga and As is observed at this temperature (F ig 4 12) The slopes o f Pd and Sn profiles decrease

56

significantly after annealing The w idths o f both Pd and Sn profiles are almost doubled at the lowest pc point (F ig 4 12) compared to the as-deposited state (F ig 4 11) indicating significant metal penetration in to the underlying GaAs substrate However, the exact penetration depth can not be determined due to the ‘knock-on’ effect as described earlier

m

e3©

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Fig 4 11 S IM S depth profiles o f the Pd(40 nm )/Sn(120 nm ) contact under as-deposited condition

57

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Fig 4 12 SIMS depth profiles o f the Pd(40 nm)/Sn(120 nm) contact annealed at 400 C, 30 min

Fig 4 13 shows the SIMS depth profiles o f the Pd(50 nm)/Sn(125 nm) contact

under both as-deposited (Fig 4 13(a)) and annealed at 400 °C for 30 mm (Fig 4 13(b))

conditions Outdiffusions o f Ga and As are observed after annealing at 400 °C for 30

mm The shape o f Pd profile does not change appreciably after annealing However, the

shape of Sn profile changes significantly indicating Sn penetration into underlying

GaAs substrate

58

From the S IM S depth profiles (from Fig 4 9 to F ig 4 13) it is clear that both Pd(40 nm )/Sn(120 nm ) and Pd(50 nm)/Sn(125 nm ) contacts have w ider depth profiles compared to both Pd(30 nm )/Sn(150 nm ) and Pd(30 nm )/Sn(90 nm ) contacts at the lowest pc points This is due to a higher temperature (400 °C) requirement at the lowest pc point fo r both Pd(40 nm )/Sn(120 nm) and Pd(50 nm )/Sn(125 nm ) contacts The Pd(30 nm )/Sn(90 nm) contact shows the most abrupt m etal/GaAs interface among a ll Pd/Sn contacts investigated

Depth (m icron)(a)

Depth (m icron)(b)

F ig 4 13 SIM S depth profiles o f the Pd(50 nm)/Sn(125 nm ) contact (a) as-deposited and (b) annealed at 400 °C, 30 m in

59

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(a)

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150

M ass (a.m .u.)

(b)

Fig.4.14. Mass spectra o f positive secondary ions fo r (a) Pd(30 nm )/Sn(150 nm) and (b) Pd(30 nm )/Sn(90 nm) contacts, both annealed at 360 °C, 30 m in.

4.4.5 Mass spectrometer analysis

Fig .4 .14 shows the mass spectrometer analysis o f positive secondary ions fo r the Pd(30 nm)/Sn(150 nm) and Pd(30 nm )/Sn(90 nm) contacts at the lowest pc point. Positive secondary ions o f Pd+, Sn+, S i+, As+, Ga*, Ga2+, GaO+, SnO+, S n 0 2+, PdGa+, SnGa+ and

60

Pd2+ are monitored in the ion m icroanalyzer fo r both contacts. Mass spectrometer analysis o f the Pd(50 nm)/Sn(125 nm ) contact at the lowest pc point is shown in Fig.4.15. The observed secondary ions are identical to those found w ith both Pd(30 nm )/Sn(150 nm) and Pd(30 nm )/Sn(90 nm ) contacts (Fig .4.14).

Mass (a.m.u.)

Fig.4.15. Mass spectra o f positive secondary ions fo r the Pd(50 nm)/Sn(125 nm) contact annealed at 400 C, 30 m in.

A t the lowest pc point, SnPd+ ions should be m onitored in the m icroanalyzer and they w ill have an atomic mass un it (amu) o f -2 26 . S IM S is not very chem ically sensitive to SnPd+ species and these species w ill be formed in the plasma w ith in the instrument. A t high amu the noise increases and weak signals are unreliable. For this reason, SnPd+ ions are not detected. The detection o f PdSn compound form ation would support the non-alloying behaviour o f the contacts. Since we failed to detect PdSn compound form ation due to S IM S insensitiv ity as described above, the non-alloying behaviour o f the contacts could not be confirmed. However, the detection o f PdGa+ and SnGa+ ions indicates the outd iffusion o f Ga into the m etallization.

61

4.4.6 Correlation between Ga signal and contact behaviour

Fig 4 16 shows the ED AX spectra of the Pd(30 nm)/Sn(150 nm) contacts at various

annealing temperatures TABLE X also summarizes the calculated various signal peaks

from ED AX spectra at different annealing temperatures As the annealing temperature

increases from 300 °C (Fig 4 16(a)) to 360 °C (Fig 4 16(b)), the peak of the Ga signal

also increases This signifies Ga outdiffusion into the metallization and formation of

more Ga vacant sites in n-GaAs The dopant Sn now occupies these Ga vacant sites to

dope the n-GaAs resulting in the formation of epitaxial n+-GaAs and thus lowers pe

values This Ga signal peak is highest at 360 °C which correlates with the lowest pc

value at that temperature The signal peaks of As decreases with increasing annealing

temperature Since annealing is carried out in an open system where As vaporizes

through the metallization into the surrounding atmosphere or to vacuum, the loss o f As

increases with the increase in annealing temperatures The diffusivity and or solubility

of Ga in Pd is greater than that o f As [2] The Pd/Sn metallization serves as a sink for

Ga in much the same way that Au acts as a sink for Ga in Au-Ge based Ohmic contacts

[120,121] The Pd and Sn signal peaks decrease with increasing temperature This type

of behaviour is anticipated since more reactions are expected at increased temperatures

indicating more compound (e g PdGa and SnGa) formation as evidenced by mass

spectrometer analysis (Fig 4 14)

T a b l e X Summary o f calculated signal peaks from EDAX spectra of the Pd(30 nm)/Sn(150 nm) contacts after annealing for 30 mm at different temperatures

Annealingtemperature

Peak counts of Ga (a u )

Peak counts of As (a u )

Peak counts of Pd (a u )

Peak counts of Sn (a u )

300 °C 265 372 620 1389360 °C 354 377 593 1293400 °C 339 320 594 1090

62

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Fig 4 16 EDAX s p e c t r a o f the Pd(30 n m ) / S n ( 1 5 0 nm) contacts a f t e r annealing for 30 min at (a) 300 C, (b) 360 °C and (c) 400 °C

63

4.4.7 Effect of layering sequence

Plots o f the I-V behaviour o f the Pd(25 nm )/Sn(25 nm ) and Sn(25 nm)/Pd(25 nm) m etallizations to n-GaAs are shown in F ig 4 17 The n-GaAs/Pd(25 nm)/Sn(25 nm ) contact shows Ohmic behaviour (constant resistance) after annealing at 390 °C fo r 20 mm (F ig 4 17(a)), whereas the n-GaAs/Sn(25 nm)/Pd(25 nm ) contact shows rectifying behaviour (variable resistance) after annealing at 400 °C fo r 5 mm This result indicates that Pd must be the firs t layer deposited on chem ically cleaned n-GaAs in order to fabncate Ohmic contacts using the Pd/Sn m etalliza tion Th is is consistent w ith the idea that Pd disperses the native oxides from the n-GaAs surface in order that the epitaxial growth o f Sn can occur during the annealing treatment [2]

* x x x h k G R A P H IC S P L O T * * * * * *

oooo50 oo

I I 2 5 0 0 / d i v (mA)

(a)

75 00

Fig 4 17 Graphics plots o f (a) n-GaAs/Pd(25 nm )/Sn(25 nm ) contact annealed at 390 °C fo r 20 m in and (b) n-GaAs/Sn(25 nm )/Pd(25 nm ) contact annealed at 400 °C fo r 5 m in

64

4.4.8 Effects of two-step annealing on the characteristics of Pd/Sn Ohmic contacts

Two-step annealing can improve the overall properties o f Ohmic contacts [71] In order

to investigate the effects o f two-step annealing, the Pd(30 nm)/Sn(150 run) contacts are

first annealed m a RTA and then m a conventional graphite strip annealer TABLE XI

summarizes the measured pc and R sh values under both single-step and two-step5 2annealing conditions A pc o f 3 26x10’ Q-cm is obtained after single-step annealing at

360 °C for 30 mm The same contact shows pc o f 1 49x1 O'5 Q-cm2 and 1 53x1 O’5 Q-cm2

after two-step annealing o f 225 °C, 50 s + 350 °C, 15 mm and 225 °C, 2 mm + 350 °C,

10 mm, respectively After annealing at 200 °C, 2 mm + 400 °C, 15 mm, the Pd(305 2nm)/Sn(150 nm) contact displays a pc of 3 35x10' Q-cm Therefore, two-step

annealing improves the electrical characteristics of the Pd/Sn contacts very slightly In

addition, two-step annealing has almost insignificant effect on R sh

T a b l e XI Summary o f measured contact resistivity, p c, and sheet resistance, R sh, o f the Pd(30 nm)/Sn(150 nm) contacts to n-GaAs under both single-step and two-step annealing conditions

Annealing condition pc (Q-cm2) R sh ( Q d )

360 °C, 30 mm 3 26x10'5 165 00225 °C, 50 s + 350 °C, 15 mm 1 49x10‘5 160 00225 °C, 2 mm + 350 °C, 10 min 1 53xl0'5 159 35200 °C, 2 m m + 400 °C, 15 min 3 3 5x10‘5 133 82

T a b l e XII Summary of surface profiles of the Pd(30 nm)/Sn(150 nm) contacts to n-GaAs under different annealing conditions

Annealing conditions TIR (nm) Ra (nm)

360 °C, 30 mm 90 15225 °C, 5 0 s + 3 5 0 °C, 15 mm 20 0225 °C, 2 mm + 350 °C, 10 min 85 10200 °C, 2 mm + 400 °C, 15 mm 90 15

TABLE XII summarizes the surface profiles o f the Pd(30 nm)/Sn(150 nm)

contacts under both types o f annealing Single-step annealing (360 °C, 30 mm) shows a

maximum peak-to-valley distance of the scanned surface, TIR, of 90 nm and average

65

surface roughness, Ra, o f 15 nm. Two-step annealing conditions exh ib it better surface profiles compared to single-step annealing. Annealing at 225 °C, 50 s + 350 °C, 15 m in shows the best results w ith a T IR o f 20 nm and a Ra o f 0 nm. Therefore, two-step annealing improves the surface profiles o f the Pd/Sn Ohmic contacts significantly.

SEM micrographs o f the Pd(30 nm )/Sn(150nm ) contacts are shown in Fig.4.18. M icro-crystals o f the order o f -1 .0 jam in diameter are observed after annealing at 360 °C fo r 30 m in (Fig.4.18(a)). The size o f m icro-crystals decreases to -0 .75 |am in diameter when annealed at 225 °C, 50 s + 350 °C, 15 m in (Fig .4.18(b)) and 225 °C, 2 m in + 350 °C, 10 m in (Fig.4.18(c)). However, two-step annealing at 200 °C, 2 m in + 400 °C, 15 m in (Fig.4.18(d)) shows m icro-crystals o f the order o f -1 .0 j m in diameter. Surface p rofilom etry measurements (TABLE X II) also reveal these results. Therefore, jud icious choice o f two-step annealing can improve the morphological characteristics o f the Pd/Sn Ohmic contacts.

Fig.4.18. SEM micrographs o f the Pd(30 nm)/Sn(150 nm ) contacts at various annealing conditions: (a) 360 °C, 30 m in; (b) 225 °C, 50 s + 350 °C, 15 m in; (c) 225 °C, 2 m in + 350 °C, 10 m in and (d) 200 °C, 2 m in + 400 °C, 15 m in.

66

Fig 4 19 and Fig 4 20 show the SIMS depth profiles o f the Pd(30 nm)/Sn(150

nm) contact after annealing at 225 °C, 50 s + 350 °C, 15 mm and 225 °C, 2 mm + 350

°C, 10 mm, respectively The depth profiles of Pd and Sn are almost identical to those

found in single-step annealing at 360 °C, 30 mm (Fig 4 9) However, the signal peaks of

Ga and As are higher in single-step annealing (Fig 4 9) than those o f two-step annealing

(Fig 4 19 & Fig 4 20) Therefore, aforementioned two-step annealings do not improve

the abruptness of the Pd(30 nm)/Sn(150 nm) contacts However, two-step annealing at

225 °C, 50 s + 350 °C, 15 mm (Fig 4 19) shows higher slopes o f Pd and Sn profiles

compared to two-step annealing at 225 °C, 2 mm + 350 °C, 10 mm (Fig 4 20) with

almost identical pc values (T a b l e XI)

Depth (nm)

Fig 4 19 SIMS depth profiles o f the Pd(30 nm)/Sn(150 nm) Ohmic contact annealed at 225 °C, 50 s + 350 °C, 15 mm

67

C/3*->cs©

U

ao

s-cs

T3COu<u

cn

Depth (p.m)

Fig.4.20. S IM S depth profiles o f the Pd(30 nm )/Sn(150 nm) Ohmic contact afterannealed at 225 °C, 2 m in + 350 °C, 10 m in.

F ig .4.21 shows the S IM S depth profiles o f the Pd(30 nm )/Sn(150 nm) Ohmic contact annealed at 200 °C, 2 m in + 400 °C, 15 m in. The Pd and Sn profiles are w ider and have low er slopes than those o f single-step annealing at 360 °C, 30 m in (Fig.4.9). However, peak counts o f both Ga and As profiles are identical in both types o f annealing. Thus two-step annealing at 200 °C, 2 m in + 400 °C, 15 m in deteriorates the abruptness o f the contact. Th is is due to higher temperature (400 °C) used in the case o f th is annealing.

68

VIC3©u

ucsnsa©CJ4 iC/3

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Fig 4 21 SIM S depth profiles o f the Pd(30 nm )/Sn(150 nm ) Ohmic contact annealed at 200 °C, 2 m in + 400 °C, 15 m in

4.5 Summary

In summary, a novel Ohmic contact system comprising o f Pd/Sn m etallization has been developed fo r n-GaAs The effects o f m eta lliza tion thickness on the characteristics o f Pd/Sn Ohmic contacts are reported M eta lliza tion thickness shows little effect on the

69

electrical characteristics o f the contacts A lowest pe o f 3 26x10"5 Q-cm2 is obtained fo r18 3a substrate doping o f 2x10 cm' w ith a Pd(30 nm )/Sn(150 nm ) contact after annealing

at 360 °C fo r 30 mm, whereas the Pd(30 nm )/Sn(90 nm ) contact shows a lowest pc o f5 26 05x10' Q-cm at the same annealing condition Thus excess Sn does not low er the pc

values significantly M eta lliza tion thickness has a significant effect on the annealing cycles at the lowest pc points The Pd(40 nm)/Sn(120 nm ) contact produces a lowest pc

o f 2 38x10° Q-cm2 at 400 °C, 30 mm, whereas a lowest pc o f 2 07x10'5 Q-cm2 is obtained w ith the Pd(50 nm)/Sn(125 nm ) contact under the same annealing condition The Pd(50 nm)/Sn(125 nm ) contact exhibits excellent reproducib ility among a ll m etallizations investigated

The Pd(30 nm )/Sn(90 nm ) Ohmic contact appears to have the best surface m orphology and least metal penetration into the underlying GaAs among a ll contacts investigated as evidenced by Surface P rofilom etry measurements, SEM and SIM S Two-step annealing has little effect on the electrical characteristics o f the Pd/Sn Ohmic contacts Two-step annealing at 225 °C, 50 s + 350 °C, 15 m in gives a pc o f 1 49x1 O’5 Q-cm w ith a Pd(30 nm )/Sn(150 nm) Ohmic contact Proper choice o f two-step annealing cycles improves the morphological characteristics o f the contacts However, two-step annealing does not improve the abruptness o f the contacts

The ED A X spectra indicate an increase in Ga out-d iffusion w ith an increase in annealing temperatures This behaviour is correlated w ith the calculated pc values Mass spectrometer analysis indicates the form ation o f PdGa and SnGa compounds at the lowest pc conditions However, the form ation o f PdSn compounds could not be identified due to S IM S insensitiv ity as described in 4 4 5 For th is reason the non- alloym g behaviour o f the contact could not be confirm ed Pd must be the firs t layer deposited on n-GaAs in order to fabricate Ohmic contacts using the Pd/Sn m etallization A ll evidence is consistent w ith a replacement mechanism in which an n+-GaAs surface region is formed when Sn occupies excess Ga vacant sites resulting in higher tunneling probability and low er pc values

70

CHAPTER 5

Effects of Au overlayers on the characteristics of Pd/Sn Ohmic

contacts to n-GaAs

5.1 Introduction

The effects o f A u overlayers on the characteristics o f non-alloyed Pd/Sn Ohmic contacts have been studied M etallizations are deposited using a resistance heating evaporator and annealing is carried out in a conventional graphite strip annealer Surface m orphology o f the contacts is investigated using Surface P ro filom etry measurements and Scanning Electron M icroscopy (SEM ) The contact depth profiles are analyzed by Secondary Ion Mass Spectrometry (S IM S) Conversion from Schottky to Ohmic behaviour o f the contacts is confirmed by I-V measurements Contact resistiv ities, pc, o f the proposed m etallizations are measured using the conventional Transm ission L ine M odel (cTLM ) method The form ation o f various compounds at the lowest pc point w ill be determined by mass spectrometer analysis F in a lly , a comparison w ill be made among non-alloyed Pd/Sn and Pd/Sn/Au and alloyed five -layer A u/G e/A u/N i/A u contacts

5.2 Experiments

Contacts were fabricated on a Si-doped (2x1018 cm’3) n-GaAs epitaxial layer grown by metal-orgamc vapor phase epitaxy (M O V P E ) in a metal-semiconductor fie ld-effect transistor (M E S F E T) structure shown previously in F ig 4 3 The GaAs substrates were sequentially cleaned and degreased in tnchloroethylene, acetone, methanol and deionized water (D I H 20 ), each fo r 10 mm The substrates were blow-dried im m ediately using dry nitrogen (N 2) Ohmic test, morphology and T L M patterns were defined by standard photolithography and lifit-o ff processes A so lution o f H 20 2 N H 4OH D I H 20 (1.3:15 by volum e) was used as an etchant fo r mesa defin ition

71

P rio r to loading into an evaporator, the wafers were soaked in a solution o f D I H 20:HC1 (15:1 by volum e) fo r at least 2 m in and then b low dried using dry N 2 to remove native oxides. Samples consisting o f n-GaAs/Pd(30 nm )/Sn(150 nm )/Au(40 nm), n-GaAs/Pd(30 nm)/Sn(150 nm )/Au(100 nm ), n-GaAs/Pd(50 nm)/Sn(125 nm )/Au(40 nm ), n-GaAs/Pd(50 nm)/Sn(125 nm )/Au(100 nm), n-GaAs/Pd(25nm )/Sn(102 nm )/Au(100 nm) and n-GaAs/Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ) structures were prepared by sequential deposition o f m etallizations in a resistance heating evaporator w ithout breaking vacuum. The base pressure was

7 6 6-4 x1 0 ’ T o rr and pressure during evaporation was between 1x10’ T o rr and 6x10' Torr.

A ll samples w ith n-GaAs/Pd/Sn/Au structures were then annealed in the temperature range o f 300-360 °C fo r 30 m in by a conventional graphite strip annealer in a flow ing form ing gas (5% H2 + 95% N 2) ambient. The five-layer Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i(l 1 nm )/Au(200 nm) contacts were alloyed at 430 °C fo r 6 m in under the same form ing gas ambient in a graphite strip annealer.

Surface m orphology o f the contacts was investigated using a Tencor Instruments Surface P rofilom eter and a H itachi S-4000 FESEM (FE M ). A Cameca IM S 3 f SIM S intrum ent using an 0 2+ prim ary ion beam w ith an impact energy o f 12.5 keV was used in depth p ro filing studies. Conversion from Schottky to Ohmic behaviour o f the contacts was examined by I-V measurements. Contact res is tiv ity was measured u tiliz ing the cTLM method.



The pc o f the contacts are measured in a test pattern conform ing to the T L M (Fig .4.1), w ith the pad spacing ranging from 2 to 128 (im . The w id th o f the Ohmic pad, W, is 140 jam. The transfer length method [12] is utilized to measure pc values o f the contacts. The Pd/Sn/Au contacts are annealed fo r 30 m in. It is assumed that the sheet resistance o f the semiconductor under the contacts, Rxhl, is equal to the sheet resistance o f the semiconductor in between the contacts, Rsh2. F ig .5.1 shows the measured average contact res is tiv ity vs. annealing temperature curves fo r 4 T L M patterns. A lowest pc o f 3.89x1 O'6 Q-cm2 is obtained at 330 °C fo r the Pd(30 nm )/Sn(150 nm )/Au(100 nm) contacts, whereas the Pd(30 nm)/Sn(150 nm )/Au(40 nm) contacts show a lowest pc o f 2.05x10-5 Q-cm2 at 360 °C.

72

The Pd(50 nm)/Sn(125 nm )/Au(40 nm) contacts show a lowest pc o f 5.10x1 O'6Q-cm2 at 330 °C, whereas the Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts have a

6 2lowest pc o f 1.29x10’ Q-cm at the same annealing temperature. However, the Pd(25 nm )/Sn(102 nm )/Au(100 nm) contacts display a lowest pc o f 2.27x1 O’5 Q-cm2 at 330 °C. In the previous chapter (Section 4.4.1), it is seen that the Pd(30 nm)/Sn(150 nm) contacts produce a m inim um pc o f 3.26x10° Q-cm2 after annealing at 360 °C fo r 30 m in, whereas the Pd(50 nm)/Sn(125 nm) contacts give a lowest pc o f 2.07x10° Q-cm2 at 400 °C. Therefore, a suitable A u overlayer improves the electrical characteristics o f the Pd/Sn Ohmic contacts and lowers the pc values by approxim ately one order o f magnitude. A A u overlayer also changes the annealing cycles o f the Pd/Sn contacts at the lowest pc points. The five-layer Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i( llnm )/Au(200 nm) contacts show a pc o f 6 .49xl0 "6 Q-cm2 after a lloying at 430 °C fo r 6

6 2m in. Herbert et al. [41] reported a pc in the range o f low 10’ Q-cm w ith th is five-layer contact after alloying at 425 °C fo r 140 seconds. The results reported in th is thesis are in consistent w ith those observations.

10 "

g 1(TVa5J 1CT (0M0)oreoO

10e

10 "

■ Pd(50 nm)/Sn(125 nm)/Au(40 nm)• Pd(50 nm)/Sn(125 nm)/Au(100 nm)

■ Pd(25 nm)/Sn(102 nm)/Au(100 nm)

250 300 350 400


Fig.5.1. Contact res istiv ity vs. annealing temperature curves o f the Pd/Sn/Au Ohmic contacts to n-GaAs. A ll contacts are annealed fo r 30 m in.

The reduction in pc values can be correlated w ith the production o f Ga out- d iffusion by Au in an open system where arsenic (A s) is allowed to escape through the m etallization into the surrounding atmosphere during annealing. In such a system, Au w ill dissolve GaAs to form Au-Ga compounds. The large positive entropy o f

73

sublim ation o f As w ill help to drive the Au-Ga reactions [158]. The technological importance o f th is reaction is that out-d iffusion o f Ga encourages the incorporation o f Sn im purities on Ga sites in the GaAs near the metal/GaAs interface, thereby resulting in the form ation o f a th in layer o f n+-GaAs which lowers the pc values.

TABLE X III summarizes the lowest pc and measurement error, Apc, o f thePd/Sn/Au Ohmic contacts. The Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts appear to

6 2have excellent reproducib ility w ith a Apc o f ±1.0x10" Q-cm among a ll o f the Pd/Sn/Au m etallizations investigated. The five-layer A u/G e/A u/N i/A u contacts show a Apc o f ±3 .25x l0 "6 Q-cm2 after having been alloyed at 430 °C fo r 6 m in.

TABLE X III. Summary o f calculated average pc and measurement error, Apc, values o f the Pd/Sn/Au and A u/G e/A u/N i/A u Ohmic contacts to n-GaAs.

Contact structure Annealingcondition

Pc(Q -cm 2)

Apc(Q-cm 2)

*Pd(30 nm )/Sn(150 nm) 360 °C, 30 m in 3.26x10'5 ± 2 .5 0 x l0 ’5Pd(30 nm )/Sn(150 nm )/Au(40 nm) 360 °C, 30 m in 2 .0 5 x l0 ’5 ± 0 .3 1 x l0 '5Pd(30 nm )/Sn(150 nm )/Au(100 nm) 330 °C, 30 m in 3.89x1 O'6 ± 1 .5 0 x l0 ‘6*Pd(50 nm)/Sn(125 nm) 400 °C, 30 m in 2.07x10'5 ±0.92x10'5Pd(50 nm)/Sn(125 nm )/Au(40 nm) 330 °C, 30 m in 5 .1 0 x l0 ’6 ±3.80x1 O'6Pd(50 nm)/Sn(125 nm )/Au(100 nm) 330 °C, 30 m in 1.29x1 O'6 ±1.00x1 O'6Pd(25 nm )/Sn(102 nm )/Au(100 nm) 330 °C, 30 m in Au(14 nm)/Ge(14 nm )/Au(14 nm )/ 430 °C, 6 m in N i( ( l 1 nm )/Au(200 nm)j----------------------------------------------------------------------------------------------------------------------------

2.27x10 '5 6.49x1 O'6

±1.26x10‘5 ±3.25x10‘6

From TABLE V II (Section 4.4.1)

5.3.2 Surface profilometry measurements

Details o f surface p rofile measurements o f the non-alloyed Pd/Sn/Au and alloyed A u/G e/A u/N i/A u contacts are summarized in TABLE X IV . In the as-deposited state, the Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts show a T IR o f 4.5 nm and Ra o f 0.5 nm, whereas fo r the Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm) contacts these values are 3.5 nm and 1.0 nm. respectively. The Pd(25 nm )/Sn(102 nm )/Au(100 nm) contacts produce a T IR o f 35 nm and a Ra o f 5 nm in the as-deposited condition.

74

A t the lowest pc point, the Pd(30 nm)/Sn(150 nm )/Au(40 nm ) contacts display a T IR o f 85 nm and a Ra o f 5 nm, whereas fo r the Pd(30 nm )/Sn(150 nm )/Au(100 nm) contacts these values are 6 nm and 1 nm, respectively The Pd(50 nm)/Sn(125 nm )/Au(40 nm) contacts exhib it a T IR o f 810 nm and a Ra o f 165 nm, whereas fo r the Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts these values are 12 5 nm and 2 0 nm, respectively A t the lowest pc point, the Pd(25 nm )/Sn(102 nm )/Au(100 nm ) contacts show a T IR o f 20 nm and a Ra o f 0 nm From the previous chapter (Section 4 4 2, TABLE IX ), it is seen that the Pd(30 nm)/Sn(150 nm ) contacts exhib it a T IR o f 90 nm and a Ra o f 15 nm at the lowest pc point, whereas fo r the Pd(50 nm)/Sn(125 nm) contacts these values are 33 nm and 5 nm, respectively Thus, a jud icious choice fo r a A u overlayer improves the surface profiles o f the Pd/Sn contacts significantly However, the A u/G e/A u/N i/A u contacts show significantly rougher surface profiles w ith a T IR o f 625 nm and a Ra o f 119 nm under the alloyed condition

TABLE X IV Summary o f surface profiles o f the Pd/Sn/Au and A u/G e/A u/N i/A u contacts to n-GaAs

Contact structure Annealing condition T IR (nm ) Ra (nm)

Pd(50 nm )/Sn(125 nm )/Au(100 nm) as-deposited 4 5 0 5Pd(50 nm )/Sn(125 nm )/Au(100 nm) 330 °C, 30 m in 12 5 2 0Pd(50 nm )/Sn(125 nm )/Au(40 nm) 330 °C, 30 mm 810 165Pd(50 nm )/Sn(125 nm) as-deposited 24 5 3 5Pd(50 nm )/Sn(125 nm) 400 °C, 30 mm 33 0 5 0

*Pd(30 nm )/Sn(150 nm) as-deposited 30 0 5 0Pd(30 nm )/Sn(150 nm) 360 °C, 30 mm 90 0 15 0

Pd(30 nm )/Sn(150 nm )/Au(40 nm) 360 °C, 30 m in 85 0 5 0Pd(30 nm )/Sn(150 nm )/Au(100 nm) 330 °C, 30 mm 6 0 1 0Pd(25 nm )/Sn(102 nm )/Au(100 nm) as-deposited 35 0 5 0Pd(25 nm )/Sn(102 nm )/Au(100 nm) 330 °C, 30 m in 20 0 0 0Au(14 nm )/Ge(14 nm )/Au(14 nm )/ as-deposited 3 5 1 0N i( l 1 nm )/Au(200 nm)Au(14 nm )/Ge(14 nm )/Au(14 nm )/ 430 °C, 6 m in 625 119N i( l 1 nm )/Au(200 nm)

From T a b l e IX (Section 4 4 2)

75


SEM micrographs o f the Pd/Sn/Au contacts under both as-deposited and lowest pc conditions are shown in Fig 5 2 M icro-crystals o f the order o f ~0 2 (j.m in diameter are observed on the surface w ith the Pd(30 nm)/Sn(150 nm )/Au(40 nm) contacts under both as-deposited (F ig 5 2(a)) and at the lowest pc (F ig 5 2(b)) conditions However, the m etallizations appear to be more un ifo rm ly distributed at the lowest pc point when compared to the as-deposited state The Pd(30 nm )/Sn(150 nm )/Au(100 nm) contacts display smooth surface morphology under both as-deposited (F ig 5 2(c)) and lowest pc (F ig 5 2(d)) conditions The Pd(30 nm)/Sn(150 nm) contacts produce m icro-crystals o f the order o f ~1 0 |am in diameter under both as-deposited and lowest pc conditions (F ig 4 6(a) & Fig 4 6(b)) Therefore, Au overlayers im prove the surface m orphology o f the Pd(30 nm )/Sn(150 nm ) contacts significantly The Pd(25 nm )/Sn(102 nm )/Au(100 nm ) contacts show m icro-crystals o f the order o f ~0 2 fim in diameter under both as- deposited (F ig 5 2(e)) and lowest pc (F ig 5 2 (f)) conditions

The Pd(50 nm)/Sn(125 nm )/Au(40 nm) contacts exhib it smooth surface m orphology under as-deposited condition (F ig 5 3(a)) A t the lowest pc point (F ig 5 3(b)), the surface morphology o f these contacts deteriorates but s till better than the Pd(50 nm)/Sn(125 nm) contacts (F ig 4 7(d)) The Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts display smooth surface morphology under both as-deposited (F ig 5 3(c)) and lowest pc (330 °C, 30 mm) (F ig 5 3(d)) conditions Once again, a jud icious choice o f A u overlayers improve the surface morphology o f the Pd(50 nm)/Sn(125 nm) contacts significantly

A lloyed Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ) contacts produce smooth surface morphology on ly under as-deposited condition (F ig 5 3(e)) Subsequently, surface morphology o f th is five-layer contact system degrades after a lloying at 430 °C fo r 6 mm (F ig 5 3 (f)) Therefore, Pd/Sn/Au m etallization exhibits better surface morphology than that o f alloyed A u/G e/A u/N i/A u m etallization w ith a comparable contact res istiv ity Surface profilom etry measurements (T a b l e X IV ) also reveal these results

76

(a) (b)•e v > ..v •; -,iV' * '*mji# ” ' >/ «■ . ,v ,:e-3« -■ • c- ■ • 1 niv#» • , Ip •«• ♦. % V -i- !

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;- .«y W '1 •• ^ t-> , f><’«** %»,-*• ■& .fC-'- V*?. *-t»M H W L ' U l 1 . 0 k V X | 5 . ' r - .' i ? * ' >•' n,

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a ‘ • - ■ “■' • •. .<> r '- > . ..'•r- •• C' • "■-• - ,4 ’ .- .- . ,• ■• -.,< • ■ '. • .x*r,c~-z r r ■- -I- ' • _r' •b'<: V> u,-: •'.•/ *JPy.'-: .

■' • '4>fc"" r~ <-r ; A •' -'■■-V' > , - * ■ p " - i • - / • * r ’^ r.\- i-^ '- -■ - - v . , . , _ . -:<■n •-c'- -.- o . ?f;''■** 1- . . <■ •* *. i;. cj i . . . * - .C- ’ - C > '- J r.;'-- T‘C> «sa,' J> tTi % / • '•'¿l,r’* , ^ « v . / . r> ca « f' ‘

■ > . . - Ii'^ 1 8 “ ' .w*:

N M R C f l l I f l . f l k V X I S . « K

Fig 5 2 SEM micrographs o f the Pd/Sn/Au contacts to n-GaAs (a) Pd(30 nm)/Sn(150 nm )/Au(40 nm ), as-deposited, (b) Pd(30 nm )/Sn(150 nm )/Au(40 nm ), 360 °C, 30 mm,(c) Pd(30 nm )/Sn(150 nm )/Au(100 nm), as-deposited, (d) Pd(30 nm )/Sn(150 nm )/Au(100 nm), 330 °C, 30 m in, (e) Pd(25 nm )/Sn(102 nm )/Au(100 nm ), as-deposited and (f) Pd(25 nm )/Sn(102 nm )/Au(100 nm), 330 °C, 30 mm

77

(a) (b)

S ’i i « ' m- ' -S ** ' J T ' - ’ . « a ^ 1 -v v ; < - «&.«#'%i ^ <..**•>• • - !«'«•' .> „ « - "• ♦•: «•;>

E’ fio f’y v * ' v L »**•*>■&•'* ,T ^ « •$¿ F .k .---jk - * _ ^ 4 % ! ' ^ '.■• - ' j •X j" i ; .;

N n R c o i i t i . o k v x i 5 . 6 k ' ' a '. ctVa'J,;,

(c) (d)

Fig 5 3 SEM micrographs o f the Pd/Sn/Au and A u /G e/A u /N i/A u contacts to n-GaAs(a) Pd(50 nm )/Sn(l25 nm )/Au(40 nm), as-deposited, (b) Pd(50 nm )/S n(l25 nm )/Au(40 nm), 330 °C, 30 mm, (c) Pd(50 nm )/Sn(l25 nm )/A u (l00 nm ), as-deposited, (d) Pd(50 nm )/S n (l25 nm )/A u (l00 nm), 330 °C, 30 m in, (e) A u (l4 nm )/G e(l4 nm )/A u (l4 n m )/N i( ll nm )/Au(200 nm), as-deposited and A u (l4 nm )/G e(l4 n m )/A u (l4 n m )/N i( ll nm )/Au(200 nm ), 430 °C, 6 mm

78

D e p t h ( m i c r o n )

(a)


(b)

Fig 5 4 S IM S depth profiles o f the Pd(50 nm )/Sn(125 nm )/Au(100 nm) contact to n-GaAs (a) as-deposited and (b) annealed at 330 °C, 30 mm

5.3.4 Contact depth profiles using SIMS

Since the reproducib ility o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm ) Ohmic contacts is superior to the other Pd/Sn/Au m etallizations investigated, S IM S depth profiles o f the Pd(50 nm )/Sn(125 nm )/Au(100 nm ) m etallization w ill be presented and compared w ith

79

those o f the alloyed Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm) m etallization

SIM S depth profiles o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts are shown in F ig 5 4 In the as-deposited state (F ig 5 4(a)), the m etal/GaAs interface is w e ll defined A fte r annealing at 330 °C fo r 30 mm (F ig 5 4(b)), it is found that Pd, Sn and A u atoms penetrate into the underlying GaAs The exact penetration depths o f these atoms can not be determined due to the ‘knock-on’ effect as described in Section 4 4 4 However, the metal/GaAs interface is s till w e ll defined after annealing at 330 °C fo r 30 mm A t the m inim um pc points, the slopes o f Pd and Sn profiles are even steeper and narrower fo r the n-G aAs/Pd/Sn/Au contacts (F ig 5 4(b)) than those o f the n-GaAs/Pd/Sn contacts (F ig 4 13(b)) Th is variation o f Pd and Sn profiles is due to the d ifferent annealing temperatures used in these contacts

The secondary ion counts o f Ga are higher fo r the n-G aAs/Pd/Sn/Au contacts (F ig 5 4(b)) than those o f the n-GaAs/Pd/Sn contacts (F ig 4 13(b)) Th is is due to the ou t-d iffusion o f Ga from GaAs by the in -d iffus ion o f A u in the contact structures containing A u as a m etallization [6] On the other hand, Ga atoms appear in the metal layer Therefore, the Pd/Sn/Au contacts are shallower than those o f the Pd/Sn contacts

F ig 5 5 shows SIM S depth profiles o f the n-G aAs/Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i(l 1 nm )/Au(200 nm) contacts under both as-deposited condition and after having been alloyed at 430 °C fo r 6 m in In the as-deposited state (F ig 5 5(a)), the metal/GaAs interface is w e ll defined A fte r a lloying at 430 °C fo r 6 mm (F ig 5 5(b)), the metal/GaAs interface is not w e ll defined as seen w ith the n-G aAs/Pd/Sn/Au contacts (F ig 5 4(b)) In addition, the penetration depths o f N i, Ge and A u species into underlying GaAs are quite significant compared to the Pd, Sn and Au species in n-G aAs/Pd/Sn/Au contacts Thus, the n-G aAs/Pd/Sn/Au contacts are more abrupt and shallower than those o f alloyed n-G aA s/A u/G e/A u/N i/A u contacts The n-GaAs/Pd/Sn contacts (F ig 4 13(b)) are also more abrupt and shallower than those o f alloyed n-G aAs/Au/G e/Au/N i/Au contacts (F ig 5 5(b))

80


(a)


(b)

Fig 5 5 S IM S depth profiles o f the Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ) contacts to n-GaAs (a) as-deposited and (b) alloyed at 430 °C fo r 6 m in

5.3.5 Mass spectrometer analysis

Fig 5 6 shows the mass spectrometer analysis o f positive secondary ions fo r the Pd(50 nm )/Sn(125 nm )/Au(100 nm) contacts at the lowest pc point Positive secondary ions o f

81

Pd+, Sn+, A u+, S i+, As+, Ga+, Ga2+, GaO+, SnO+, PdGa+, SnGa+ and Pd2+ are monitored in the ion m icroanalyzer Due to the noise generation at higher amu (>200) as described in Section 4 4 5, other ions could not be determined However, the detection o f PdGa+ and SnGa+ ions indicates the out-d iffusion o f Ga into the m etalliza tion

Mass (a.m u )

Fig 5 6 Mass spectra o f positive secondary ions fo r the n-GaAs/Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts annealed at 330 °C, 30 mm

Fig 5 7 shows the mass spectrometer analysis o f positive secondary ions fo r the Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ) contacts under both as- deposited condition and after having been alloyed at 430 °C fo r 6 mm In the as- deposited state (F ig 5 7(a)), positive secondary ions o f N i+, Ge+, A u+, S i+, As+, Ga+, N i2+, Ga2+, GaO+, and As2+ are monitored in the ion m icroanalyzer A fte r a lloying at 430 °C fo r 6 mm (F ig 5 7(b)), N iA s+, Ga20 + and N i2Ga+ ions are m onitored in addition to the ions detected in the as-deposited state which are m consistent w ith the alloyed A u-G e/N i contacts [71,81]

82

s3OUsopmb«

*t5Scuo

1 5 0

Mass (a m u.)

(a)

200

1 0

I S O

Mass (a m.u.)

(b)

Fig 5 7 Mass spectra o f positive secondary ions fo r the Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i(l 1 nm )/Au(200 run) contacts to n-GaAs (a) as-deposited and (b) alloyed at 430 °C fo r 6 m in

83

5.4 Conclusion

The effects o f A u overlayers on the characteristics o f Pd/Sn Ohmic contacts to n-GaAshave been investigated A comparison has also been made among non-alloyed Pd/Snand Pd/Sn/Au and alloyed five -layer A u/G e/A u/N i/A u contacts A jud icious choice o fA u overlayers improves the characteristics o f Pd/Sn contacts A A u overlayer also

6 2changes the annealing cycles at the lowest pc points A lowest pc o f 3 89x10’ Q-cm isobtained fo r a substrate doping o f 2 x l0 18 cm’3 w ith a Pd(30 nm )/Sn(150 nm )/Au(100nm) contact after annealing at 330 °C fo r 30 mm, whereas the Pd(50 nm)/Sn(125

6 2nm )/Au(100 nm) contact had a m inim um pc o f 1 29x10" Q-cm at the same annealingcondition The reproducib ility o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm ) Ohmic contact

6 2is also excellent w ith a Apc o f ±1 0x10’ Q-cm at the lowest pc point The Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm) contacts produce a pc o f 6 4 9 x l0 ’6 Q-cm2 after a lloying at 430 °C fo r 6 m in

Proper choice o f A u overlayers also improves the morphological characteristics o f Pd/Sn contacts The Pd(50 nm)/Sn(125 nm )/Au(100 nm ) Ohmic contacts appear to have better surface morphology and a low er metal penetration in to the underlying GaAs than those o f alloyed five-layer A u/G e/A u/N i/A u contacts as evidenced by Surface P ro filom etry measurements, SEM and SIM S The Pd(50 nm )/Sn(125 nm ) contacts are also shallower than those o f alloyed A u/G e/A u/N i/A u contacts Surface m orphology o f the Pd(30 nm )/Sn(150 nm )/Au(100 nm ) and Pd(50 nm )/Sn(125 nm )/Au(100 nm ) Ohmic contacts is even better than that o f alloyed Au-G e/N i and non-alloyed Au-Ge Ohmic contacts to n-GaAs w ith a comparable contact res is tiv ity [73,121]

Mass spectrometer analysis indicates the form ation o f PdGa and SnGa at the lowest pc condition w ith the Pd/Sn/Au contacts However, the form ation o f other compounds w ith higher amu (>200) could not be identified due to the noise generation as described in Section 4 4 5 For the A u/G e/A u/N i/A u contacts, form ation o f N iA s and N i2Ga compounds are confirmed after a lloying at 430 °C fo r 6 mm

84

CHAPTER 6

Comparison of Pd/Sn, Pd/Ge, Pd/Sn/Au and alloyed Au-Ge/Ni

Ohmic contacts to n-GaAs

6.1 Introduction

The electrical and m orphological characteristics o f Pd/Sn and Pd/Sn/Au Ohmic contacts are described in the previous chapters (chapter 4 & chapter 5) Non-alloyed Pd/Ge and alloyed A u-G e/N i are the most common Ohmic contacts fo r n-GaAs In th is chapter, an e ffo rt has been made to fabricate these contacts on the same M E S FE T structure (F ig 4 3) as used fo r the Pd/Sn and Pd/Sn/Au Ohmic contacts A lloyed N i/A u-G e/N i contacts have also been fabricated m order to investigate the effect o f N i firs t layer on the properties o f Au-G e/N i Ohmic contacts The electrical and morphological characteristics o f the non-alloyed Pd/Ge and alloyed A u-G e/N i and N i/A u -G e/N i Ohmic contacts have been studied and compared w ith those o f the Pd/Sn and Pd/Sn/Au contacts M etallizations are deposited using a resistance heating evaporator and annealing is carried out in a conventional graphite stnp annealer Surface morphology o f the contacts is investigated using Scanning Electron M icroscopy (S EM ) Conversion from Schottky to Ohmic behaviour o f the contacts is confirm ed by I-V measurements Contact resistiv ities, pc, o f the m etallizations are measured using the cTLM method

6.2 Experiments| oContacts were fabricated on a Si-doped (2x10 cm’ ) n-GaAs epitaxial layer grown by

metal-organic vapor phase epitaxy (M O VPE) in a metal-semiconductor fie ld-effect transistor (M E S FE T) structure shown previously in F ig 4 3 The GaAs substrates were sequentially cleaned and degreased in the same manner as used fo r the preparation o f Pd/Sn and Pd/Sn/Au contacts (Section 4 3 and Section 5 2) Ohmic test, morphology and T L M patterns were defined by standard photolithography and lif t - o f f processes A solution o f H 20 2 N H 4OH D I H20 (1 3 15 by volum e) was used as an etchant fo r mesa d efin ition

85

P rio r to loading into an evaporator, the wafers were soaked m a solution o f D I H20 HC1 (15 1 by volum e) fo r at least 2 m in and then b low dried using dry N 2 to remove native oxides Samples consisting o f n-GaAs/Pd(50 nm)/Ge(126 nm), n-G aAs/Au-12w t % Ge(150 nm )/N i(16 nm) and n-G aAs/N i(5 nm )/A u-12w t %Ge(150 nm )/N i(16 nm ) structures were prepared by sequential deposition o f m etallizations in a resistance heating evaporator w ithout breaking vacuum The base pressure was ~ lx l O’6 To rr and pressure during evaporation was between 1 5x1 O’6 T o rr and 4 5x1 O'6 To rr

The n-GaAs/Pd(50 nm)/Ge(126 nm ) contacts were then annealed in the temperature range o f 300-360 °C fo r 30 mm by a conventional graphite strip annealer m a flow ing form ing gas (5% H 2 + 95% N 2) ambient The eutectic n-GaAs/Au-Ge(150 nm )/N i(16 nm ) and n-G aAs/N i(5 nm )/Au-G e(150 nm )/N i(16 nm) contacts were alloyed fo r 150 s m the temperature range o f 400-440 °C under the same form ing gas ambient m a graphite strip annealer The alloying tim e was measured from the moment at which the wafer temperature reached 98% o f its preset value

Surface m orphology o f the contacts was investigated using a Cambridge S360 SEM Conversion from Schottky to Ohmic behaviour o f the contacts was examined by I-V measurements Contact res is tiv ity was measured u tiliz in g the cTLM method



The pc o f the contacts are measured in a test pattern conform ing to the T L M (F ig 4 1),w ith pad spacing ranging from 2 to 128 |im The w id th o f the Ohmic pad, W, is 140 jam The transfer length method [12] is utilized to measure pc values o f the contacts The Pd/Ge contacts are annealed fo r 30 mm It is assumed that the sheet resistance o f the semiconductor under the contacts, Rshl, is equal to the sheet resistance o f the semiconductor in between the contacts, R.M F ig 6 1 shows the measured average contact re s is tiv ity vs annealing temperature curves fo r 2 groups o f samples, each group consists o f tw o samples A lowest pc o f 2 84x10 6 Q-cm2 is obtained at 330 °C fo r the Pd(50 nm)/Ge(126 nm) contacts This pc value is approxim ately one order o f magnitude low er than that o f the Pd(50 nm)/Sn(125 nm) contacts (F ig 4 4) M oreover, the Pd/Ge contacts show excellent reproducib ility w ith a Apc o f ±0 1 2 x l0 ’6 Q-cm2.

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Fig 6 1 Contact res is tiv ity vs annealing temperature curves o f the non-alloyed Pd/Ge and alloyed Au-G e/N i and N i/A u -G e/N i Ohmic contacts to n-GaAs The Pd/Ge contacts are annealed fo r 30 mm, whereas the Au-G e/N i and N i/A u -G e /N i contacts are alloyed fo r 150 s

The alloyed eutectic Au-Ge(150 nm )/N i(16 nm ) contacts produce a m inim um pc o f 1 90x1 O'5 Q-cm2 after having been alloyed at 420 °C fo r 150 s, whereas the N i(5 nm )/Au-G e(150 nm )/N i(16 nm ) contacts display a lowest pc o f 7 60x1 O’6 Q-cm2 at the same annealing condition The measurement error, Apc, o f the A u-G e/N i contacts at the m inim um pc point is ±1 04x10‘5 Q-cm2, whereas fo r the N i/A u -G e /N i contacts this value is ±3 40x10"6 Q-cm2 Therefore, the N i firs t layer reduces the spread o f pc significantly which is consistent w ith the observations o f Shih et al [81] Moreover, a 5 nm N i firs t layer in the alloyed Au-G e/N i Ohmic contacts lowers the pc value significantly The m inim um pc value o f the alloyed N i/A u -G e /N i Ohmic contacts is s lig h tly higher than that o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts annealed at 330 °C fo r 30 mm (F ig 5 1) However, the Au-G e/N i contacts produce a lowest pc which is approxim ately one order o f magnitude higher than that o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts The Pd(50 nm )/Sn(125 nm )/Au(100 nm) contacts show superior reproducib ility w ith a Apc o f ±1 00x1 O'6 Q-cm2 (Section 5 3 1) than those o f alloyed Au-G e/N i and N i/A u -G e/N i Ohmic contacts


SEM micrographs o f the non-alloyed Pd/Ge and alloyed A u-G e/N i and N i/A u-G e/N i contacts under both as-deposited and lowest pc conditions are shown in F ig 6 2 The

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Pd/Ge contacts show smooth surface m orphology under the as-deposited state (F ig 6 2(a)) A fte r annealing at 330 °C fo r 30 m in (F ig 6 2(b)), surface m orphology o f th is contact system detenorates very s lightly, but remains superior to that o f Pd(50 nm)/Sn(125 nm ) (F ig 4 7(d)) and Pd(50 nm)/Sn(125 nm )/Au(100 nm ) (F ig 5 3(d)) contacts

(a) (b)

Fig 6 2 SEM micrographs o f the non-alloyed Pd(50 nm)/Ge(126 nm ) contacts to n-GaAs (a) as-deposited and (b) annealed at 330 °C fo r 30 mm

Fig 6 3 shows the SEM micrographs o f the alloyed Au-Ge(150 nm )/N i(16 nm) and N i(5 nm )/Au-G e(150 nm )/N i(16 nm) contacts In the as-deposited state (F ig 6 3(a)), the A u-G e/N i contacts display almost smooth surface m orphology A fte r having been alloyed at 420 °C fo r 150 s (F ig 6 3(b)), surface m orphology o f the A u-G e/N i contacts deteriorates significantly and balling-up o f the m eta lliza tion is observed The N i/A u - G e/N i contacts exhib it smooth surface morphology in the as-deposited state (F ig 6 3(c)) A t the m inim um pc point (F ig 6 3(d)), the N i/A u -G e /N i contacts show rough surface m orphology Balling-up o f the m etallization is also observed in this case However, at the m inim um pc point, the N i/A u-G e/N i contacts produce better surface morphology than that o f the Au-G e/N i contacts (F ig 6 3(b) & F ig 6 3(d)) Therefore, a 5 nm N i firs t layer improves the morphological characteristics o f the alloyed Au-G e/N i Ohmic contacts A t the lowest pc point, both Pd(50 nm )/Sn(125 nm ) and Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts (F ig 4 7(d) & Fig 5 3(d)) show better surface morphology than that o f the alloyed Au-Ge(150 nm )/N i(16 nm) and N i(5 nm )/Au-G e(150 nm )/N i(16 nm ) contacts (F ig 6 3(b) & Fig 6 3(d))

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(a) (b)

Fig 6 3 SEM micrographs o f the Au-G e/N i and N i/A u -G e /N i contacts to n-GaAs(a) Au-Ge(150 nm )/N i(16 nm), as-deposited, (b) Au-Ge(150 nm )/N i(16 nm ), 420 °C, 150 s, (c) N i(5 nm )/Au-G e(150 nm )/N i(16 nm), as-deposited and (d) N i(5 nm )/Au- Ge(150 nm )/N i(16 nm ), 420 °C, 150 s

6.4 Conclusion

The electrical and morphological characteristics o f the non-alloyed Pd/Ge and alloyed eutectic A u-G e/N i and N i/A u-G e/N i Ohmic contacts to n-GaAs are presented and compared w ith those o f Pd/Sn and Pd/Sn/Au contacts The Pd(50 nm)/Ge(126 nm) contacts show excellent reproducib ility and produce a m inim um pc o f 2 84x10"6 Q-cm2 after annealing at 330 °C fo r 30 mm which is approxim ately one order o f magnitude low er than that o f the Pd(50 nm)/Sn(125 nm) contacts However, m inim um pc values are alm ost identical fo r both Pd(50 nm)/Ge(126 nm ) and Pd(50 nm)/Sn(125 nm )/Au(100 nm ) contacts A lowest pc o f 1 90 x105 Q-cm 2 is obtained fo r the Au-Ge(150 nm )/N i(16 nm ) contacts after having been alloyed at 420 °C fo r 150 s, whereas the N i(5 nm )/Au-Ge(150 nm )/N i(16 nm) contacts show a m inim um pc o f

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7 60x10’ Q-cm under the same annealing condition Therefore, a 5 nm N i firs t layer improves the electrical characteristics o f the alloyed A u-G e/N i contacts The Pd(50 nm)/Sn(125 nm )/Au(100 nm ) Ohmic contacts display superior reproducib ility and improved electrical characteristics w ith a m inim um pc o f 1 29x1 O’6 Q-cm2 (F ig 5 1) when compared w ith the alloyed Au-G e/N i and N i/A u -G e /N i contacts

The non-alloyed Pd/Ge Ohmic contacts appear to have better surface m orphology than those o f Pd/Sn and Pd/Sn/Au and alloyed A u-G e/N i and N i/A u-G e/N i Ohmic contacts A N i firs t layer improves the m orphological properties o f the alloyed A u-G e/N i contacts However, surface morphology o f the Pd/Sn and Pd/Sn/Au Ohmic contacts is better than those o f alloyed Au-G e/N i and N i/A u -G e /N i contacts

6 2

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CHAPTER 7

Thermal and long-term stability of the Pd/Sn and Pd/Sn/Au Ohmic

contacts to n-GaAs

7.1 Introduction

One o f the most im portant criteria fo r an Ohmic contact is its therm al stab ility 410 °C and 300 °C are typical temperatures fo r testing the degradation o f Ohmic contacts on GaAs [31,38,44,56] In this chapter, therm al and long-term stab ility analysis o f the Pd/Sn and Pd/Sn/Au Ohmic contacts w ill be presented A comparison w ill be made between the therm al stab ility o f the Pd/Sn and Pd/Ge contacts Therm al stab ility o f the Pd/Sn/Au contacts w ill be compared w ith those o f alloyed A u/G e/A u/N i/A u , Au-G e/N i and N i/A u -G e /N i contacts SEM w ill be employed to investigate the surface m orphology o f the Ohmic contacts Contact resistiv ities, pc, o f the proposed m etallizations are measured using the cTLM method

7.2 Experiments

Once again, the contacts were fabricated on a Si-doped (2x10 18 cm’3) n-GaAs epitaxial layer grown by metal-organic vapor phase epitaxy (M O V P E ) in a metal-semiconductor fie ld -effect transistor (M E S FE T) structure shown previously in F ig 4 3 Samples consisting o f n-GaAs/Pd(50 nm)/Sn(125 nm), n-GaAs/Pd(50 nm)/Ge(126 nm), n-GaAs/Pd(50 nm )/Sn(125 nm )/Au(100 nm), n-G aAs/Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm), n-G aAs/Au-12wt % Ge(150 nm )/N i(16 nm) and n-G aAs/N i(5 nm )/Au-12w t %Ge(150 nm )/N i(16 nm ) structures were prepared as described in the previous sections (Section 4 3, Section 5 3 & Section 6 2)

A fte r Ohmic contact form ation at the lowest pc points, therm al stab ility measurements o f the contacts were then earned out in a furnace at 410 °C fo r 10 h in a flow ing form ing gas (5% H2 + 95% N 2) ambient The long-term stab ility o f the contacts were performed at 300 °C fo r 400 h under the same ambient condition

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Surface m orphology o f the contacts was investigated using a H itachi S-4000 FESEM (F E M ) and a Cambridge S360 SEM Contact re s is tiv ity was measured u tiliz in g the cTLM method

Accumulated annealing time (hour)

Fig 7 1 Contact res is tiv ity vs accumulated annealing tim e curves fo r the Pd/Sn and non-alloyed Pd/Ge Ohmic contacts to n-GaAs at 410 °C


7.3.1 Thermal stability at 410 °C

The transfer length method [12] is u tilized to measure pc values o f the contacts It is assumed that the sheet resistance o f the semiconductor under the contacts, RM, is equal to the sheet resistance o f the semiconductor in between the contacts, Rsh2 F ig 7 1 shows the therm al stab ility at 410 °C fo r the n-GaAs/Pd(50 nm)/Sn(125 nm) and non-alloyed n-GaAs/Pd(50 nm)/Ge(126 nm ) contacts The average pc values o f 4 T L M patterns are presented m Fig 7 1 The zero accumulated annealing tim e value o f pc indicates the m inim um value o f pc fo r both types o f contacts before starting therm al stab ility at 410 °C A fte r annealing at 410 °C fo r 4 h, the Pd/Sn contacts show pc value in the range

“5 2o f low 10' Q-cm and no significant change in contact re s is tiv ity is observed A fte r 10 h o f annealing, the pc value reaches to ~ lx l O’4 Q-cm2 The pe o f the Pd/Ge contacts increases by approxim ately tw o orders o f magnitude from its in itia l value after 2 h o f annealing at 410 °C. A fte r that the Pd/Ge contacts m aintain a pc in the range o f low lx l0 "4 Q-cm2 but s till higher than those o f the Pd/Sn contacts Therefore, the Pd(50

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nm )/Sn(125 nm) contacts display supenor therm al stab ility at 410 °C when compared to the Pd(50 nm)/Ge(126 nm) contacts Han et al [56] observed that the non-alloyed R T A Pd/G e/Ti/P t contact is therm ally stable at 400 °C fo r 35 s Therefore, therm al stab ility o f the Pd/Sn contact is supenor to that o f the Pd/G e/Ti/P t contact

Fig 7 2 shows SEM micrographs o f the Pd/Sn and Pd/Ge contacts after having been annealed at 410 °C fo r 10 h For the Pd(50 nm )/Sn(125 nm ) contacts (F ig 7 2(a)), surface m orphology remains identical to that o f observed at the m inim um pc condition (F ig 4 7(d)) No change in surface m orphology is observed fo r the Pd/Ge contacts (F ig 7 2(b)) when compared to the lowest pc condition (F ig 6 2(b)) However, Pd/Ge contacts display superior surface morphology to that o f Pd/Sn contacts after having been annealed at 410 °C fo r 10 h (F ig 7 2)

(a) (b)

Fig 7 2 SEM micrographs o f the (a) Pd(50 nm)/Sn(125 nm ) and (b) non-alloyed Pd(50 nm)/Ge(126 nm ) contacts to n-GaAs after having been annealed at 410 °C fo r 10 h

Therm al stab ility o f the Pd(50 nm)/Sn(125 nm )/Au(100 nm ) and alloyed Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm), Au-Ge(150 nm )/N i(16 nm) and N i(5 nm )/Au-G e(150 nm )/N i(16 nm) Ohmic contacts at 410 °C is shown in Fig 7 3 A fte r 30 m in o f annealing at 410 °C, the pc o f the Pd/Sn/Au contacts increases by approxim ately one order o f magnitude The pc remains in the low 10'5 Q-cm2 range fo r up to 10 h o f annealing at 410 °C The alloyed five-layer A u/G e/A u /N i/A u Ohmic contacts show alm ost identical thermal stab ility to the Pd/Sn/Au contacts The thermal stab ility o f both Pd/Sn/Au and A u/G e/A u/N i/A u contacts is better than that o f alloyed A u-G e/N i and N i/A u-G e/N i contacts The A u-G e/N i contacts also show supenor therm al stab ility when compared w ith N i/A u -G e/N i contacts Th is is in consistent w ith observations o f Shih et al [81]

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103

0 10"41aS>

10 s (0 1U35

04

onc 10-6oO

10 70 2 4 6 8 10 12


Fig 7 3 Contact res is tiv ity vs accumulated annealing tim e curves fo r the Pd/Sn/Au, A u/G e/A u/N i/A u , Au-G e/N i and N i/A u-G e/N i Ohmic contacts to n-GaAs at 410 °C

- Pd(50 nm)/Sn(125 nm)/Au(100 nm)

—O—Au(14 nm)/Ge(14 nm)/Au(14 nm)/Ni(11 nm)/Au(200 nm)

—• — Au-Ge{150 nm)/Ni(16 nm)

- X - Ni(5 nm)/Au-Ge(150 nm)/Ni(16 nm)

Fig 7 4 SEM micrographs o f the (a) Pd(50 nm)/Sn(125 nm )/Au(100 nm ) and alloyed (b) Au(14 nm )/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ), (c) Au-Ge(150 nm )/N i(16 nm ) and (d) N i(5 nm )/Au-Ge(150 nm )/N i(16 nm ) contacts to n-GaAs after therm al stab ility at 410 °C fo r 10 h

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SEM micrographs o f the Pd/Sn/Au and alloyed A u/G e/A u/N i/A u , Au-G e/N i and N i/A u -G e /N i contacts after therm al stab ility at 410 °C fo r 10 h are shown m Fig 7 4 Sigm ficant changes m surface morphology are observed fo r a ll o f the contacts Segregation o f m etallization is observed on the surface w ith the A u-G e/N i and N i/A u - G e/N i contacts (F ig 7 4(c) & Fig 7 4(d)) The surface m orphology o f both Pd/Sn/Au (F ig 7 4(a)) and A u/G e/A u/N i/A u (F ig 7 4(b)) contacts is better than that o f the A u-G e/N i and N i/A u-G e/N i contacts

7.3.2 Long-term stability at 300 °C

Long-term stab ility o f the Pd(50 nm)/Sn(125 nm) and Pd(50 nm)/Ge(126 nm ) contacts is earned out at 300 °C fo r 400 h and is shown in F ig 7 5 A fte r 8 h o f annealing, the pc o f both Pd/Sn and Pd/Ge contacts increases by approxim ately one order o f magmtude The pc o f the Pd/Sn contacts remain in the low 10"4 Q-cm2 range up to 300 h F in a lly , it reaches the high 1 O’4 Q-cm2 range at 400 h The Pd/Ge contacts m aintain pc in the range o f low 10‘5 Q-cm2 up to 83 h A fte r that pc remains in the range o f m id 10'5 Q-cm2 Therefore, the long-term stab ility o f the Pd/Ge contacts appears to be better than that o f the Pd/Sn contacts


Fig 7 5 Contact re s is tiv ity vs accumulated annealing tim e curves fo r the Pd/Sn and Pd/Ge Ohmic contacts to n-GaAs at 300 °C

A fte r annealing at 300 °C fo r 400 h, SEM micrographs o f the Pd/Sn and Pd/Ge Ohmic contacts are shown in F ig 7 6 For the Pd/Sn contacts, no change m surface m orphology is observed after 400 h o f annealing at 300 °C (F ig 7 6(a)) when compared

95

to that o f the m inim um pc condition (Fig.4.7(d)). No change in surface morphology is also observed after annealing the Pd/Ge contacts fo r 400 h at 300 °C (F ig .7.6(b)) when compared to the lowest pc point (Fig .6.2(b)). However, Pd/Ge contacts show better surface m orphology than that o f Pd/Sn contacts after long-term stab ility tests (F ig .7.6).

F ig .7.6. SEM micrographs o f the (a) Pd(50 nm)/Sn(125 nm ) and (b) Pd(50 nm)/Ge(126 nm) contacts to n-GaAs after having been annealed fo r 400 h at 300 °C.

omcoo

1 0 '

—• — Pd(50 nm)/Sn(125 nm)/Au(100 nm)

—O — Au(14 nm)/Ge(14 nm)/Au(14 nm)/Ni(11 nm)/Au(200 nm)

—• — Au-Ge(150 nm)/Ni(16 nm)

■X— Ni(5 nm)/Au-Ge(150 nm)/Ni(16 nm)

50 100 150 200 250 300 350

A ccum ula ted an nealing tim e (hour)

400 450

F ig .7.7. Contact res is tiv ity vs. accumulated annealing tim e curves fo r the Pd/Sn/Au, A u/G e/A u/N i/A u , Au-G e/N i and N i/A u -G e/N i Ohmic contacts to n-GaAs at 300 °C.

F ig .7.7 shows the long-term stab ility o f the Pd/Sn/Au and alloyed A u /G e/A u/N i/A u , Au-G e/N i and N i/A u-G e/N i Ohmic contacts at 300 °C. A fte r 3 h o f annealing at 300 °C, the pc o f Pd/Sn/Au contacts reaches the m id 10° Q-cm2 range and remains in th is region up to 300 h. The pc approaches the high 10"5 Q-cm2 range at 400 h. For the alloyed five-layer A u/G e/A u/N i/A u contacts, the pc remains in the range

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5 2 5 2 to f low 10’ Q-cm up to 155 h and it increases to m id 10" Q-cm at 400 h The increase in pc fo r the alloyed A u-G e/N i contacts is m sigmficant up to 83 h o f annealing at 300 °C

5 2 5and pc remains in the range o f low 10' Q-cm A t 400 h, it increases to the high 10" Q - cm range The N i/A u -G e /N i contacts show the best long-term stab ility up to 83 h o f annealing at 300 °C among a ll o f the contacts investigated, w ith a pc in the range o f low

5 210’ Q-cm The five-layer alloyed A u/G e/A u/N i/A u contacts exh ib it the best stab ility at 300 °C fo r 400 h among a ll o f the Au-based contacts (F ig 7 7)

(a) (b)

Fig 7 8 SEM micrographs o f the (a) Pd(50 nm)/Sn(125 nm )/Au(100 nm ) and alloyed (b) Au(14 nm)/Ge(14 nm )/Au(14 n m )/N i( ll nm )/Au(200 nm ), (c) Au-Ge(150 nm )/N i(16 nm ) and (d) N i(5 nm )/Au-Ge(150 nm )/N i(16 nm ) contacts to n-GaAs after long-term stab ility at 300 °C fo r 400 h

A fte r long-term stab ility tests at 300 °C fo r 400 h, SEM micrographs o f the Pd/Sn/Au and alloyed A u/G e/A u/N i/A u , Au-G e/N i and N i/A u -G e /N i contacts are shown m Fig 7 8 No significant change in surface m orphology is observed after 400 h o f annealing at 300 °C fo r the Pd/Sn/Au (F ig 7 8(a)) and A u /G e/A u /N i/A u (F ig 7 8(b)) contacts when compared to the lowest pc conditions (F ig 5 3(d) & F ig 5 3 (f)) However, the A u-G e/N i and N i/A u-G e/N i contacts display alm ost identical morphological

97

characteristics after having been annealed at 300 °C fo r 400 h (F ig7 8(c) & Fig 7 8(d))

7.4 Conclusion

Therm al stab ility and long-term stab ility o f the Pd/Sn and Pd/Sn/Au Ohmic contacts are presented and compared to the non-alloyed Pd/Ge and alloyed A u/G e/A u/N i/A u, Au-G e/N i and N i/A u -G e /N i Ohmic contacts The Pd/Sn contacts show superior therm al stab ility at 410 °C to that o f the Pd/Ge contacts A fte r annealing at 410 °C fo r 4 h, pc o f the Pd/Sn contacts reduces to 1 4 4 x l0 ’5 Q-cm2 from the in itia l value o f 2 0 7 x l0 ’5 Q- cm The pc o f the Pd/Ge contacts increases by approxim ately tw o orders o f magnitude after 2 h o f annealing at 410 °C from the in itia l value o f 2 84x1 O'6 Q-cm2 No significant change in surface morphology o f both Pd/Sn and Pd/Ge contacts is observed However, the Pd/Ge contacts exhib it better surface m orphology than that o f the Pd/Sn contacts after annealing fo r 10 h at 410 °C

The Pd/Sn/Au contacts show almost identical therm al stab ility at 410 °C to that o f the alloyed five-layer A u/G e/A u/N i/A u contacts A fte r annealing at 410 °C fo r 10 h, the pc o f the Pd/Sn/Au contacts increases by approxim ately one order o f magnitude and remains in the range o f lo w 10"5 Q-cm2 The Pd/Sn/Au contacts also display better therm al stab ility than that o f non-alloyed Pd/Ge and alloyed A u-G e/N i and N i/A u - G e/N i Ohmic contacts at 410 °C A lthough the electrical and morphological characteristics o f N i/A u -G e /N i Ohmic contacts are better than that o f A u-G e/N i contacts (Section 6 3), therm al stab ility o f the form er contacts is worse Surface m orphology o f the above Au-Ge based contacts deteriorates significantly after annealing at 410 °C fo r lO h

Long-term stab ility at 300 °C o f the non-alloyed Pd/Ge contacts is better than that o f the Pd/Sn contacts A fte r 8 h o f annealing at 300 °C, the pc o f the Pd/Sn contacts increases by approxim ately one order o f magnitude from an in itia l value o f 2 07x10'5 Q - cm2 A t th is condition, the Pd/Ge contacts m aintain pc in the range o f low 10"5 Q-cm2 A fte r annealing fo r 400 h at 300 °C, pc o f the Pd/Ge contacts remains in the range o f

-5 2m id 10 Q-cm , w hich is one order o f magnitude low er than that o f the Pd/Sn contacts Once again, no change in surface morphology o f the Pd/Sn and Pd/Ge contacts is observed The Pd/Ge contacts m aintain surenor surface m orphology to that o f the Pd/Sn contacts after annealing at 300 °C fo r 400 h

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The alloyed N i/A u-G e/N i contacts show improved long-term stab ility at 300 °C on ly up to 83 h A fte r that, the five-layer A u/G e/A u/N i/A u contacts m aintain pc in the

5 2range o f m id 10' Q-cm w hich is better than those o f the Pd/Sn/Au and alloyed A u-G e/N i and N i/A u-G e/N i contacts For the Pd/Sn/Au contacts, pc remains in the

5 2 5 2range o f m id 10" Q-cm up to 300 h and it approaches the high 10" Q-cm range at 400 h A t 300 °C, the Pd/Sn/Au Ohmic contacts display pc’ s w hich are s lig h tly higher than those o f alloyed A u/G e/A u/N i/A u, Au-G e/N i and N i/A u -G e /N i contacts However, the Pd/Sn/Au contacts m aintain better surface m orphology than that o f the alloyed contacts and no significant m orphological change is observed after annealing at 300 °C fo r 400 h Therefore, therm ally stable Pd/Sn and Pd/Sn/Au Ohmic contacts appear to be prom ising candidates fo r GaAs devices

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CHAPTER 8

Fabrication of GaAs MESFETs using Pd/Sn and Pd/Sn/Au

Ohmic contacts

8.1 Introduction

GaAs M etal Semiconductor F ie ld -E ffect Transistors (GaAs M ESFETs) have been fabricated using Pd/Sn and Pd/Sn/Au Ohmic contacts as source/drain m etallizations and Schottky A1 gate contacts. The characteristics o f the GaAs M ESFETs fabricated w ith non-alloyed Pd/Ge Ohmic contacts are also investigated and compared w ith those o f the Pd/Sn and Pd/Sn/Au contacts. M etallizations are deposited using a resistance heating evaporator and annealing is carried out in a conventional graphite strip annealer. Surface m orphology o f the contacts is investigated using Scanning Electron M icroscopy (SEM ). Conversion from Schottky to Ohmic behaviour o f the contacts is confirm ed by I-V measurements. The I-V characteristics o f the GaAs M ESFETs are determined using a T E K T R O N IX 576 curve tracer. Contact resistiv ities, pc, o f the m etallizations are measured using the cTLM method.

8.2 Experimental Procedures

8.2.1 Level 1 - Mesa isolation

The substrate shown previously in Fig.4.3 is used fo r the M E S FE T fabrication. The firs t process in the fabrication cycle is the production o f mesas on the surface by chemical etching. A n appropriate mask and Shipley M icroposit S 1818 positive photoresist are used fo r th is purpose. Mesas fo r the M ESFETs, morphology and T L M structures were fabricated in the same chip. It is important to etch deep enough such that the bulk SI GaAs is reached. Th is provides mesas which are electrically isolated from each other. The sequential steps fo r the mesa isolation were as fo llow s:• The GaAs substrates were sequentially cleaned and degreased in trichloroethylene,

acetone, methanol and de-ionized water (D I H20 ), each fo r 10 m in.

100

• The substrates were blow-dned im m ediately using dry N 2• Spin on M icroposit S I818 photoresist diluted w ith M icroposit EC solvent m the

ra tio o f 1 4 by volum e Spinner speed and acceleration were optim ised using testsamples Spinner speed=4500 rpm and acceleration ^maximum

• Soft bake at 115 °C fo r 5 m in and cool to room temperature• Using a U V lig h t mask aligner and mesa mask, expose the substrates fo r 25 s

Expose tim e was optimised using test samples• Develop in 3 1 (by volum e) D I H 20 M icroposit M 3 51 developer fo r ~60 s and then

clean in D I H 20 D ry o ff using N 2• Hard bake at 115 °C fo r 5 mm and cool to room temperature• Etch m a solution o f H 20 2 N H 4OH D I H 20 (1 3 15 by volum e)• The etch rate fo r the above etchant was typ ica lly 0 8 |am /m in at a room temperature

o f 20 °C and was determined from test samples The etch tim e was 4 mm 15 s so that the to ta l etch depth became at least 3 2 |a.m

• Rinse m D I H 20 and dry o f f on ly using N 2• Leave the chips in acetone fo r 10 m in and strip o ff photoresist Rinse in D I H 20 and

dry o ff using N 2

8.2.2 Level 2 - Ohmic contacts

The second level is the Ohmic level The sequential process steps o f th is level were asfo llow s• Spin on M icroposit S 1818 photoresist diluted w ith EC solvent in the ra tio o f 1 1 by

volum e on the mesa defined chip Th is ratio was optim ised using test samples• Soft bake at 115 °C fo r 5 m in and cool to room temperature• Soak in chlorobenzene fo r 3-4 mm and dry o ff on ly Th is gives the resist an

undercut p ro file w hich w ill assist the metal l if t o ff• Using a U V lig h t mask aligner and Ohmic mask, expose the substrates fo r 12 s

Expose tim e was optimised using test samples• Develop in 3 1 (by volum e) D I H 20 M icroposit M3 51 developer fo r -4 5 s and then

clean in D I H 20 D ry o ff using N 2• The source/drain m etallizations were sequentially cleaned m tnchloroethylene,

acetone, methanol and de-iomzed water (D I H 20 ), each fo r 10 m in and dry o ff usingN2

• P rio r to loading into an evaporator, the wafers were soaked in a solution o f D I H 20.HC1 (15.1 by volum e) fo r at least 2 m in and then b low dried using dry N 2 to remove native oxides.

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• The n-GaAs/Pd(50 nm)/Sn(125 nm), n-GaAs/Pd(50 nm )/Ge(126 nm) and n-GaAs/Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts were prepared by sequential deposition o f m etallizations in a resistance heating evaporator (Appendix A ) w ithout breaking vacuum W boats were used as evaporation sources The base pressure was ~ lx l0 ’6 T o rr and pressure during evaporation was between 1 5 x l0 ’6 To rr and 4 5x1 O'6 To rr

• Leave the chips in M icroposit 1165 remover fo r at least 3 h and strip o ff photoresist Rinse in D I H 20 and dry o ff using N 2 A n ultrasonic bath was used (w ith care) to aid lif t -o ff

• A ll contacts were annealed fo r 30 mm by a conventional graphite stop annealer (Appendix B ) in a flow ing form ing gas (5% H 2 + 95% N 2) ambient The Pd(50

* nm )/Sn(125 nm ) and Pd(50 nm)/Ge(126 nm) contacts were annealed at 330 °C,whereas the Pd(50 nm)/Sn(125 nm )/Au(100 nm) contacts were annealed at 300 °C

8.2.3 Level 3 - Schottky (Gate) contacts

Level 3, the most critica l step fo r device performance, involves the deposition o f gate m etallization between the source and dram contact pads The Schottky contact is composed o f A1 The gate length, LG, used fo r the fabrication o f M ESFETs are 2, 5 and 50 jam The gate-to-source distance, Las, is equal to the gate-to-drain distance, LGD, and fo r a ll M ESFETs LGs=LGD=2 jim The sequential process steps fo r th is level were as fo llow s• Spin on M icroposit S I818 photoresist diluted w ith EC solvent in the ratio o f 1 1 (by

volum e) on the Ohmic contact defined chip Th is ra tio was optim ised using test samples

• Soft bake at 115 °C fo r 5 m in and cool to room temperature• Soak in chlorobenzene fo r 3-4 mm and dry o ff only• Using a U V lig h t mask aligner and gate mask, expose the substrates fo r 20 s Expose

tim e was optim ised using test samples• Develop in 3 1 (by volum e) D I H 20 M icroposit M3 51 developer fo r ~45 s and then

clean in D I H 20 D ry o ff using N 2• A recess gate etch was performed in order to obtain a target pinch o ff voltage o f 5V

(Appendix D ) The fo llow ing steps were carried out in order to achieve a channel depth, d, o f 0 12 fim (120 nm)

■ A solution o f H20 2 N H 4OH D I H 20 in the ra tio o f 1 3 15 (by volume) was prepared and diluted w ith D I H 20 in the ra tio 1 10 Etch rate was checked using test pieces and the Tencor P rofllom eter Etch rate was ~24A/s

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■ A stop etch solution o f N H 4OH D I H20 m l 5 ra tio was prepared■ The substrates were placed in the etchant fo r 75 s in order to achieve

d= 0 12 (j.m■ Place m stop etch fo r 30 s■ Rinse in D I H 20 fo r 30 s and dry o ff using N 2

• The gate m etallization, A l, was sequentially cleaned in trichloroethylene, acetone, methanol and de-iomzed water (D I H 20 ), each fo r 10 m m and dried o ff using N 2

• P rio r to loading into an evaporator, the wafers were soaked in a solution o f D I H 20 HC1 (15 1 by volum e) fo r at least 2 mm and then b low dried using dry N 2 to remove native oxides

• A 250 nm A l gate m etallization was evaporated using a W co il in a resistance heating evaporator (Appendix A ) The base pressure was ~ 2x l 0‘6 T o rr and pressure during evaporation was between 3 0x1 O’6 T o rr and 4 0x10’6 To rr

• Leave the chips in M icroposit 1165 remover fo r at least 3 h and strip o ff photoresist Rinse in D I H20 and dry o ff using N 2 L ift-o ff was aided by careful use o f an ultrasonic bath

Surface m orphology o f the contacts was investigated using a Cambridge S360 SEM Conversion from Schottky to Ohmic behaviour o f the contacts was examined by I-V measurements The I-V characteristics o f the M ESFETs were determined using a T E K T R O N IX 576 curve tracer Contact res istiv ity was measured u tiliz in g the cTLM method


8.3.1 Ohmic contacts

The pc o f the Ohmic contacts are measured in a test pattern conform ing to the T L M (F ig 4 1), w ith pad spacing ranging from 2 to 128 (a.m The w id th o f the Ohmic pad, W, is 140 |im The transfer length method [12] is u tilized to measure pc values o f the contacts A ll Ohmic contacts are annealed fo r 30 mm It is assumed that the sheet resistance o f the semiconductor under the contacts, Rsh/, is equal to the sheet resistance o f the semiconductor in between the contacts, RM The average pc fo r 2 groups o f samples, w ith tw o samples in each group, were measured The Pd(50 nm)/Sn(125 nm) contacts show a pc o f 2 .2 8 x l0 "5 Q-cm2 at 330 °C, whereas fo r the Pd(50 nm)/Ge(126 nm) contacts this value is 2 84x1 O'6 Q-cm2 under the same annealing condition A pc o f 8 13x1 O’6 Q-cm2 is obtained at 300 °C fo r the Pd(50 nm )/Sn(125 nm )/Au(100 nm)

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contacts Under these conditions, contact resistances, Rc, o f the Pd/Sn, Pd/Ge and Pd/Sn/Au Ohmic contacts are 3 88Q, 1 41Q and 2 31Q , respectively

10 |im10 nm 10 jim 8Q ^m « - » (L0 + 4 ) (im

«— * ----------------------------- > — L010 (im

<= =»100 urn

Fig 8 1 Layout o f GaAs M E S FE T A lignm ent marks are not included

8.3.2 MESFET characterization

The layout o f the GaAs M E S FE T is shown in F ig 8 1 Level 4 (passivation level) was not used fo r th is characterization M ESFETs w ith gate lengths, LG, o f 2 (J.m, 5 (im and 50 jam were investigated in this study The dimensions o f the source and dram Ohmic pads is 100 ¡j.m x 100 fim M E S FE T characteristics were investigated under the gate metal as-deposited condition A ll M ESFETs operated in depletion mode. M ESFET transconductance, g m, and series resistance, Rs, were extracted from the I-V characteristics The Rs was measured in the linear region and was defined by

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( 8 . 1 )

whereas gm was measured in the saturation region and was defined by

DSS (8 .2)m dV,

where I ds = drain current and IDss = drain saturation current. Both R s and gm have a significant effect on the performance o f GaAs M ESFETs. Higher R s produces greater heat dissipation and larger voltage drop in the extrinsic parts o f the device, which in turn reduces the value o f I DS. The relationship between R s and gm is defined by

where gm(in t) is the intrinsic transconductance o f the device. As R s increases, gm

decreases as seen from eqn.(8.3). Any degradation in IDs and gm w ill have a corresponding effect on the speed o f the GaAs ICs [159]. In analog circuits, the small- signal voltage gain is directly proportional to gm [160].

F ig .8.2 compares the I-V characteristics o f the M ESFETs fabricated w ith Pd/Sn and Pd/Sn/Au metallizations fo r LG = 2 [im . It is seen that these characteristics exhibit looping behaviour (i.e., hysteresis o f drain current). It is believed that the looping phenomenon is attributed to slow transient behaviour o f deep traps present in semi- insulating substrates [161]. This type o f looping phenomenon in GaAs M ESFETs is also observed by other researchers [162-164], In the case o f Pd/Sn Ohmic metallizations (F ig .8.2(a)), /?s=107Q (linear, VGS=0V ) and gm= 107.1 mS/mm (VCS=-0.1V and VD5=0.94V) . For the Pd/Sn/Au metallizations (F ig .8.2(b)), Rs=52.63H (Vcs=0V). Due to the d ifficu lty o f viewing I-V characteristics at VG5=0V in the saturation region (F ig .8.2(b)), gm is calculated at VGS = -0 .8V and VDs = 0.76V. This value is 100 mS/mm. Generally, maximum gm (gmax) occurs around VGS = 0V . Therefore, gmax fo r this M E S FE T would, in all lik lihood, be greater than 100 mS/mm. The calculated gm values under different gate bias conditions fo r the above M ESFETs are shown in TABLE X V and TABLE X V I. From these tables, it is clear that the M E S FE T w ith Pd/Sn/Au'm etallization displays an improved gm when compared to the Pd/Sn contact.

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k(b)

F ig .8.2. I-V characteristics o f the M ESFETs fo r LG~2 (am w ith (a) Pd/Sn and(b) Pd/Sn/Au as source/drain contacts.

TABLE X V . Calculated gm values under d ifferent gate bias conditions fo r a M E S FE T w ith Lg =2 (im and Pd/Sn source/drain contacts (F D5=0.94V).

^GS(V) -0.1 -0.2 -0.3 o1 .-0.5(m S/m m ) 107.1 98.2 88.1 78.6 69.3

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TABLE X V I Calculated gm values under d ifferent gate bias conditions fo r a M E S FE T w ith Lg =2 (a.m and Pd/Sn/Au source/drain contacts (F Dy=0 76V )

VGS(V) -0 8 -1 0 -1 2 -1 4 -1 6gm (m S/m m ) 100 92 5 77 1 67 2 57 5

Fig 8 3 I-V characteristics o f the M E S FE T fo r LG=5 fj.m w ith Pd/Sn as source/dram contacts

Fig 8 3 shows the I-V characteristics o f the M E S FE T fo r LG=5 fim w ith Pd/Sn as source/drain m etallization A t VGf=0W, Rs=l 10Q For th is M E S FE T , g m values are calculated at VDf=0 78V and are shown in TABLE X V II The gmax occurs at VGS -0 IV which is 71 4 mS/mm

TABLE X V II Calculated gm values under d ifferent gate bias conditions fo r a M E S FE T w ith Lg =5 jam and Pd/Sn as source/drain contacts ( VDS=0 78V)

Vos (V ) -0 1 -0 2 -0 3 -0 4 -0 5 -0 6 -0 7 -0 8gm (m S/m m ) 71 4 69 6 69 0 67 0 64 3 60 7 56 1 51 5

A M E S FE T w ith Pd/Sn/Au as source/drain contacts yields R$= 109 22Q ( gsÔV) fo r Lg =5 (im (F ig 8 4) The gm values are calculated fo r VDS=0 78V and are shown in TABLE X V III The gmax occurs at Vgs~ -0 IV and is 64 3 m S/m m Therefore, M ESFETs w ith both Pd/Sn and Pd/Sn/Au source/drain contacts show almost identical Rs values at La =5 (am However, the Pd/Sn contact shows improved gm values when

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compared w ith the Pd/Sn/Au m etallization Th is result is somewhat surprising and this may be due to the production variations

Fig 8 4 I-V characteristics o f the M E S FE T fo r LG -5 p.m w ith Pd/Sn/Au as source/drain contacts

TABLE X V III Calculated gm values under d ifferent gate bias conditions fo r a M E S FE T w ith Lg =5 |am and Pd/Sn/Au as source/drain contacts (VDS=0 78V)

Vg sW -0 1 -0 2 -0 3 -0 4 -0 5 -0 6 -0 7gm (m S/m m ) 64 3 60 0 54 3 50 0 45 7 42 9 40 8

A M E S FE T w ith LG =50 (im and Pd/Sn as source/drain contacts yields a ^?^505Q at F ^ O V The I-V characteristics fo r th is M E S FE T is shown m Fig 8 5 TABLE X IX summarizes gm values at d ifferent gate bias points fo r VDS=\ 89V The gmax

is 20 8 m S/m m (VGf =-0 IV , VDS= l 89V) For Pd/Sn/Au m etalliza tion (F ig 8 6), the calculated Rs is 485Q at V G5=0V The gm data are calculated at VDS=2V and are shown m TABLE X X The gmax is 22 2 m S/m m (F Gy=-0 IV , VDS=2V) w hich is s lig h tly higher than that o f the Pd/Sn contacts (TABLE X IX )

TABLE X IX Calculated gm values under d ifferent gate bias conditions fo r a M ESFET w ith Lg =50 |_im and Pd/Sn as source/drain contacts ( VDS= 1 89V)

VGS(V ) -0.1 -0 2 -0 3 -0 4 -0 5 -0 6 -0 7 -0 8gm (m S/m m ) 20 8 194 194 19 1 18 3 18 1 179 16 9

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Fig 8 5 I-V characteristics o f the M E S FE T fo r LG =50 (j.m w ith Pd/Sn as source/drain contacts

Fig 8 6 I-V characteristics o f the M E S FE T fo r L G=50 jim w ith Pd/Sn/Au as source/drain contacts

TABLE X X Calculated gm values under d ifferent gate bias conditions fo r a M ESFET w ith La =50 (am and Pd/Sn/Au as source/drain contacts ( VDS=2V)

Vg sOO -0 1 -0 2 -0 3 t o I o -0 6 i o -j

gm (m S/m m ) 22 2 20 8 20.4 194 189 18 1 173

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A lthough M ESFETs were fabricated w ith Pd/Ge m eta lliza tion fo r La =2 fim , the I-V characteristics were very poor and hence om itted from th is study For Lc=5 (am, the I-V characteristics fo r the M E S FE T fabricated w ith Pd/Ge as source/drain contacts is shown in F ig 8 7 A t VGS=0V, Rf=49 71Q The gm values are calculated at VDS= l 89V and are shown in TABLE X X I The measured gmax has a broad peak and is 92 9 mS/mm A t VDS= l 89V, the I-V curve is not in the saturation region fo r VGS= OV For th is reason, gmax occured at d ifferent Vgs The calculated Rs is better than that o f the Pd/Sn and Pd/Sn/Au contacts I t is believed that this improved Rs is due to the low er Rc w ith the Pd/Ge contacts (Section 8 3 1) Th is may also be due to production variations However, the Pd/Ge m etallization also produces a better gmax than that o f the Pd/Sn and Pd/Sn/Au contacts

Fig 8 7 I-V characteristics o f the M E S FE T fo r LG =5 (am fabricated w ith Pd/Ge as source/dram contacts

T a b l e X X I Calculated gm values under d ifferent gate bias conditions fo r a M ESFET w ith Lg =5 (im and Pd/Ge as source/drain contacts ( VDS= 1 89V)

VGS (V ) -0 5 -1 0 -1 5 -2 0 -2 5 l o

gm (m S/m m ) 92 9 92 9 90 5 85 7 80 0 73 3

For the M E S FE T w ith LG =50 (am and Pd/Ge as source/dram contacts, Rf=316Q at VGS=0V The gm parameters are calculated from the I-V curve o f F ig 8 8 at VDS=\ 34V and are summarized in TABLE X X II. The gmax is 15 3 m S/m m at VGS=-0 5V which is comparable to that o f the M ESFETs fabricated w ith Pd/Sn and Pd/Sn/Au contacts at the same VGS (TABLE X IX & TABLE X X )

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Fig 8 8 I-V characteristics o f the M E S FE T fo r LG =50 |im w ith Pd/Ge as source/drain contacts

TABLE X X II Calculated gm values under d ifferent gate bias conditions fo r a M E S FE T w ith Lg =50 |im and Pd/Ge as source/drain contacts {VD \ 34V)

V asC n -0 5 -1 0 -1 5 -2 0gm (m S/m m ) 15 3 14 6 13 7 12 3

The gate I-V characteristics ( i e IGS vs VGS) are almost identical fo r a ll m etallizations Fig 8 9 shows th is characteristic fo r the Pd/Sn source/dram contacts w ith Lg =2 |um Diode behaviour is expected and it is observed The VF at which diode current starts to increase from its zero value is ~0 5V

Fig 8 9 Gate leakage I-V characteristics, l e IGS vs. VGS

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F ig .8.10. SEM micrographs o f the source/drain and gate m etallizations: (a) Pd/Sn,(b) Pd/Sn/Au, (c) Pd/Ge and (d) A l.

SEM micrographs o f the source/drain and gate m etallizations are shown in F ig .8.10. The Pd/Ge m etallization (F ig .8 .10(c)) exhibits smooth surface morphology compared to the Pd/Sn contact (F ig .8 .10(a)) and is s lig h tly better than the Pd/Sn/Au m etallization (F ig .8 .10(b)). The as-deposited A l gate m etallization also displays smooth surface m orphology (F ig .8 .10(d)). A typical M E S FE T w ith a LG =5 |am and Pd/Sn as source/drain contacts is shown in F ig .8.11. The contact edges and alignm ent accuracy fo r 2 jam M ESFETs w ith d ifferent source/drain m etallizations are shown Fig.8.12, Fig.8.13 and F ig .8.14. M orphological characteristics display a significant effect on contact edge un ifo rm ity. For a ll M ESFETs, gate m etallization shows smooth and un iform contact edges. The contact edges are poor fo r the Pd/Sn m etallization (Fig.8.12) and are due to the rough surface morphology. The m axim um amplitude o f this undulation is ~0.65 p.m. Improved surface morphology produces better edge un ifo rm ity fo r the contacts. It is obviously better fo r the Pd/Sn/Au m etallization (Fig .8.13) and is -0 .1 0 fim . A lthough the edge un ifo rm ity fo r the Pd/Ge contact is very good and the undulation is v irtu a lly impossible to measure, this m etallization system exhibits a slight lif t - o f f problem as seen in F ig .8.14.

112

Fig 8 11 SEM micrograph o f a typical M E S FE T device showing Gate, Source and Dram regions and also some alignm ent marks

Fig 8 12 SEM micrograph showing alignment accuracy and edge un ifo rm ity o f a M E S FE T fabricated w ith Pd/Sn Ohmic contacts fo r LG = 2 p.m

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Fig 8 13 SEM micrograph showing alignment accuracy and edge un ifo rm ity o f a M E S FE T fabricated w ith Pd/Sn/Au Ohmic contacts fo r LG = 2 (im

L * S£1 £HT = ¿0 . 0 i;v WD* 24 ran flftG= :i 1. ?u Y FHLIT0® 314177

S 5 ?h¿O.Ouft h — ----------1

Fig 8 14 SEM micrograph showing alignment accuracy and edge un ifo rm ity o f a M E S FE T fabricated w ith Pd/Ge Ohmic contacts fo r La - 2 p.m

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8.4 Conclusion

GaAs M ESFETs have been fabricated w ith Pd/Sn, Pd/Sn/Au and Pd/Ge m etallizations as source/drain Ohm ic contacts M ESFETs w ith gate length o f 2 }im , 5 |a.m and 50 fim are investigated M ESFETs w ith Pd/Sn/Au m etallizations show improved characteristics compared to Pd/Sn contacts A lthough M ESFETs w ith Pd/Ge m etallizations were fabricated fo r LG- 2 jam, the I-V characteristics were very poor and thus om itted from th is study

The gate length, LG, appears to have significant impact on Rs Th is is due to the increase in channel resistance w ith an increase in LG [165] gm decrease w ith increasing Lg (eqn 8 3), as expected The Pd/Ge m etallization displays s lig h tly better R s and gm

values compared to the Pd/Sn/Au m etallization at LG=5 jxm

M orphological characteristics have a significant impact on the edge un ifo rm ity o f the contacts Sharp edge d e fin ition /un ifo rm ity o f the source/drain m etallizations is necessary fo r V L S I GaAs devices Improved m orphology im plies better edge d efin ition The edge d e fin ition o f source/drain contacts fabricated w ith Pd/Sn/Au m etallization is better than that o f the Pd/Sn m etallization The Pd/Ge contacts show s lig h tly improved surface m orphology when compared to Pd/Sn/Au m etalliza tion However, the edge defin ition o f the Pd/Sn/Au m etallization is comparable to that o f the Pd/Ge contacts

115

CHAPTER 9

Conclusions and suggestions for future research

9.1 Conclusions

The m ain objective o f this study was to develop and characterize a novel Pd/Sn Ohmic contact system to n-GaAs fo r use in m icrowave, optoelectronic and low-dim ensional devices The proposed Ohmic contact system has been developed and system atically and extensively characterized usmg Scanning Tunneling M icroscopy (S TM ), Tencor Surface P rofilom etry, Scanning Electron M icroscopy (SEM ), Energy Dispersive Analysis o f X-rays (E D A X ), Secondary Ion Mass Spectrometry (S IM S ) and Current- Voltage (I-V ) measurements Contact resistiv ities, pc, o f the proposed m etallizations were measured u tiliz in g a conventional Transm ission L ine M odel (cTLM ) method

In itia lly , Pd and Sn evaporation rates were optim ized fo r better surface morphology o f the contacts usmg STM The effects o f Sn to Pd thickness ratio (m ) on the properties o f Pd/Sn m etallizations were also presented Annealing cycles were optim ized fo r m inim um values o f pc Proper choice o f two-step annealing cycles m arginally improves morphological and electrical characteristics o f the contacts B ut it does not change contact abruptness A lthough it is postulated that the Ohmic contact form ation mechanisms o f the Pd/Sn m etallizations undergo solid-phase reaction (F ig 4 8), the non-alloying behaviour could not be confirm ed due to S IM S insensitiv ity as described in Section 4 4 5

The effects o f A u overlayers on the properties o f Pd/Sn Ohmic contacts, l e the properties o f Pd/Sn/Au m etallizations were also analysed I t is seen that a judicious choice o f A u overlayers improves the characteristics o f the Pd/Sn contacts A n overlayer o f A u also changes the annealing cycles at the m inim um pc points B oth Pd/Sn and Pd/Sn/Au Ohmic contacts are very adhesive to the substrates The Pd/Sn and Pd/Sn/Au m etallizations are more abrupt than the alloyed five-layer A u /G e /A u /N i/A u contacts

A comparison has also been made between the electrical and morphological characteristics o f the Pd/Sn, Pd/Sn/Au, non-alloyed Pd/Ge and alloyed eutectic

116

A u-G e/N i and N i/A u-G e/N i contacts. The Pd/Sn Ohmic contacts show almost identical pc values when compared w ith alloyed Au-G e/N i contacts. However, morphological characteristics o f the Pd/Sn m etallizations are even better than those o f alloyed A u-G e/N i and N i/A u-G e/N i contacts at the lowest pc conditions. The Pd/Sn/Au Ohmic contacts display comparable pc values to the non-alloyed Pd/Ge m etallizations w ith only a s lig h tly deteriorated surface. The electrical and m orphological properties o f the Pd/Sn/Au m etallizations are much better than those o f alloyed Au-G e/N i and N i/A u - G e/N i contacts.

One o f the most im portant criteria fo r an Ohmic contact is its thermal stab ility. No significant change in surface morphology is observed fo r the Pd/Sn and Pd/Ge m etallizations after annealing at 410 °C fo r 10 h. The Pd/Sn m etallizations exhib it excellent therm al stab ility at 410 °C when compared to the non-alloyed Pd/Ge m etallizations. Even the Pd/Sn/Au m etallizations show better therm al stab ility at this temperature than that o f non-alloyed Pd/Ge contacts w ith a s lig h tly deteriorated surface morphology. Therm al stab ility o f the five-layer alloyed A u/G e/A u/N i/A u Ohmic contacts is almost identical to that o f the Pd/Sn/Au m etallizations. However, the Pd/Sn/Au Ohmic contacts display improved therm al stab ility when compared to the alloyed Au-G e/N i and N i/A u-G e/N i m etallizations w ith a better surface morphology.

A n analysis o f the long-term stab ility o f the Ohmic contacts was carried out at 300 °C. The non-alloyed Pd/Ge m etallizations show better long-term stab ility than the Pd/Sn contacts. No change in surface morphology is observed fo r the Pd/Sn and Pd/Ge m etallizations after annealing at 300 °C fo r 400 h. A lthough Pd/Sn/Au m etallizations m aintain pc values which are sligh tly higher than those o f alloyed A u-G e/N i, N i/A u - G e/N i and A u/G e/A u/N i/A u m etallizations, no singificant m orphological change is observed w ith Pd/Sn/Au conatcts after having been annealed at 300 °C fo r 400 h. A t this temperature, the pc values o f the Pd/Sn/Au m etallizations are on ly s lig h tly higher than those o f non-alloyed Pd/Ge contacts.

F in a lly , GaAs M ESFETs have been fabricated using Pd/Sn and Pd/Sn/Au m etallizations as source/drain contacts. Non-alloyed Pd/Ge Ohmic contacts have also been utilized to fabricate GaAs M ESFETs. M ESFETs w ith gate lengths o f 2 (am, 5 (im and 50 jam were investigated.

The m orphological characteristics o f the source/drain and gate m etallizations impose an ultim ate lim it on gate-to-source and gate-to-drain separations (LGS & LGD).

Improved m orphology im plies sharper edge defin ition fo r the contacts. Surface

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m orphology o f the non-alloyed Pd/Ge m etallizations is better than that o f Pd/Sn m etallizations The Pd/Ge m etallizations also display s lig h tly improved surface m orphology when compared to the Pd/Sn/Au contacts A lthough, edge d efin ition fo r the Pd/Sn/Au source/drain contacts is comparable to that o f non-alloyed Pd/Ge m etallizations, Pd/Ge contacts tend to exhib it imperfect metal lif t - o f f

Therm al stab ility o f the Ohmic contacts at a device processing temperature (400 °C) is o f serious concern One o f the most im portant reasons fo r developing non- alloyed Pd/Ge Ohmic contacts was to overcome the therm al instab ility o f the conventional alloyed Au-G e/N i m etallizations A lthough, non-alloyed Pd/Ge m etallization offers somewhat better electrical and m orphological properties, thermal stab ility o f th is contact system s till require further studies The new ly developed Pd/Sn Ohmic contacts display better therm al stab ility at 410 °C when compared to the non- alloyed Pd/Ge m etallizations A t this temperature, therm al stab ility o f Pd/Sn/Au m etallizations is also better than that o f non-alloyed Pd/Ge contacts w ith a slightly deteriorated surface morphology Therm al stab ility o f Pd/Sn/Au Ohm ic contacts is much better than that o f alloyed A u/G e/A u/N i/A u, Au-G e/N i and N i/A u-G e/N i m etallizations The analysis o f long-term stab ility at 300 °C shows that both Pd/Sn/Au and Pd/Ge m etallizations have almost identical stab ility at th is temperature The longterm stab ility o f Pd/Sn/Au m etallizations is much better than that o f alloyed A u/G e/A u/N i/A u , Au-G e/N i and N i/A u-G e/N i contacts w ith a improved surface m orphology Therefore, therm ally stable Pd/Sn and Pd/Sn/Au m etallizations provide prom ising candidates fo r future GaAs devices

118

9.2 Suggestions for Future Research

For future research w ith Pd/Sn and Pd/Sn/Au Ohmic contacts, the fo llo w in g suggestionsare made

• X -R ay D iffrac tion (X R D ) method could be employed in order to investigate the non-alloying behaviour o f the contacts This measurement w ill also determine the phase form ation o f the m etallizations

• Transm ission Electron M icroscopy (T E M ) w ill show the metal/GaAs interface w hich w ill indicate the spiking or non-spiking nature o f the contacts

• A Rapid Therm al Annealer (R T A ) could be employed fo r contact form ation This should improve the overall characteristics o f the contacts

• Auger Electron Spectroscopy (A ES) could determine the actual depth profiles o f the contacts as S IM S cannot indicate real profiles (Section 4 4 4)

• For fabrication o f GaAs M ESFETs in the sub-fj.m range u tiliz in g these m etallizations, electron beam evaporation o f metals is recommended

119

References

[1] A . Bariev, Semiconductors and Electronic Devices, Prentice H a ll, 3rd Ed., Chap. 16 & Chap.22, 1993.

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133

Appendix A

Resistance heating (Thermal) evaporator

A n Edwards Coating System E306A (Fig A l ) was used as a resistance heating (thermal) evaporator for the deposition o f metallizations on the GaAs substrates In itia lly , the whole system was disassembled and chemically cleaned using tnchloroethylene, acetone, methanol and de-iomzed water (D I H 20 ) A n ultrasonic bath was used for the cleaning o f small parts A ll parts were then dried m the fume hood The system was then reassembled

Protective jar

Vacuum chamber

Liquid N 2 inlet port

Control lever

Pirani gauge

Penning gauge

Power control knob

F ig A l Photograph o f Edwards Coating System E306A indicating some o f the components

A l

In itia lly , the system had only one evaporation source This source was a low tension (L T ) source and was not sufficient for the evaporation o f Pd A fte r some modification o f the system, a second evaporation source (high tension, H T) was connected F ig A 2 shows the H T transformer, L T transformer, rotary pump and diffusion pump A fte r reassembling, the m inim um base pressure was 2x10' Torr

Fig A2 Photographs o f resistance heating evaporator indicating H T transformer, L T transformer, rotary pump and diffusion pump

A close-up o f the base plate o f the system is shown m Fig A3 W boats were used fo r the evaporation o f a ll metals, except A1 For A l evaporation, a W coil was used The system has three shutters The substrate shutter was used to isolate the substrates from the source when outgassing o f the system occurs The second shutter, known as the crystal shutter, was used w ith the crystal thickness m onitor The third shutter, known as the source shutter, was used to isolate the H T and L T boats so that metal inter-m ixing does not occur

A2

Fig A3 Detailed photograph o f base plate o f the evaporator Shutters and other components are indicated

A3

Appendix B

Graphite strip annealer

The graphite strip annealer is shown in Fig B1 The main components o f the annealer are a rotary pump, transformer, thermocouple w ith monitor, annealing chamber, cooling water system and annealing ambient The system is new ly designed and built Forming gas (5% H 2 + 95% N 2) i s used fo r the annealing ambient A valve (Fig B l) is used to isolate the pump from the annealing chamber during annealing

Thermocouple monitor

Annealing chamber

Forming gas cylinder

Speedy valve

Power control transformer

Water cooling system

Transformer

— Rotary pump

Fig B l Photograph o f the graphite strip annealer indicating mam components

A close-up o f the base plate is shown m Fig B2 The graphite strip is held by the water cooled power ports The middle o f the graphite strip is thinned and its surface area is reduced to achieve higher temperature A small hole is drilled in this thinned region fo r the thermocouple Samples are placed next to this hole so that accurate sample temperature is monitored The rate o f temperature rise is ~10 °C/s up to 400 °C and above 400 °C this rate falls slightly The temperature fa ll rate is higher than the rise rate and is -1 2 °C/s up to 200 °C Below 200 °C, this fa ll rate reduces The maximum attainable temperature o f this annealer is 550 °C

Bl

Forming gasinlet port Substrate

Fig B2 Photograph o f base plate o f the graphite strip annealer indicating various components

B2

Appendix C

Original STM photographs of the Pd/Sn contacts to GaAs(SI)

ci

'i 'i i ' . l inn n .nniii i n 11,n o n i i i .n i in n n

Sample A (as-deposited)

h ] l im n '‘ " ' I tf 'H M

Sample \(2 0 0 °C 10 mm)

Fig 3 2 Onginal STM photographs ot sample \

c:

I I r u n i I H | I l H I I I

I, I 1

' ' i 1 H i m ti i i i i i i h ii 11 l i n n it i i n i i i i t i i

Sample E (as-deposited)

u m j I f n u i AnqMrum

l.dlUtU \\

1MIIII1 II

iiiunii 0

‘ . n u n it

!.%(]

" " I M M I I I I I t d l U U ! II 4 > , m i l l II l . l i m m (I

Sample E (200 C lO m in)

2 Onginal STM photographs of sample E

C3

n*| If I l fH im| t r 41f11

1 S0I HI I)

.111100 0

‘ . m m (i

(»‘ISO

i 1 o i i i i o m o n o ii 1 S I I O O II I . OI tl l l l (I

Sample G (as-deposited)

im ] Im in tin ] l im n

m u m ii

1S0I MI I)

iiniiii) 0

Mum n

b'M/

I M i n n I! . i in i i i i ii v h i h i i i i i i n i i i i i i

Sample G (200 (C. 10 mm)

3 Original STM photographs ot sample G

C4

UJ

I • 11 ir iin

\ iH

> 1 i ' m m ti l i m i l i i l 1 M H I I I n t u m i l i ii

i n ] I m i t i

l im ili n

Sample H (as-deposited)

m| tmni

hbH‘i

l imili ii

m m it

' ' I i 1 m in i i it 1‘ m in ii i m u m ii

Sample H ( 200 1C 10 m in )

Original STM photographs ot sample H

C5

| M | I f ' I K , i m | I r « I < 11

Sample E (350 °C 10 m in)

1 MII II I II

ì h d i i i i il

M im i il

" " i m m u n i i m m i l l i i m i i i i i il m i i i i i i i ii

Sample E (400 C 10 min)

5 Original STM photographs of sample E

C6

t.1. ' i

ii

f l i t i t i

t, « M /

UJ

ml trulli A n i j f r i n i i

1MI I I I I II

u l t i mi li

i Mimi il

il il

1 1 'i i ' . i n n i il i n f l ui i li 1 S I I I HI il i . l i mi l i ii

Sample H (350 °C, IO m in)

ui| (min

> m im i il

i m h i i i il

m im i it

i1 nini il

i '•■mu <1 m im i il 1M IIH I ii i . i ium i

Sample H (400 C 10 min)

5 Original STM photographs of sample H

C7

694/

II

t r o n i

M i l l i

jm| irnin « I I I ) 1 ( 4 1 * 1 »

Sample A (350 °C, 10 mm)

in ) tru tt i M , l, l

t ' 'W i l l II MIIIIMI II 1M IIII) II I * t IIIII11 II

Sample A (400 °C. 10 mm)

Fig 3 6 Original STM photographs ot sample A

CS

Appendix D

Calculation of pinch off voltage

The relationship between the pinch o ff voltage, VP, and the channel depth, d, is given by

d = 2 e t( y , + y fl)

i q N D

where es = intrinsic perm ittivity = 13 1 x 8 85 x 10 12 F/m VB= B u ilt in potential = 0 8V q = electronic charge = 1 9 x 1 0 19C Nd = donor concentration = 5 0 x 1023 m '3

Thus when ¿ = 01 2 (xm, VP = 5 V

DI

Appendix E

Publications based on this work

1 M S Islam, P J McNally, D C Cameron and P A F Herbert, "The Importance of the Pd to Sn Ratio and Annealing Cycles on the Performance of Pd/Sn Ohmic Contacts to n-GaAs," Thin Solid Films, 1996 (in press)

2 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Effects of Au Overlayers on the Electrical and Morphological Characteristics of Pd/Sn Ohmic

- Contacts to n-GaAs," Thin Solid Film, 1996 (m press) (presented at the Int Conf onMetallurgical Coatings and Thin Films (ICMCTF’96), San Diego, CA, USA, 22-26 April 1996)

3 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Comparison of Pd/Sn and Pd/Sn/Au Thin-Film Systems for Device Metallization," Mater Res Soc Symp P r o c , Vol 427, 1996 (Mater Res Soc (MRS) 1996 Spring Meeting, San Francisco, USA, 8-12 April 1996) (in press)

4 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Ohmic Contacts to n-type GaAs made with Pd/Sn and Pd/Sn/Au Metallizations," Proc o f the 8th Mediterranean Electrotechnical Conf (melecon '96), Ban, Italy, 13-16 May 1996, pp 385-388

5 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Effects of Annealing Cycles on the Electrical and Morphological Characteristics of Pd/Sn Ohmic Contacts to n-GaAs," Proc o f the 8th Mediterranean Electrotechnical Conf (melecon '96), Bari, Italy, 13-16 May 1996, pp 1294-1297

6 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Characterization of Pd/Sn Ohmic Contacts on n-GaAs using Electrical Measurements, EDAX and SIMS," Proc o f the 3rd IEEE Int Workshop on High Performance Electron Devices fo r Microwave and Optoelectronic Applications (EDMO'95), King's College London, UK, 27 November 1995, pp 26-31

7 M S Islam, P J McNally, D C Cameron and P A F Herbert, "A Novel Pd-Based Ohmic Contact System for n-type GaAs A Structural, Morphological and Electrical Investigation," Proc o f the 6th European Conf on Applications o f Surface and Interface Analysis '95 (ECASIA'95), Montreux, Switzerland, 9-13 October 1995, published by Wiley & Sons, pp 299-302

8 M S Islam, P J McNally, D C Cameron and P A F Herbert, "Properties o f Pd/Sn Ohmic Contacts to n-GaAs," Proc o f the Int C onf on Advances in Materials and

El

Processing Technologies '95 (AMPT'95), Vol I, Dublin City University, Ireland, 8-12 August 1995, pp 40-49

9 M S Islam, P J McNally and D C Cameron, "Palladium-Based Ohmic Contacts to n-type GaAs- A Review of Recent Advances," Proc o f the Int C onf on Advances in Materials and Processing Technologies '95 (AMPT'95), Vol I, Dublin City University, Ireland, 8-12 August 1995, pp 18-29

10 M S Islam, P J McNally and D C Cameron, "Thermal Stability of the Pd/Sn and Pd/Ge Ohmic Contacts to n-GaAs,” Int Conf on Metallurgical Coatings and Thin Films (ICMCTF’97), San Diego, CA, USA, 21-25 April 1997 (submitted)

E2

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