Thermo-Mechanical ReliabilityAssessment of TSV Die Stacks byFinite Element Analysis
Dr. Roland Irsigler, Siemens AGCorporate Technology, CT T P HTC
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 2
Outline
�TSV application�FEA modeling appoaches�Material parameter set�TSV FE/BE build-up process� Impact of TSV geometry on internal die
level stress �Regions of critical loading�Packaging related stress on TSVs�Options to lower the risks�Summary
SOLID µBump
Stacking
TSV
Packaging
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 3
TSV Application: DRAM
Via Ø5-10 µm
Signal PadPower Pad
Dummy Pad
TSV-Interconnect Chip (UP-TV) TSV´s
DRAM wafer
TSV-Testvehicle
SOLID Interconnect TSV stack (4-fold)
TSV-Package
Benefits:
Challenges:
• memory/volume• low parasitics
• new technology• new equipment• cost, yield• reliability
12,4 mm
8,0
mm
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 4
FEA modeling approaches
Global/Submodel approach3D via model2D via model
Cu
W
Si
Polymer
Ti/Cu
Cu
SiO2
WCu
SiO2
Al
Ti/CuCu
• rotatio symmetry• periodic bounderies• variation in:- via diameter & pitch- layer thickness- material set
• full 3D model• variation in:- via shape, dimensions- via arrays- pad geometry
• fixed material set• include build-up process flow
• 3D model of complete TSV-package• boundary conditions for TSV submodelare determined by the global model
• variation in:- # of dies/stack- package construction
FraunhoferInstitutZuverlässigkeit undMikrointegration
IZM
Symmetric BCSymmetric BC
Coupled x – DOFs
Coupled z – DOFs
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 5
Material Regions and Dimensions3D – FE quarter Cu-Via model with circular via cross section
*Coupled degrees of freedom of the nodesat the outside area
Via Ø 10 µm
15 µm
17 µm
30 µm
Dielectric layeropening
Al-pad
Cu-pad
SiOSiO2, 2, 1,5 1,5 µµm m
Cu, Cu, ØØ10 10 µµmm
Polymer, Polymer,
herehere 1 1 µµmm
Si, 50 Si, 50 µµmm
Al, Al, 850 nm850 nm
Ti/Cu, Ti/Cu, 50/150 nm50/150 nm
Cu, 4 Cu, 4 µµmm
Sn, 2 Sn, 2 µµmm
Cu, 4 Cu, 4 µµmm
SiOSiO2, 2, 100 nm 100 nm
Coupled z – DOFs*
top region
bottom region
Pad of next die
Pad of next die
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 6
3D Global Stacked Die Model and Submodelling
Via region
Interconnect side view
Top CuTop Cu--padpad
Bottom CuBottom Cu--padpad
Bottom die
Top die IMC IMC CuCu33SnSn
Submodel: single via
Simplified die global model
global-local
matching
At the so-called cut boundaries the displacements, which were calculated in the global model, are extrapolated on the finer mesh of the submodel.
Global model: 8 –fold stack in package
Package warpage
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 7
Material Parameter Set
• Thin film material parameter can differ significantly from bulk material parameter• They can also depend on the deposition process and the source chemistry• Measurements on dedicated testsamples required
*Microelectronics Packaging Materials Database developed at Purdue University, Center for Numerical Data Analysis and Synthesis (CINDAS) under the Sponsorship of Semiconductor Research Corporation (SRC), Version 2.32, 1999
Micro Materials CenterBerlin and ChemnitzHead: Prof. B. Michel
Material Constitutive law
(Instantaneous-) E-Modulus [MPa]
Poissons ratio
CTE [1/K]
Initial yield stress [MPa]
Source
Chip Elastic 168,000 0.30 2.8 10-6 Normally used for Si <100>
SiO2-Passivation
Elastic 72,000 0.20 1.7 10-6 Normally used in semiconductor fabrication
SixN4-Passivation
Elastic 160000 0.20 2.1 10-6 Normally used in semiconductor fabrication
Al-Pad Elastic-plastic 70,000 at 233 K
50,000 at 523 K
0.32
24 10-6 σ0: 210;Etan: 4000 at 233K σ0: 180;Etan: 5000 at 523K
CINDAS
W-via
Elastic-plastic 210,000 at 233 K
180,000 at 523 K
0.32
4.5 10-6 σ0: 3100;Etan: 6900 at 233K σ0: 2810;Etan: 6900 at 523K
(after Nanoindentation and simulation)
Cu-via/Cu-pad
Elastic-plastic 103,000 at 233 K
83,000 at 673 K
0.35
17 10-6 σ0: 410;Etan: 1090 at 233K σ0: 350;Etan: 1090 at 553K
(after Nanoindentation and simulation updated)
Ti/Cu Elastic-plastic 110,000 at 233 K
90,000 at 523 K
0.31
15 10-6
σ0: 540;Etan: 16000 at 233K σ0: 450;Etan: 7353 at 523K
CINDAS
WPR Viscoelastic,
Tg=100 °C
4,200 at 218 K
2,800 at 423 K
0.3
0.32
45 10-6 < 373K
85 10-6 > 373K
Shear:a1: 0.0351; a2: 0.0659 at t1: 45.68; t2: 914.64
Measured in previous project
IMC Cu3Sn Elastic-plastic 115,000 0.32
19 10-6 σ0: 400 Applied in previous projects
BacksidePolymer
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 8
TSV build-up process
• The process steps up to the starting point (initial condition) can be neglected in the FE analysis because only elastic strains occur• Process steps with elastic-plastic conditions were realized as loading steps with fictive time scale. • Layer is stress free at deposition temperature. Non-thermal intrinsic stress (e.g. chemical shrink) were not considered. • The first time step with real process time becomes effective after the deposition of the viscoelastic polymer at the wafer bottom due to its time dependent properties.
Process Flow I
0
50
100
150
200
250
300
350
400
450
0 5 10 15 20 25
Time [s]
Pro
cess
tem
pera
ture
[°C
]
depositionhard passivationupside
Adjusting Cu deposition T
Initial condition
Heating up to polymer deposition
Al-layer deposition
Process step
Process Flow II
0
50
100
150
200
250
300
20 1020 2020 3020 4020 5020
Time [s]P
roce
ss te
mpe
ratu
re [°
C]
Polymer deposition
Ti/Cu depositionupside andbackside
Resistdeposition
Polymer etch
Cu plating and
backside
Resist strip
Ti/Cu etch
upside
Process Flow III
0
50
100
150
200
250
300
20 1020 2020 3020 4020 5020
Time [s]
Pro
cess
tem
pera
ture
[°C
]
Heating up to 270 °Cand adding Cu 3Snsolder
Reflow soldering and cooling
Molding -cooling to RT
Ti/Cu etch
Visco-elastic conditionsElastic-plastic conditions „Packaging“Wafer/die level Package level
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 9
Single step vs. TSV build-up process results
1Equivalent plastic strain
after an intermediate step of the processing sequence
Al
after one “equivalent”cooling step
active elements
Max. 1.9 % Max. 3.9 %
Deactivated (dead)elements
• effects of the process steps have to be modeled adequately• differences in stress and strain distribution patterns as well as in their amplitudes are obvious• single-step approach even fails qualitatively.
TSV / Padinterface edge
CuW
SiO2
CuW
SiO2
Al
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 10
Schematic representation of results and tendencies
Results afterprocess flow 2
Ø 2,5 µm
Ø 15 µm
<1 µm10 µm
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 11
Results from 2D and 3D Modeling
Maximum stress values in Si and Cu
circ.TSV arrays Single rect. TSV´s
5x1 via array
13 via array
10x10 via
10x20 via
10x40 via
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 12
Regions of stress concentrations (Indicator: v.Mises stress and equiv. plastic strain) in the via structure independent of the via shape, dimension, and the level of modeling
2D Model
3D Model
Εpl,eqv
Seqv [MPa]
Al-pad
Al-pad
Top region Bottom region
Al-pad
Al-pad
Cu
CuCu Si
Si
SiCu
CuCu pad
Cu pad
Top region, Al Pad
Si
Si
Polym.
SiO2
W
W
SiO2
SiO2
Regions of critical loading
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 13
FE modeling procedure to include process flow 3 (“p ackaging”)
Create submodel (TSV) Create global model (package)
Deposition temperature is stress free (reference) temperature
Write cut boundary nodes
Execute cut boundary interpolation for
molding step
Delete boundary conditions set for build-up
Save submodel
CalculationSequential building of the TSV structure up to molding
temperature 180 °C
CalculationMolding 180 °C to RT
Set cut boundary DOF specificationsfor molding-step
CalculationMolding 180 °C to RT
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 14
Via loading depending on the number of Si-chips in the stack
Z – displacements [µm] of the global model
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 15
Results after process flow 3 (“packaging”)
New quality and quantity of stress loading for the via structure after the inclusion of soldering and molding in the sequence of the build-up process
The via is located at the edge of a 4fold stack in package in the 2nd die from bottom of.
εεεεpl,eqvDisplacement scaling: 3x
Si
Cu
WPR
SiO2
Cu pad
Top region Bottom region
Cu
Si
Polym.
Cu-Pad
Si
Cu-Pad
Factor 6 higherthandie levelstress!
tilt and shear!
Max. stress moved to outeredge of Cu pad
1% higher
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 16
Results after process flow 3 (“packaging”)
Top region
Bottom region
Plastic straining is induced at the via bottom region, which accumulates during thermal cycling � Cu fatigue risk
Sz [MPa]
Cu-via filling
εpleqv
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 17
0
500
1000
1500
2000
2500
72 36 18 3.6 3.1
Young's Modulus of Bottom Insulator Film [GPa]
van-
Mis
es S
tres
s [M
Pa
]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Pla
stic
Str
ain
per
T
herm
al C
ylce
[%]
Stress in ViaPassivation
Plastic Strain inthe Cu Via
InitialDesign
PI
SiO2
Impact of bottom isolation layer material substituti on
Temperature Cycle: 125°C � -55°C
A more rigid bottom isolation layer can lower stresses and strains in the TSV bottom region
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 18
Impact of underfiller between dies
Seqv [MPa]Seqv [MPa]
Package without underfilling Package with underfilling
Sz [MPa]Cu
Sz [MPa]Cu
Si
Seqv [MPa]
SiSeqv [MPa]
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 19
Summary
General:
• TSV process temperature sequence has to be modeled adequately to identifycritical regions and stress levels.
• Thin film material parameter needs to be determined properly � measurements
Die level:
• No clear failure risk for all simulated variants of via shapes found.
• Circuar vias and via arrays show less stress in Si than single, rectanular vias
• Local stress concentrations are Cu/SiO2/Al at the top region and Si/SiO2/Polymer at the bottom region.
Package level:
• No clear failure risk at via top region identified
• Clear failure risk on via bottom region due to the low stiffness of the polymer layer.
• Use of rigid bottom isolation layer or underfill significantly reduces stress at the via
Corporate Technology, CT T P HTC2010/03/16 Dr. Roland Irsigler,Page 20
Contact
Dr. Roland IrsiglerSiemens AG, CT T P HTC, ErlangenE-mail: [email protected]
Dr. Rainer DudekFraunhofer ENAS, Micro Materials Center Berlin and ChemnitzE-mail: [email protected]
Dr. Sven RzepkaFraunhofer ENAS, Micro Materials Center Berlin and ChemnitzE-mail: [email protected]
• Thermo-Mechanical Reliability Assessment for 3D Through-Si Stacking, R. Dudek et al.EuroSimE 2009, Delft, April 2009
• Virtual Prototyping in Microelectronics and Packaging, S. Rzepka et al., 33th International Conference and Exhibition IMAPS – Poland 2009, 21-24 September 2009