1

Transistors for VLSI, for Wireless:

A View Forwards Through Fog

Mark Rodwell, UCSB

Plenary, Device Research Conference, June 22, 2015, Ohio State

InP HBT: J. Rode**, P. Choudhary, A.C. Gossard, B. Thibeault, W. Mitchell: UCSB M. Urteaga, B. Brar: Teledyne Scientific and Imaging

III-V MOS C.-Y. Huang, S. Lee*, A.C. Gossard, V. Chobpattanna, S. Stemmer, B. Thibeault, W. Mitchell : UCSB

Low-voltage devices P. Long, E. Wilson, S. Mehrotra, M. Povolotskyi, G. Klimeck: Purdue

Now with: *IBM, **Intel

2

Co-authors

In(Ga)As MOS THz InP HBT

Steep FET design Process

Cheng-Ying Huang

Sanghoon Lee

Varista Chobpattanna

Prof. Susanne Stemmer

Johann Rode

Prateek Choudhary

Pengyu Long

Prof. Michael Povolotski

Prof. Gerhard Klimeck

III-V EPI

Brian Thibeault

Bill Mitchell

Prof. Art Gossard

..and at Teledyne (HBT): Miguel Urteaga, Bobby Brar

Evan Wilson

3

What's a Professor to do ?

Transistors approaching scaling limits

Process technology: it's getting hard. extreme resolution, complex process, many steps exhausted students

How can we steer the future of VLSI, of wireless ?

Beyond yet another new semiconductor (be it 3D or 2...)

let's explore other options.

4

VLSI

4

5

What does VLSI need ?

Small transistors: plentiful, cheap

Small transistors→ short wires small delay CVDD /I low energy CVDD

2/2

Small-area electronics is key

Low leakage current thermal: Ioff > Ion*exp(-qVDD/kT) want low VDD yet low Ioff.

0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

Vgs

I d, A

mps/m

ete

r

0 0.1 0.2 0.3 0.4 0.510

-1

100

101

102

103

Vgs

60

mV/decade

Want: Large dI/dV above threshold Steeper than thermal below threshold

6

First: Steep-subthreshold-swing transistors

Characteristics steeper than thermal→ lower supply voltage

0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

60

mV/decade

0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

Vgs

I d, A

mps/m

ete

r

7

Tunnel FETs: truncating the thermal distribution

Source bandgap truncates thermal distribution

J. Appenzeller et al., IEEE TED, Dec. 2005

T-FET

Normal

Must cross bandgap: tunneling

Fix (?): broken-gap heterojunction

8

Tunnel FETs: are prospects good ?

Useful devices must be small

Quantization shifts band edges→ tunnel barrier

Band nonparabolicity increases carrier masses

Electrostatics: bands bend in source & channel

What actual on-current might we expect ?

9

Tunneling Probability

barrier

barrier

*2 where),2exp(

barrier) square (WKB,y Probabiliton Transmissi

EmTP

barrier thick 4nm afor %1

barrier thick 2nm afor %10

barrier thick 1nm afor %33

:Then

eV 2.0 ,06.0* :Assume 0

P

Emm b

For high Ion, tunnel barrier must be *very* thin.

~3-4nm minimum barrier thickness: P+ doping, body & dielectric thicknesses

10

T-FET on-currents are low, T-FET logic is slow

-1.5

-1

-0.5

0

0.5

1

1.5

2

5 10 15 20 25

En

erg

y, eV

position, nm10

-310

-210

-110

0

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

Transmission

En

erg

y(e

V)

3.0%

NEMO simulation: GaSb/InAs tunnel finFET: 2nm thick body, 1nm thick dielectric @ er=12, 12nm Lg

10-5

10-4

10-3

10-2

10-1

100

101

102

0 0.1 0.2 0.3 0.4 0.5 0.6

dra

in c

urr

en

t, A

/m

gate-source bias, volts

60mV/dec.

10 mA/mm

Experimental: InGaAs heterojunction HFET; Dewey et al, 2011 IEDM, 2012 VLSI Symp.

~15 mA/mm @0.7V

Low current → slow logic

11

Resonant-enhanced tunnel FET Avci & Young, (Intel) 2013 IEDM

2nd barrier: bound state

dI/dV peaks as state aligns with source

improved subthreshold swing.

Can we also increase the on-current ?

12

Electron anti-reflection coatings

Tunnel barrier: transmission coefficient < 100% reflection coefficient > 0% want: 100% transmission, zero reflection familiar problem

Optical coatings reflection from lens surface quarter-wave coating, appropriate n reflections cancel

Microwave impedance-matching reflection from load quarter-wave impedance-match no reflection Smith chart.

13

T-FET: single-reflector AR coating

Peak transmission approaches 100%

Narrow transmission peak; limits on-current

10-3

10-2

10-1

100

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

TransmissionE

ne

rgy(e

V)

TFET

TFET+ one barrier10

-5

10-4

10-3

10-2

10-1

100

101

102

0 0.1 0.2 0.3 0.4 0.5

dra

in c

urr

ent,

A/m

gate-source bias, volts

60mV/dec.

TFET

+one barrier

Can we do better ?

14

Limits to impedance-matching bandwidth

-7

-6

-5

-4

-3

-2

-1

0

1

0 5 10 15 20

Tra

nsm

issio

n,

dB

Frequency, GHz

1, 2, 3 sections

Microwave matching: More sections→ more bandwidth Is there a limit ?

Bode-Fano limits R. M. Fano, J. Franklin Inst., Jan. 1960

Bound bandwidth for high transmission example: bound for RC parallel load→ Do electron waves have similar limits ?

0

2||||

1ln

RCd

Yes ! Schrödinger's equation is isomorphic to E&M plane wave. Khondker, Khan, Anwar, JAP, May 1988

T-FET design→ microwave impedance-matching problem Fano: limits energy range of high transmission Design T-FETs using Smith chart, optimize using filter theory Working on this: for now design by random search

)/*)(/()( wherepower,currenty probabilit , , , / xjmxIVfhE *

15

T-FET with 3-layer antireflection coating

-1.5

-1

-0.5

0

0.5

1

1.5

2

5 10 15 20 25 30 35

En

erg

y, e

V

position, nm10

-310

-210

-110

00.1

0.15

0.2

0.25

Transmission

En

erg

y(e

V) 3-layer

0-layer

10-5

10-4

10-3

10-2

10-1

100

101

102

0 0.1 0.2 0.3 0.4 0.5 0.6

dra

in c

urr

en

t, A

/m

gate-source bias, volts

P-GaSb/N-InAs

tunnel FET

single layer

triple layer

60mV/dec.

Interim result; still working on design

Simulation

16

Source superlattice: truncates thermal distribution

Gnani, 2010 ESSDERC

M. Bjoerk et al., U.S. Patent 8,129,763, 2012. E. Gnani et al., 2010 ESSDERC

Proposed 1D/nanowire device:

Gnani, 2010 ESSDERC:

simulation

17

Planar (vs. nanowire) superlattice steep FET Long et al., EDL, Dec. 2014

Planar superlattice FET superlattice by ALE regrowth easier to build than nanowire (?)

Performance (simulations): ~100% transmission in miniband. 0.4 mA/mm Ion , 0.1mA/mm Ioff ,0.2V

Ease of fabrication ? Tolerances in SL growth ? Effect of scattering ?

simulation

18

What if steep FETs prove not viable ?

Instead, increase dI/dV above threshold. dI/dV: a.k.a. transconductance, gm. Reduced voltage, reduced CV2

0 0.1 0.2 0.3 0.4 0.50

200

400

600

800

1000

Vgs

I d, A

mps/m

ete

rSteep FETs will not be easy.

0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

60

mV/dec.

First: III-V MOS as (potential) high-(dI/dV) device

19

Why III-V MOS ?

III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering → higher current. Then trade for lower voltage or smaller FETs.

Problems: Low m*→ less charge. Low m* → more S/D tunneling. Narrow bandgap→ more band-band tunneling, impact ionization.

20

In(Ga)As: low m*→ high velocity → high current (?)

Ballistic on-current: Natori, Lundstrom, Antoniadis (Rodwell)

torsemiconduc

channel

ox 2

1

ee

TT

c

ox

equiv

valleys# g

More current unless dielectric, and body, are extremely thin.

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

norm

aliz

ed d

rive c

urr

en

t K

1

m*/mo

g=2

EET=1.0 nm

0.6 nm

0.4 nm

g=1

EET=Tox

eSiO2

/eox

+Tchannel

eSiO2

/2echannel

In(Ga)As thin {100} Si

2/3*

,

2/1*

1

2/3

1

)/()/(1

, V 1m

mA84

oequivodos

o

thgs

mmgcc

mmgK

VVKJ

m

21

Excellent III-V gate dielectrics

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

ea

ka

ge

| (A

/cm

2)

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse Sweep

Solid: Forward Sweep

Lg = 1 mm

61 mV/dec Subthreshold swing at VDS=0.1 V

Negligible hysteresis

2.5nm ZrO2

1nm Al2O3 2.5nm InAs

V. Chobpattanna, S. Stemmer FET data: S Lee, 2014 VLSI Symp.

22

Record III-V MOS

S. Lee et al., VLSI 2014

10 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014

J. Lin, IEDM 2013

T. Kim, IEDM 2013

Intel, IEDM 2009

J. Gu, IEDM 2012

D. Kim, IEDM 2012

I on (

mA

/mm

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/mm

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (

mS

/mm

)

Cu

rre

nt

De

ns

ity

(m

A/m

m)

Gate Bias (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0L

g = 25 nm

SS~ 72 mV/dec.

SS~ 77 mV/dec.

Ion= 500 mA/mm at Ioff

=100 nA/mm

and VD=0.5V

Vertical Spacer

N+ S/D

Lg~25 nm

record for III-V

= best UBT SOI silicon

23

Double-heterojunction MOS: 60 pA/mm leakage

• Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm

• 100:1 smaller Ioff compared to InGaAs spacer

• BTBT leakage suppressedisolation leakage dominates

Lg-30nm

C. Y. Huang et al., IEDM 2014

Lg-30nm

24

III-V MOS @ Lg = ???

Courtesy of S. Kraemer (UCSB)

Huang et al., this conference

25

High-current III-V PMOS

nm thickness [110]-oriented PMOS channels→ low transport mass

Very low m* Current approaching NMOS finFETs are naturally [110]

Silicon PMOS: Wang et al., IEEE TED 2006 (Intel) III-V: S. Mehrotra (Purdue), unpublished

simulation

26

Minimum Dielectric Thickness & Gate Leakage

-6

-5.5

-5

-4.5

-4

-3.5

-3

-2.5

-2

eV

fro

m v

acu

um

leve

l

Si

InGaAs HfO2

TiO2

Ec

Ev

er ~20 e

r ~40

barrier

1

barrier *2 where),2exp(y Probabiliton Transmissi EmTP

→ 0.5-0.7nm minimum EOT constrains on-current electrostatics degrades with scaling → fins, nanowires

High-er materials have lower barriers

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

norm

aliz

ed d

rive c

urr

en

t K

1

m*/mo

g=2

EET=1.0 nm

0.6 nm

0.4 nm

g=1

EET=Tox

eSiO2

/eox

+Tchannel

eSiO2

/2echannel

Thin dielectrics are leaky

27

Quick check: scaling limits

finFET: 5 nm physical gate length. Channel: <100> Si, 0.5, 1, or 2nm thick dielectric: er=12.7, 0.5 or 0.7 nm EOT

60

65

70

75

80

0 0.5 1 1.5 2 2.5

Dielectric: 0.5 nm EOT

su

bth

resh

old

sw

ing

, m

V/d

eca

de

body thickness, nm

thermionic+

tunneling

thermionic

only

5nm gate length

<100> Si finFET

0 0.5 1 1.5 2 2.5

Dielectric: 0.7nm EOT

body thickness, nm

thermionic+

tunneling

thermionic

only

NEMO ballistic simulations

Given EOT limits, ~1.5-2nm body is acceptable.

Source-drain tunneling often dominates leakage.

simulation

28

Do 2-D semiconductors help ?

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

norm

aliz

ed d

rive c

urr

en

t K

1

m*/mo

g=2isotropic

EET=1.0 nm

0.6 nm

0.4 nm

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive

cu

rre

nt,

K1

normalized effective mass m*/mo

EET=1.0 nm

0.6 nm0.4 nm g=6

isotropic

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive

cu

rre

nt,

K1

normalized longitudinal transport mass mL/m

o

EET=1.0 nm

0.6 nm0.4 nm

EET=Tox

eSiO2

/eox

+Tchannel

eSiO2

/2echannel

g=1transverse mass

=2.6*mo

Silic

on

M

oS 2

P

ho

sph

ore

ne

2/32/1

||

2/1

,

2/12/1

2/3

)/()/(1

)/( where

, V 1m

mA84

oequivodos

o

thgs

mmmgcc

mmgK

VVKJ

m

3D: Is body thickness a scaling limit ? recall the previous slide

If oxides won't scale, we must make fins with 2D, can we make fins ? later, will need to make nanowires...

Ballistic drive currents don't win either high m*, and/or high DOS mobility sufficient for ballistic ?

29

When it gets crowded, build vertically

2-D integration: wire length # gates1/2

Los Angeles: sprawl Manhattan: dense

3-D integration: wire length #gates1/3

LA is interconnect-limited

1) Chip stacking (skip) 2) 3D transistor integration

30

Corrugated surface→ more surface per die area

31

Corrugated surface→ more current per unit area

Cohen-Elias et al., UCSB 2013 DRC

J .J. Gu et al., 2012 DRC, Purdue 2012 IEDM

32

3D→shorter wires→less capacitance→less CV2

All three have same drive current, same gate width

Tall fin, "4-D": smaller footprint→ shorter wires

33

Corrugation: same current, less voltage, less CV2

0 0.1 0.2 0.3 0.4 0.5

10-1

100

101

102

103

Vgs

60mV/decade

I d,

Am

ps p

er

me

ter

of

FE

T f

oo

tprin

t w

idth

0 0.1 0.2 0.3 0.4 0.5

10-1

100

101

102

103

104

Vgs

I d,

Am

ps p

er

me

ter

of

FE

T f

ootp

rin

t w

idth

0 0.1 0.2 0.3 0.4 0.5

10-1

100

101

102

103

104

Vgs

10:1

corrugation

I d,

Am

ps p

er

me

ter

of

FE

T f

ootp

rin

t w

idth

34

Industry is moving to taller fins.

http://techreport.com/review/26896/intel-broadwell-processor-revealed

35

Fixing source-drain tunneling by increasing mass ?

Source-drain tunneling leakage:

)(*2 where),2exp( 1

thgoff qVmLI

2/1*constant gg LmL

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

norm

aliz

ed d

rive c

urr

en

t K

1

m*/mo

g=2

EET=1.0 nm

0.6 nm

0.4 nm

g=1

EET=Tox

eSiO2

/eox

+Tchannel

eSiO2

/2echannel

Fix by increasing effective mass ?

This will decrease the on-current:

?

!

long gate→ big

shorter gate→ smaller

less current

wider→ more current

big again !

(also increases transit time)

36

Fixing source-drain tunneling by corrugation

Transport distance > gate footprint length Only small capacitance increase

37

RF/Wireless

38

mm-Waves: high-capacity mobile communications

Needs→ research: RF front end: phased array ICs, high-power transmitters, low-noise receivers IF/baseband: ICs for multi-beam beamforming, for ISI/multipath suppression, ...

wide, useful bandwidths from 60 to ~300 GHz

39

mm-Wave CMOS won't scale much further

Gate dielectric can't be thinned → on-current, gm can't increase

Tungsten via resistances reduce the gain Inac et al, CSICS 2011

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive

cu

rre

nt

K1

m*/mo

EET=1.0 nm

0.6 nm

0.4 nm

g=1

EET=Tox

eSiO2

/eox

+Tchannel

eSiO2

/2echannel

0.3 nm

Shorter gates give no less capacitance dominated by ends; ~1fF/mm total

Maximum gm, minimum C→ upper limit on ft. about 350-400 GHz.

Present finFETs have yet larger end capacitances

40

III-V high-power transmitters, low-noise receivers

Cell phones & WiFi: GaAs PAs, LNAs

mm-wave links need high transmit power, low receiver noise

0.47 W @86GHz

0.18 W @220GHz

1.9mW @585GHz M Seo, TSC, IMS 2013

T Reed, UCSB, CSICS 2013

H Park, UCSB, IMS 2014

41

Making faster bipolar transistors

to double the bandwidth: change

emitter & collector junction widths decrease 4:1

current density (mA/mm2) increase 4:1

current density (mA/mm) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

Narrow junctions.

Thin layers

High current density

Ultra low resistivity contacts

Teledyne: M. Urteaga et al: 2011 DRC

42

THz HBTs: The key challenges

Obtaining good base contacts in full HBT process flow (vs. in TLM structure)

1018

1019

1020

1021

P-InGaAs

10-10

10-9

10-8

10-7

10-6

10-5

Hole Concentration, cm-3

B=0.8 eV

0.6 eV0.4 eV0.2 eV

step-barrierLandauer

Co

nta

ct

Re

sis

tivit

y,

cm

2

3THz target

Baraskar et al, Journal of Applied Physics, 2013

RC parasitics along finger length metal resistance, excess junction areas

43

THz InP HBTs blanket Pt/Ru base contacts: resist-free, cleaner surface → lower resistivity

J. Rode, in review

44

THz HEMTs: one more scaling generation ?

Xiaobing Mei, et al, IEEE EDL, April 2015 doi: 10.1109/LED.2015.2407193

First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process

45

nm & THz electronics

46

Electron devices: What's next ?

http://en.wikipedia.org/wiki/Standard_Model

Problems: oxide, S/D tunneling

~ l/n

deep UV absorption

lithography interconnect energy

& static dissipation

..electrostatic control of charge

...and communicating by E&M waves

Why transistors are best:

our best tools are:

Opportunities:

low voltages high currents nm via 3D RF→ THz

47

(backup slides follow)