By

Prof P P GhadekarVishwakarma Institute of Technology, Pune

Presentation Outline

Overview of VHDLVHDL Fundamentals

Libraries and PackagesEntities, Architectures, and ConfigurationsSignalsData TypesOperatorsEssential Language StatementsAdvanced Language Statements

VHDL ExamplesSynthesis Vs. Simulation

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Overview of VHDL

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V ery High Speed Integrated CircuitH ardwareD escriptionL anguage

VHDL language can be regarded as combination of followinglanguages

Sequential Language+Concurrent Language+Netlist Language+Timing Specifications+Waveform genration Language+

VHDL is a language that can be used to describe the structureand / or behaviour of hardware designsVHDL designs can be simulated and / or synthesized VHDLHierarchical use of VHDL designs permits the rapid creation ofcomplex hardware designs

History of VHDL

VHDL was developed by the VHSIC (Very High Speed IntegratedCircuit) Program in the late 1970s and early 1980sVHDL was designed to be a documentation and simulation languageVHDL is now used widely by industry and academia for bothsimulation and synthesisTwo versions of VHDL have been standardized by the IEEE:

• VHDL87 - IEEE-1076-1987• VHDL93 - IEEE-1076-1993

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Features of VHDL

VHDL has powerful constructsIn VHDL, design may be decomposed hierarchicallyEach design elements has a well defined interface useful for connecting it to other elements.Test bench is available for SimulationVHDL handles asynchronous & synchronous sequential circuits.In VHDL, concurrency, timing and clocking can be modeled.In VHDL, design is target independent.VHDL support design library.The language is not case sensitive.A Formal Language for Specifying the Behavior and Structure of a Digital CircuitAllows Top-Down Design

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Libraries and Packages

Libraries provide a set of hardware designs, components, and functionsthat simplify the task of designingPackages provide a collection of commonly used data types andsubprograms used in a designThe following is an example of the use of the IEEE library and itsSTD_LOGIC_1164 package:

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

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Entities, Architectures, and Configurations

• The structure of a VHDL design resembles the structure ofa modern, object-oriented software design in the sense thatevery VHDL design describes both an external interfaceand an internal implementation

• A VHDL design consists of entities, architectures, andconfigurations

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Entities

An Entity is something that has separate real existence.An entity is a specification of the design’s external interface.Entity declarations specify the following:

• Name of the entity• Set of port declarations defining the inputs and outputs to the

hardware designThe following is an example of an entity declaration:

ENTITY andgate IS

PORT (

a : IN STD_LOGIC;

b : IN STD_LOGIC;

c : OUT STD_LOGIC );

END andgate;

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Architectures

An architecture is a specification of the design’s internal implementationMultiple architectures can be created for a particular entityThe following is an example of an architecture declaration:

ARCHITECTURE r001 OF andgate IS

BEGINc <= a AND b;

END r001;

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Entity-Architecture Pair

entity name port names port mode (direction)port type

reserved words

punctuation

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VHDL Program Structure

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Ports

Port name choices:Consist of letters, digits, and/or underscoresAlways begin with a letterCase insensitive

Port direction choices:IN Input portOUT Output portINOUT Bidirectional portBUFFER Buffered output port

Port signal type (suggested) choices:STD_LOGICSTD_LOGIC_VECTOR(<max> DOWNTO <min>)

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Configurations

A configuration is a specification of the mapping between an architecture and a particular instance of an entityA configuration exists for each entityThe default configuration maps the most recently compiled architecture to the entityConfigurations are often used to specify alternative simulation models for hardware designs

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Signals

Signals represent wires and storage elements within a VHDL designSignals may only be defined inside architecturesSignals are associated with a data typeSignals have attributes It holds a list of values, which includes current value of the signal, and a set of possible future values that are to be appears on the signal.Future values can be assigned to a signal using a signal assignment statement i.e. <=

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Process Statement

Process is a main concurrent statement in VHDL code.It describe the sequential behavior of the design.All statement within process executes sequentially in zero time.Only one driver is placed on a signal.The signal is updated with the last value assigned to it with in the process. Syntax→ begin

process(sensitivity list)begin------------

end processSensitivity List- List of signal on which process should execute after

arranging its state. Every process must have either sensitivity list or waitstatement.

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Process Statements

-- Assume that the following ports exist for this entity

SIGNAL a, b, sel :IN STD_LOGIC;SIGNAL x, y :OUTSTD_LOGIC;

PROCESS (a, b, sel)-- a, b, and sel are in the sensitivity list to indicate-- that they are inputs to the process BEGINIF (a = ’0’) THEN -- Only valid in a process

x <= a OR b;ELSIF (b = ’0’) THEN

x <= a XNOR b;ELSE

x <= ’0’;END IF;

CASE sel IS -- Only valid in a processWHEN ‘0’ =>y <= a AND b;

WHEN OTHERS =>y <= ‘1’;

END CASE;END PROCESS;

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Built-In Data Types

VHDL supports a rich set of built-in data types as well as user-defined data types.Built-in data types work well for simulation but not so well for synthesis

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Data Type Characteristics

BIT Binary, Unresolved

BIT_VECTOR Binary, Unresolved, Array

INTEGER Binary, Unresolved, Array

REAL Floating Point

Examples:A: in bit;G: out boolean;D: in bit_vector(0 to 7);E: in bit_vector(7 downto 0);

STD_LOGIC_1164 Data Types

STD_LOGIC_1164 is a standardized package that implements a set of data types

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Data Type Characteristics

STD_ULOGIC MVL – 9, Unresolved

STD_ULOGIC_VECTOR MVL – 9, Unresolved, Array

STD_LOGIC MVL – 9, Resolved

STD_LOGIC_VECTOR MVL – 9, Resolved, Array

IEEE recommends the use of the STD_LOGIC and STD_LOGIC_VECTOR data types

Logical Operators

VHDL supports the following logical operators:ANDORXORXNORNOTNANDNOR

VHDL also supports the overloading of existing operators and the creation of new ones

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Assignment Statements

SIGNAL x, y, z : STD_LOGIC;SIGNAL a, b, c : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL sel : STD_LOGIC_VECTOR(2 DOWNTO 0);

-- Concurrent Signal Assignment Statements-- NOTE: Both x and a are produced concurrentlyx <= y AND z;a <= b OR c;

-- Alternatively, signals may be assigned constantsx <= ’0’;y <= ’1’;z <= ’Z’;a <= "00111010"; -- Assigns 0x3A to ab <= X"3A"; -- Assigns 0x3A to bc <= X"3" & X"A"; -- Assigns 0x3A to c

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Assignment Statements (cont.)SIGNAL x, y, z :STD_LOGIC;SIGNAL a, b, c :STD_LOGIC_VECTOR( 7 DOWNTO 0);SIGNAL sel :STD_LOGIC_VECTOR( 2 DOWNTO 0);

-- Conditional Assignment Statement-- NOTE: This implements a tree structure of logic gatesx <= ’0’ WHEN sel = “000” ELSE

y WHEN sel = “011” ELSEz WHEN x = ’1’ ELSE’1’;

-- Selected Signal Assignment Statement-- NOTE: The selection values must be constantsWITH sel SELECTx <= ’0’ WHEN “000”,

y WHEN “011”,z WHEN “100”,’1’ WHEN OTHERS;

-- Selected signal assignments also work with vectorsWITH x SELECTa <= “01010101” WHEN ’1’,

b WHEN OTHERS;

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AND-NAND Example

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Different Modeling Styles

The architectural body between begin and end can have only one of the following modeling stylesBehavioral ModelingData flow ModelingStructural Modeling

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Behavioral Style of Modeling

• The behavioral style of modeling specifies the behavior of an entity as a set of statement that are executed sequentially in the specified order.

• A ‘Process’ statement is a key element in the behavioral modeling. A process statement contains a set of sequential statements which specify the functionality of the model and not the exact structure of it.

• Process Statement is a concurrent statement which executes in parallel With other concurrent statement s and other processes.

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Data flow style of Modeling

• In this type of modeling , the flow of the data is expressed primarilyusing concurrent signal assignment statements. The structure of theentity is not explicitly specified in this type of modeling but it isinferred from the equation.

• The primary difference between Behavioral and Data flow modeling isthat Behavioral modeling uses processes and other does not.

• Data flow description are used in the cases where we have simpledesign equations of the circuit.

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Structural style of Modeling

• An architecture that uses components is often called as Structuralmodeling.

• It defines the precise interconnection structure of signals and entitieswithin that entity.

• A pure Structural description is equivalent to a schematic diagram ornet list of the circuit.

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Complete Example

• Example 1 -- A Package with a procedure modeling the functionality of an OR gate

package gate isprocedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit);

end gate;

package body gate isprocedure Or_gate(signal In1, In2 : bit; signal Out1 : out bit) isbegin

Out1 <= In1 or In2;end Or_gate;

end gate;

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Half Adder

• Example 2 -- Behavioral Description of a Half Adderentity Half_adder is

generic (AB_to_sum : TIME := 0 ns;AB_to_carry : TIME := 0 ns);

port ( A : in bit;B : in bit;Sum : out bit;Carry : out bit);

end Half_adder;

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Half Adder (contd.)

architecture Behavioral of Half_adder isbegin

processbegin

Sum <= A xor B after AB_to_sum;Carry <= A and B after AB_to_carry;wait on A,B;

end process;end Behavioral;

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Full Adder• Example 2 -- Structural Description of a Full Adder that instantiates

Half Adder and Uses procedure Or_gate from the package gate.

use WORK.gate.all; -- use the Package gateentity Full_adder is

port (A : in bit;B : in bit;Carry_in : in bit;Sum : out bit;Carry_out : out bit);

end Full_adder;

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Full Adder (contd.)architecture structural of Full_adder iscomponent Half_adder

generic (AB_to_sum : TIME := 0 ns;AB_to_carry : TIME := 0 ns

);port (

A : in bit;B : in bit;Sum : out bit;Carry : out bit

);end component;for all : Half_adder use entity work.Half_adder(behavioral);

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Full Adder (contd.)

signal Temp_sum : bit;signal Temp_carry1 : bit;signal Temp_carry2 : bit;

beginU0 : Half_adder generic map (5 ns, 5 ns)port map (A, B, Temp_sum, Temp_carry1);

U1 : Half_adder generic map (5 ns, 5 ns)port map (A => Temp_sum, B => Carry_in, Sum => Sum, Carry => Temp_carry2);

U3 : Or_gate ( Temp_carry1, Temp_carry2, Carry_out);end structural;

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Test Bench

library STD;use STD.standard.all;use STD.textio.all;library testpackage;use testpackage.testpackage.all;

entity fa_test is -- Entity for the test benchend fa_test;architecture bench of fa_test iscomponent Full_adder -- Component declaration for Full Adder

port (A : in bit; B : in bit; Carry_in : in bit;Sum : out bit; Carry_out : out bit

);end component;

for all : Half_adder use entity work.Full_adder(Structural

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Test Bench (contd.)signal A, B, Carry_in : bit;signal Sum, Carry_out : bit;signal temp : bit_vector(0 to 31);begina1: Full_adder port map ( A, B, Carry_in, Sum, Carry_out);

A <= temp(31);B <= temp(30);Carry_in <= temp(29);

a2: processvariable sttr : line;variable rando : integer;file dataout : text is out "data.out";

beginrando := 1;

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Test Bench (contd.)for i in 0 to 40 loop

temp <= int2vec(rando);rando := (rando * 3)/2 +1;wait for 1 ms;write(sttr, string('(" A = ")); write(sttr, A);write(sttr, string('(" B = ")); write(sttr, B);write(sttr, string('(" Carry_in = ")); write(sttr, Carry_in);write(sttr, string('(" Sum = ")); write(sttr, Sum);write(sttr, string('(" Carry_out = ")); write(sttr, Carry_out);writeline (dataout, sttr);wait for 0 ns;

end loop;wait;

end process;end bench;

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Basic VHDL Concepts

• Interfaces• Behavior• Structure• Test Benches• Analysis, elaboration, simulation• Synthesis

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Modeling Interfaces

• Entity declaration– describes the input/output ports of a module

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end entity reg4;

entity name port names port mode (direction)

port typereserved words

punctuation

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VHDL-87

• Omit entity at end of entity declaration

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end reg4;

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Modeling Behavior

• Architecture body– describes an implementation of an entity– may be several per entity

• Behavioral architecture– describes the algorithm performed by the module– contains

• process statements, each containing• sequential statements, including• signal assignment statements and• wait statements

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Behavior Example

architecture behav of reg4 isbegin

storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;

beginif en = '1' and clk = '1' then

stored_d0 := d0;stored_d1 := d1;stored_d2 := d2;stored_d3 := d3;

end if;q0 <= stored_d0 after 5 ns;q1 <= stored_d1 after 5 ns;q2 <= stored_d2 after 5 ns;q3 <= stored_d3 after 5 ns;wait on d0, d1, d2, d3, en, clk;

end process storage;end architecture behav;

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VHDL-87

• Omit architecture at end of architecture body• Omit is in process statement header

architecture behav of reg4 isbegin

storage : process...

begin...

end process storage;end behav;

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Modeling Structure

• Structural architecture– implements the module as a composition of subsystems– contains

• signal declarations, for internal interconnections– the entity ports are also treated as signals

• component instances– instances of previously declared entity/architecture pairs

• port maps in component instances– connect signals to component ports

• wait statements

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Structure Example

int_clk

d0

d1

d2

d3

en

clk

q0

q1

q2

q3

bit0d_latchd

clk

q

bit1d_latchd

clk

q

bit2d_latchd

clk

q

bit3d_latchd

clk

q

gateand2

a

b

y

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Structure Example

• First declare D-latch and and-gate entities and architectures

entity d_latch isport ( d, clk : in bit; q : out bit );

end entity d_latch;

architecture basic of d_latch isbegin

latch_behavior : process isbegin

if clk = ‘1’ thenq <= d after 2 ns;

end if;wait on clk, d;

end process latch_behavior;end architecture basic;

entity and2 isport ( a, b : in bit; y : out bit );

end entity and2;

architecture basic of and2 isbegin

and2_behavior : process isbegin

y <= a and b after 2 ns;wait on a, b;

end process and2_behavior;end architecture basic;

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Structure Example

• Now use them to implement a registerarchitecture struct of reg4 is

signal int_clk : bit;begin

bit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 );

bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 );

bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 );

bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 );

gate : entity work.and2(basic)port map ( en, clk, int_clk );

end architecture struct;

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VHDL-87

• Can’t directly instantiate entity/architecture pair• Instead

– include component declarations in structural architecture body

• templates for entity declarations– instantiate components– write a configuration declaration

• binds entity/architecture pair to each instantiated component

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Structure Example in VHDL-87

• First declare D-latch and and-gate entities and architectures

entity d_latch isport ( d, clk : in bit; q : out bit );

end d_latch;

architecture basic of d_latch isbegin

latch_behavior : processbegin

if clk = ‘1’ thenq <= d after 2 ns;

end if;wait on clk, d;

end process latch_behavior;end basic;

entity and2 isport ( a, b : in bit; y : out bit );

end and2;

architecture basic of and2 isbegin

and2_behavior : processbegin

y <= a and b after 2 ns;wait on a, b;

end process and2_behavior;end basic;

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Structure Example in VHDL-87

• Declare corresponding components in register architecture body

architecture struct of reg4 iscomponent d_latch

port ( d, clk : in bit; q : out bit );end component;component and2

port ( a, b : in bit; y : out bit );end component;signal int_clk : bit;

...

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Structure Example in VHDL-87

• Now use them to implement the register

...begin

bit0 : d_latchport map ( d0, int_clk, q0 );

bit1 : d_latchport map ( d1, int_clk, q1 );

bit2 : d_latchport map ( d2, int_clk, q2 );

bit3 : d_latchport map ( d3, int_clk, q3 );

gate : and2port map ( en, clk, int_clk );

end struct;

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Structure Example in VHDL-87

• Configure the register model

configuration basic_level of reg4 isfor struct

for all : d_latchuse entity work.d_latch(basic);

end for;for all : and2

use entity work.and2(basic)end for;

end for;end basic_level;

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Mixed Behavior and Structure

• An architecture can contain both behavioral and structural parts

– process statements and component instances• collectively called concurrent statements

– processes can read and assign to signals

• Example: register-transfer-level model– data path described structurally– control section described behaviorally

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Mixed Example

shift_reg

reg

shift_adder

control_section

multiplier multiplicand

product

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Mixed Exampleentity multiplier is

port ( clk, reset : in bit;multiplicand, multiplier : in integer;product : out integer );

end entity multiplier;

architecture mixed of mulitplier issignal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;

beginarith_unit : entity work.shift_adder(behavior)

port map ( addend => multiplicand, augend => full_product,sum => partial_product,add_control => arith_control );

result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,

en => result_en, reset => reset );...

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Mixed Example…multiplier_sr : entity work.shift_reg(behavior)

port map ( d => multiplier, q => mult_bit,load => mult_load, clk => clk );

product <= full_product;

control_section : process is-- variable declarations for control_section-- …

begin-- sequential statements to assign values to control signals-- …wait on clk, reset;

end process control_section;end architecture mixed;

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